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JPS6158967B2 - - Google Patents
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JPS6158967B2 - - Google Patents

Info

Publication number
JPS6158967B2
JPS6158967B2 JP56094738A JP9473881A JPS6158967B2 JP S6158967 B2 JPS6158967 B2 JP S6158967B2 JP 56094738 A JP56094738 A JP 56094738A JP 9473881 A JP9473881 A JP 9473881A JP S6158967 B2 JPS6158967 B2 JP S6158967B2
Authority
JP
Japan
Prior art keywords
manufacturing
ionized
vapor
semiconductor
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56094738A
Other languages
Japanese (ja)
Other versions
JPS57208126A (en
Inventor
Yoshuki Fukumoto
Yoji Kono
Masahiro Hotsuta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sekisui Chemical Co Ltd
Original Assignee
Sekisui Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sekisui Chemical Co Ltd filed Critical Sekisui Chemical Co Ltd
Priority to JP56094738A priority Critical patent/JPS57208126A/en
Publication of JPS57208126A publication Critical patent/JPS57208126A/en
Publication of JPS6158967B2 publication Critical patent/JPS6158967B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34Deposited materials, e.g. layers
    • H10P14/3402Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411Silicon, silicon germanium or germanium
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/24Vacuum evaporation
    • C23C14/32Vacuum evaporation by explosion; by evaporation and subsequent ionisation of the vapours, e.g. ion-plating
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/22Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using physical deposition, e.g. vacuum deposition or sputtering

Landscapes

  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Photovoltaic Devices (AREA)

Description

【発明の詳細な説明】 本発明は非晶質ケイ素半導体の製造方法に関す
る。 従来、非晶質ケイ素半導体はグロー放電分解
法、イオンスパツタリング法等で製造されている
が、該方法ではシランガス、水素ガス、アルゴン
ガス等の数トールから10-2トール程度の比較的真
空度の低い低圧雰囲気中に於けるプラズマを利用
しているので、非晶質ケイ素層は不純物が混入
し、膜質が悪く、導電性が不均一であり、熱的に
不安定であるという欠点を有していた。本発明は
上記欠点に鑑み、膜質が良く、導電性が均一であ
り、熱的に安定な非晶質ケイ素層を有する半導体
の製造方法を提供せんとしてなされたものであつ
て、その要旨は5×10-5トール以下に排気された
高真空中においてケイ素を加熱し、蒸気化し、次
いで該蒸気に電子放射源からの加速電子を衝突せ
しめることによりイオン化し、更に該イオン化蒸
気粒子を電界加速して1〜104evの運動エネルギ
ーを付与し基材上に、該基材の法線に対し31〜74
゜の入射角で衝突せしめ非晶質ケイ素層を形成す
ることを特徴とする半導体の製造方法に存する。 以下図面を参照して本発明の半導体の製造方法
について説明する。第1図は本発明の方法を実施
するための装置の一例を示す模型図である。図中
1は真空槽であり、排気口2が設けられている。
排気口2は油回転ポンプ、油拡散ポンプ等の排気
装置(図示せず)に接続されており、真空槽1内
を5×10-5トール以下の高真空になるように排気
することができるようになされている。真空槽1
内には蒸着イオン源3と角度を自由に変化できる
ようになされたイオン加速電極4が設置されてい
る。 蒸着イオン源3は蒸気発生部5と蒸気イオン化
部6により構成されている。蒸気発生部5はケイ
素を蒸発するためのルツボ7とルツボ7を加熱す
るための180゜偏向Eガン8及びルツボ7の周囲
に設置されたルツボ7を冷却するための水冷銅ハ
ース9とから構成されている。 蒸気イオン化部6は、熱電子放出用フイラメン
ト10と、放出された電子を電界加速する網状電
極11と電界制御のためのガード12とケイ素イ
オンの飛散防止のための邪魔板13とから形成さ
れている。 又14,15,16は本装置を作動させるため
の電源である。 次に第1図に示した装置を用いて本発明により
半導体を製造する方法を説明する。まずイオン加
速電極4の表面に基材18を設置し、基材18の
法線に対し、ケイ素のイオン化蒸気粒子が31〜74
゜の入射角で衝突するようにイオン加速電極4を
固定する。 上記基材としては、たとえばポリ塩化ビニル、
ポリフツ化ビニル、酢酸セルロース、ポリエチレ
ンテレフタレート、ポリブチレンテレフタレー
ト、ポリエチレン、ポリプロピレン、ポリカーボ
ネート、ポリイミド、ポリエーテルサルフオン、
ポリバラパン酸等の高分子材料や磁器、陶器、ガ
ラス等のセラミツク材料やシリカ、アルミナ、塩
化ナトリウム等の無機化合物の結晶板などの表面
にアルミニウムや金などの導電性材料の薄膜を形
成したもの及びアルミニウム、タンタル、鉄、モ
リブデン、タングステン、ニツケル、金、銀等の
導電性材料があげられる。 次にルツボ7にケイ素17を供給し、排気口2
から排気し、真空槽1内を5×10-5トール以下の
高真空にし、電源14,15,16を入れ、水冷
銅ハース9に冷却水を流しながら180゜偏向Eガ
ン8を作動させてケイ素17を加熱する。ケイ素
17はその加熱温度に応じた蒸気圧で蒸気化し、
蒸気は拡散されて蒸気イオン化部6に達する。該
蒸気イオン化部6において電源15によりフイラ
メント10を通電加熱し、熱電子を放出させ、電
源16によりフイラメント10及びガード12に
負の直流電圧を印加し、網状電極11を接地し、
前記熱電子を電界加速して前記蒸気に衝突させ正
の荷電状態にイオン化し、イオン化蒸気粒子を作
製する。蒸気中のケイ素粒子は0.5〜50%イオン
化されてイオン化蒸気粒子となされるのが好まし
い。 次に電源14によりイオン加速電極4に対して
負の直流電圧を印加し、イオン化蒸気粒子に1〜
104eVの運動エネルギーを付与し、基材5に衝突
せしめる。この際基材5をイオン化蒸気粒子が基
材5の法線に対し31〜74゜で入射するように設置
すると、基材5表面に非晶質層が形成され半導体
が製造される。なお運動エネルギーは102〜103eV
であるのが好ましい。又非晶質ケイ素層の導電性
を向上せしめるために真空槽に極少量の水素ガス
又はフツ素ガスを導入してもよく、価電子制御を
行うためにホスフイン、ジボラン等を極少量添加
しても良い。 本発明の製造方法は上述の通りであるから、非
晶質ケイ素の層が基材上に不純物をほとんど含む
ことなく、均一に積層されるので、導電性が均一
であり、熱的に安定な非晶質ケイ素層を有する半
導体が容易に製造できる。 次に本発明の製造方法を実施例で説明する。 実施例 第1図で示した装置においてルツボ7に高純度
多結晶ケイ素塊(ケイ素含量99.99%)5g供給
し、基材18として真空蒸着法により500Åの厚
さの金薄膜が形成されたガラス板を入射角50゜で
衝突されるように設置し、第1表に示す条件で蒸
着して基材表面に2μのケイ素の非晶質層を有す
る半導体を得た。なお水素ガスを水素ボンベより
供給し製造の間第1表に示す水素ガス分圧に保つ
た。得られた半導体の比抵抗は3×105KΩcmで
あり、電子移動度は0.02cm2/V・secであつた。
次に得られた半導体を200℃で10時間加熱したか
比抵抗及び電子移動度の変化はなかつた。 【表】
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an amorphous silicon semiconductor. Conventionally, amorphous silicon semiconductors have been manufactured by glow discharge decomposition method, ion sputtering method, etc., but these methods use silane gas, hydrogen gas, argon gas, etc. in a relatively vacuum of several Torr to 10 -2 Torr. Since plasma is used in a low-pressure atmosphere with low temperature, the amorphous silicon layer has the drawbacks of being contaminated with impurities, having poor film quality, nonuniform conductivity, and thermal instability. had. In view of the above-mentioned drawbacks, the present invention has been made to provide a method for manufacturing a semiconductor having a thermally stable amorphous silicon layer with good film quality, uniform conductivity, and the gist thereof is as follows: Silicon is heated and vaporized in a high vacuum evacuated to a pressure below ×10 -5 Torr, and then the vapor is ionized by colliding with accelerated electrons from an electron radiation source, and the ionized vapor particles are further accelerated in an electric field. kinetic energy of 1 to 104 ev is applied to the base material, and 31 to 74 ev is applied to the normal to the base material.
The present invention resides in a semiconductor manufacturing method characterized in that an amorphous silicon layer is formed by colliding at an incident angle of .degree. DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor according to the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram showing an example of an apparatus for carrying out the method of the present invention. In the figure, 1 is a vacuum chamber, and an exhaust port 2 is provided.
The exhaust port 2 is connected to an exhaust device (not shown) such as an oil rotary pump or an oil diffusion pump, and can exhaust the inside of the vacuum chamber 1 to a high vacuum of 5×10 -5 Torr or less. It is done like this. Vacuum chamber 1
Inside, a vapor deposition ion source 3 and an ion accelerating electrode 4 whose angle can be freely changed are installed. The evaporation ion source 3 includes a steam generation section 5 and a steam ionization section 6. The steam generating section 5 is composed of a crucible 7 for evaporating silicon, a 180° deflection E gun 8 for heating the crucible 7, and a water-cooled copper hearth 9 installed around the crucible 7 for cooling the crucible 7. has been done. The steam ionization section 6 is formed of a filament 10 for emitting thermionic electrons, a mesh electrode 11 for accelerating emitted electrons with an electric field, a guard 12 for controlling the electric field, and a baffle plate 13 for preventing scattering of silicon ions. There is. Further, 14, 15, and 16 are power sources for operating this device. Next, a method for manufacturing a semiconductor according to the present invention using the apparatus shown in FIG. 1 will be explained. First, the base material 18 is installed on the surface of the ion accelerating electrode 4, and 31 to 74 silicon ionized vapor particles are
The ion accelerating electrode 4 is fixed so that the collision occurs at an incident angle of .degree. Examples of the base material include polyvinyl chloride,
Polyvinyl fluoride, cellulose acetate, polyethylene terephthalate, polybutylene terephthalate, polyethylene, polypropylene, polycarbonate, polyimide, polyether sulfon,
Thin films of conductive materials such as aluminum and gold are formed on the surfaces of polymeric materials such as polyvarapanic acid, ceramic materials such as porcelain, ceramics, and glass, and crystal plates of inorganic compounds such as silica, alumina, and sodium chloride; Examples of conductive materials include aluminum, tantalum, iron, molybdenum, tungsten, nickel, gold, and silver. Next, silicon 17 is supplied to the crucible 7, and the exhaust port 2
The inside of the vacuum chamber 1 is evacuated to a high vacuum of 5×10 -5 Torr or less, the power supplies 14, 15, and 16 are turned on, and the 180° deflection E gun 8 is operated while cooling water is flowing through the water-cooled copper hearth 9. Heat silicon 17. Silicon-17 is vaporized at a vapor pressure depending on its heating temperature,
The vapor is diffused and reaches the vapor ionization section 6. In the steam ionization section 6, the filament 10 is heated with electricity by the power source 15 to emit thermoelectrons, a negative DC voltage is applied to the filament 10 and the guard 12 by the power source 16, and the mesh electrode 11 is grounded.
The thermoelectrons are accelerated in an electric field, collide with the vapor, and are ionized into a positively charged state to produce ionized vapor particles. Preferably, 0.5 to 50% of the silicon particles in the vapor are ionized to form ionized vapor particles. Next, a negative DC voltage is applied to the ion accelerating electrode 4 by the power source 14, and the ionized vapor particles are
A kinetic energy of 10 4 eV is applied to cause the material to collide with the base material 5. At this time, if the base material 5 is placed so that the ionized vapor particles are incident at an angle of 31 to 74 degrees with respect to the normal to the base material 5, an amorphous layer is formed on the surface of the base material 5, and a semiconductor is manufactured. The kinetic energy is 10 2 to 10 3 eV
It is preferable that In addition, a very small amount of hydrogen gas or fluorine gas may be introduced into the vacuum chamber to improve the conductivity of the amorphous silicon layer, and a very small amount of phosphine, diborane, etc. may be added to control valence electrons. Also good. Since the manufacturing method of the present invention is as described above, the amorphous silicon layer is uniformly laminated on the base material with almost no impurities, so that the conductivity is uniform and the layer is thermally stable. A semiconductor having an amorphous silicon layer can be easily manufactured. Next, the manufacturing method of the present invention will be explained using examples. Example In the apparatus shown in FIG. 1, 5 g of high-purity polycrystalline silicon ingots (silicon content 99.99%) were supplied to the crucible 7, and a glass plate was formed with a 500 Å thick gold film as the base material 18 by vacuum evaporation. The substrate was placed so as to be collided with the substrate at an incident angle of 50°, and vapor deposition was performed under the conditions shown in Table 1 to obtain a semiconductor having a 2 μm thick silicon amorphous layer on the substrate surface. Note that hydrogen gas was supplied from a hydrogen cylinder and maintained at the hydrogen gas partial pressure shown in Table 1 during production. The specific resistance of the obtained semiconductor was 3×10 5 KΩcm, and the electron mobility was 0.02 cm 2 /V·sec.
Next, the obtained semiconductor was heated at 200°C for 10 hours, but there was no change in resistivity or electron mobility. 【table】

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の方法を実施するための装置の
一例を示す模型図である。 1……真空槽、2……排気口、3……蒸着イオ
ン源、4……イオン加速電極、5……蒸気発生
部、6……蒸気イオン化部、7……ルツボ、8…
…180゜偏向Eガン、9……水冷銅ハース、10
……熱電子放出用フイラメント、11……網状電
極、12……カード、13……邪魔板、14,1
5,16……電源、17……ケイ素、18……基
材。
FIG. 1 is a schematic diagram showing an example of an apparatus for carrying out the method of the present invention. DESCRIPTION OF SYMBOLS 1... Vacuum chamber, 2... Exhaust port, 3... Vapor deposition ion source, 4... Ion accelerating electrode, 5... Steam generation section, 6... Steam ionization section, 7... Crucible, 8...
...180° deflection E gun, 9...Water-cooled copper hearth, 10
...Thermionic emission filament, 11...Mesh electrode, 12...Card, 13...Baffle plate, 14,1
5, 16...Power supply, 17...Silicon, 18...Base material.

Claims (1)

【特許請求の範囲】 1 5×10-5トール以下に排気された高真空中に
おいて、ケイ素を加熱し、蒸気化し、次いで該蒸
気に電子放射源からの加速電子を衝突せしめるこ
とによりイオン化し、更に該イオン化蒸気粒子を
電界加速して1〜104evの運動エネルギーを付与
し基材上に、該基材の法線に対し31〜74゜の入射
角で衝突せしめ非晶質ケイ素層を形成することを
特徴とする半導体の製造方法。 2 イオン化蒸気粒子が蒸気粒子の0.5〜50%で
ある特許請求の範囲第1項記載の製造方法。 3 運動エネルギーが102〜103evである特許請求
の範囲第1項又は第2項記載の製造方法。
[Scope of Claims] In a high vacuum evacuated to 15×10 -5 Torr or less, silicon is heated and vaporized, and then ionized by bombarding the vapor with accelerated electrons from an electron radiation source, Furthermore, the ionized vapor particles are accelerated in an electric field to impart kinetic energy of 1 to 10 4 ev, and are caused to collide with the substrate at an incident angle of 31 to 74 degrees with respect to the normal to the substrate to form an amorphous silicon layer. A method for manufacturing a semiconductor, characterized by forming a semiconductor. 2. The manufacturing method according to claim 1, wherein the ionized vapor particles account for 0.5 to 50% of the vapor particles. 3. The manufacturing method according to claim 1 or 2, wherein the kinetic energy is 10 2 to 10 3 ev.
JP56094738A 1981-06-18 1981-06-18 Manufacture of semiconductor Granted JPS57208126A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56094738A JPS57208126A (en) 1981-06-18 1981-06-18 Manufacture of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56094738A JPS57208126A (en) 1981-06-18 1981-06-18 Manufacture of semiconductor

Publications (2)

Publication Number Publication Date
JPS57208126A JPS57208126A (en) 1982-12-21
JPS6158967B2 true JPS6158967B2 (en) 1986-12-13

Family

ID=14118448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56094738A Granted JPS57208126A (en) 1981-06-18 1981-06-18 Manufacture of semiconductor

Country Status (1)

Country Link
JP (1) JPS57208126A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6230315A (en) * 1985-07-31 1987-02-09 Anelva Corp Electron gun apparatus

Also Published As

Publication number Publication date
JPS57208126A (en) 1982-12-21

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