JPS6158968B2 - - Google Patents
Info
- Publication number
- JPS6158968B2 JPS6158968B2 JP56094739A JP9473981A JPS6158968B2 JP S6158968 B2 JPS6158968 B2 JP S6158968B2 JP 56094739 A JP56094739 A JP 56094739A JP 9473981 A JP9473981 A JP 9473981A JP S6158968 B2 JPS6158968 B2 JP S6158968B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- ionized
- vapor
- manufacturing
- base material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
- H10P14/3411—Silicon, silicon germanium or germanium
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/24—Vacuum evaporation
- C23C14/32—Vacuum evaporation by explosion; by evaporation and subsequent ionisation of the vapours, e.g. ion-plating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/22—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using physical deposition, e.g. vacuum deposition or sputtering
Landscapes
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Engineering & Computer Science (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Photovoltaic Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体の製造方法に関する。
従来、太陽電池等に使用されるケイ素半導体は
真空蒸着法、化学蒸着法、イオンスパツタリング
法等により製造されている。しかしながら上記の
方法では基材の温度は600℃以上の温度に加熱さ
れなければならず又表面がケイ素結晶の格好と略
同形であり、格子定数が類似しておりかつ清浄で
あることが必要なため特殊な基材しか使用できな
いという欠点があり又製膜速度が遅いという欠点
を有していた。
本発明は上記欠点に鑑み、400℃以下の低温で
任意の基材に単結晶のケイ素層を積層した半導体
を容易にかつ速く製造する方法を提供せんとして
なされたものであつて、その要旨は、５×10-5ト
ール以下に排気された高真空中においてケイ素を
加熱し、蒸気化し、次いで該蒸気に電子放射源か
らの加速電子を衝突せしめることによりイオン化
し、更に該イオン化蒸気粒子を電界加速して１〜
104eVの運動エネルギーを付与し基材上に、該基
材の法線に対し０〜30゜又は75〜89゜の入射角で
衝突せしめ単結晶ケイ素層を形成することを特徴
とする半導体の製造方法に存する。
以下図面を参照して本発明の半導体の製造方法
について説明する。第１図は本発明の方法を実施
するための装置の一例を示す模型図である。図中
１は真空槽であり、排気口２が設けられている。
排気口２は油回転ポンプ、油拡散ポンプ等の排気
装置（図示せず）に接続されており、真空槽１内
を５×10-5トール以下の高真空になるように排気
することができるようになされている。真空槽１
内には蒸着イオン源３と角度を自由に変化できる
ようになされたイオン加速電極４が設置されてい
る。
蒸着イオン源３は蒸気発生部５と蒸気イオン化
部６により構成されている。蒸気発生部５はケイ
素を蒸発するためのルツボ７とルツボ７を加熱す
るための180゜偏向Ｅガン８及びルツボ８及びル
ツボ７の周囲に設置されたルツボ７を冷却するた
めの水冷銅ハース９とから構成されている。
蒸気イオ化部６は、熱電子放出用フイラメント
１０と、放出された電子を電界加速する網状電極
１１と電界制御のためのガード１２とケイ素イオ
ンの飛散防止のための邪魔板１３とから形成され
ている。
又１４，１５，１６は本装置を作動させるため
の電源である。
次に第１図に示した装置を用いて本発明により
半導体を製造する方法を説明する。まずイオン加
速電極４の表面に基材１８を設置し、基材１８の
法線に対し、ケイ素のイオン化蒸気粒子が０〜30
゜又は75〜89゜の入射角で衝突するようにイオン
加速電極４を設置する。
上記基材としては、たとえばポリ塩化ビニル、
ポリフツ化ビニル、酢酸セルロース、ポリエチレ
ンテレフタレート、ポリブチレンテレフタレー
ト、ポリエチレン、ポリプロピレン、ポリカーボ
ネート、ポリイミド、ポリエーテルサルフオン、
ポリパラバン酸等の高分子材料や磁器、陶器、ガ
ラス等のセラミツク材料やシリカ、アルミナ、塩
化ナトリウム等の無機化合物の結晶板などの表面
にアルミニウムや金などの導電性材料の薄膜を形
成したもの及びアルミニウム、タンタル、鉄、モ
リブデン、タングステン、ニツケル、金、銀等の
導電性材料があげられる。
次にルツボ７にケイ素１７を供給し、排気口２
から排気し、真空槽１内を５×10-5トール以下の
高真空にし、電源１４，１５，１６を入れ、水冷
銅ハース９に冷却水を流しながら180゜偏向Ｅガ
ン８を作動させてケイ素１７を加熱する。ケイ素
１７はその加熱温度に応じた蒸気圧で蒸気化し、
蒸気は拡散されて蒸気イオン化部６に達する。該
蒸気イオン化部６において、電源１５によりフイ
ラメント１０を通電加熱し、熱電子を放出させ、
電源１６によりフイラメント１０及びガード１２
に負の直流電圧を印加し、網状電極１１を接地
し、前記熱電子を電界加速して前記蒸気に衝突さ
せ正の荷電状態にイオン化し、イオン化蒸気粒子
を作製する。蒸気中のケイ素流子は0.5〜50％イ
オン化されてイオン化蒸気粒子となされるのが好
ましい。
次に電源１４によりイオン加速電極４に対して
負の直流電圧を印加し、イオン化蒸気粒１〜
104eVの運動エネルギーを付与し、基材５に衝突
せしめる。この際基材５をイオン化蒸気材５の法
線に対し０〜30゜又は75〜89゜で入射するように
設置すると、基材５表面に単結晶層が形成され半
導体が製造される。なお運転エネルギーは102〜
103eVであるのが好ましい。本発明の製造方法は
上述の通りであるから、400℃以下の低温で任意
の基材に基材表面を前処理することなくケイ素の
単結晶層を容易にかつ速く積層することができ、
単結晶ケイ素層を有する半導体が容易に製造でき
る。
次に本発明の製造方法を実施例で説明する。
実施例
第１図で示した装置においてルツボ７に高純度
多結晶ケイ素塊（ケイ素含量99.99％）５ｇ供給
し、塩化ナトリウム単結晶のヘキ開面に真空蒸着
法により厚さ500Åの金薄膜が形成された塩化ナ
トリウム板を基材１８として前記金薄膜にイオン
化蒸気粒子が入射角０゜で衝突されるように設置
し、第１表に示す条件で蒸着して基材表面に１μ
のケイ素の単結晶層を有する半導体を得た。得ら
れた半導体の比抵抗は1700KΩcmであり、正孔移
動度は320cm2／Ｖ・secであつた。
【表】DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor. Conventionally, silicon semiconductors used in solar cells and the like have been manufactured by vacuum evaporation, chemical vapor deposition, ion sputtering, and the like. However, in the above method, the substrate must be heated to a temperature of 600°C or higher, and the surface must be approximately the same as that of a silicon crystal, have a similar lattice constant, and be clean. Therefore, it has the disadvantage that only special base materials can be used, and the film forming speed is slow. In view of the above-mentioned drawbacks, the present invention was made with the aim of providing a method for easily and quickly manufacturing a semiconductor in which a single crystal silicon layer is laminated on an arbitrary base material at a low temperature of 400°C or less, and the gist thereof is Silicon is heated and vaporized in a high vacuum evacuated to 5×10 -5 Torr or less, then ionized by bombarding the vapor with accelerated electrons from an electron radiation source, and the ionized vapor particles are then exposed to an electric field. Accelerate to 1~
A semiconductor characterized in that a single crystal silicon layer is formed by imparting kinetic energy of 10 4 eV and colliding it onto a substrate at an incident angle of 0 to 30° or 75 to 89° with respect to the normal to the substrate. It consists in the manufacturing method. DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor according to the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram showing an example of an apparatus for carrying out the method of the present invention. In the figure, 1 is a vacuum chamber, and an exhaust port 2 is provided.
The exhaust port 2 is connected to an exhaust device (not shown) such as an oil rotary pump or an oil diffusion pump, and can exhaust the inside of the vacuum chamber 1 to a high vacuum of 5×10 -5 Torr or less. It is done like this. Vacuum chamber 1
Inside, a vapor deposition ion source 3 and an ion accelerating electrode 4 whose angle can be freely changed are installed. The evaporation ion source 3 includes a steam generation section 5 and a steam ionization section 6. The steam generating section 5 includes a crucible 7 for evaporating silicon, a 180° deflection E gun 8 for heating the crucible 7, a water-cooled copper hearth 9 for cooling the crucible 8 and the crucible 7 installed around the crucible 7. It is composed of. The steam ionization section 6 is formed of a filament 10 for emitting thermionic electrons, a mesh electrode 11 for accelerating emitted electrons with an electric field, a guard 12 for controlling the electric field, and a baffle plate 13 for preventing scattering of silicon ions. ing. Further, 14, 15, and 16 are power sources for operating this device. Next, a method for manufacturing a semiconductor according to the present invention using the apparatus shown in FIG. 1 will be explained. First, the base material 18 is installed on the surface of the ion accelerating electrode 4, and ionized silicon vapor particles are 0 to 30 with respect to the normal to the base material 18.
The ion accelerating electrode 4 is installed so that the collision occurs at an incident angle of 75 to 89 degrees. Examples of the base material include polyvinyl chloride,
Polyvinyl fluoride, cellulose acetate, polyethylene terephthalate, polybutylene terephthalate, polyethylene, polypropylene, polycarbonate, polyimide, polyether sulfon,
Thin films of conductive materials such as aluminum and gold are formed on the surfaces of polymer materials such as polyparabanic acid, ceramic materials such as porcelain, ceramics, and glass, and crystal plates of inorganic compounds such as silica, alumina, and sodium chloride; Examples of conductive materials include aluminum, tantalum, iron, molybdenum, tungsten, nickel, gold, and silver. Next, silicon 17 is supplied to the crucible 7, and the exhaust port 2
The inside of the vacuum chamber 1 is evacuated to a high vacuum of 5×10 -5 Torr or less, the power supplies 14, 15, and 16 are turned on, and the 180° deflection E gun 8 is operated while cooling water is flowing through the water-cooled copper hearth 9. Heat silicon 17. Silicon-17 is vaporized at a vapor pressure depending on its heating temperature,
The vapor is diffused and reaches the vapor ionization section 6. In the steam ionization section 6, the filament 10 is electrically heated by the power source 15 to emit thermoelectrons,
The filament 10 and the guard 12 are powered by the power source 16.
A negative DC voltage is applied to the net electrode 11, the mesh electrode 11 is grounded, and the thermoelectrons are accelerated in an electric field so that they collide with the vapor and are ionized into a positively charged state, thereby producing ionized vapor particles. Preferably, the silicon flow particles in the vapor are ionized by 0.5 to 50% to form ionized vapor particles. Next, a negative DC voltage is applied to the ion accelerating electrode 4 by the power source 14, and the ionized vapor particles 1 to
A kinetic energy of 10 4 eV is applied to the base material 5 to cause it to collide with the base material 5. At this time, if the base material 5 is placed so that the light is incident at an angle of 0 to 30 degrees or 75 to 89 degrees with respect to the normal line of the ionized vapor material 5, a single crystal layer is formed on the surface of the base material 5, and a semiconductor is manufactured. The operating energy is 10 2 ~
Preferably it is 10 3 eV. Since the manufacturing method of the present invention is as described above, it is possible to easily and quickly laminate a single crystal layer of silicon on any base material at a low temperature of 400° C. or lower without pretreating the surface of the base material.
A semiconductor having a single crystal silicon layer can be easily manufactured. Next, the manufacturing method of the present invention will be explained using examples. Example In the apparatus shown in Fig. 1, 5 g of high-purity polycrystalline silicon ingot (silicon content 99.99%) was supplied to the crucible 7, and a thin gold film with a thickness of 500 Å was formed on the hexagonal surface of a single crystal of sodium chloride by vacuum evaporation. The sodium chloride plate obtained was placed as a base material 18 so that ionized vapor particles collided with the gold thin film at an incident angle of 0°, and vapor deposition was performed under the conditions shown in Table 1 to form a 1 μm film on the surface of the base material.
A semiconductor having a single crystal layer of silicon was obtained. The specific resistance of the obtained semiconductor was 1700 KΩcm, and the hole mobility was 320 cm 2 /V·sec. 【table】
第１図は本発明の方法を実施するための装置の
一例を示す模型図である。
１……真空槽、２……排気口、３……蒸着イオ
ン源、４……イオン加速電極、５……蒸気発生
部、６……蒸着イオン化部、７……ルツボ、８…
…180゜偏向Ｅガン、９……水冷銅ハース、１０
……熱電子放出用フイラメント、１１……網状電
極、１２……カード、１３……邪魔板、１４，１
５，１６……電源、１７……ケイ素、１８……基
材。
FIG. 1 is a schematic diagram showing an example of an apparatus for carrying out the method of the present invention. DESCRIPTION OF SYMBOLS 1... Vacuum chamber, 2... Exhaust port, 3... Vapor deposition ion source, 4... Ion acceleration electrode, 5... Steam generation section, 6... Vapor deposition ionization section, 7... Crucible, 8...
...180° deflection E gun, 9...Water-cooled copper hearth, 10
...Thermionic emission filament, 11...Mesh electrode, 12...Card, 13...Baffle plate, 14,1
5, 16...Power supply, 17...Silicon, 18...Base material.
Claims (1)
おいてケイ素を加熱し、蒸気化し、次いで該蒸気
に電子放射源からの加速電子を衝突せしめること
によりイオン化し、更に該イオン化蒸気粒子を電
界加速して１〜104eVの運動エネルギーを付与し
基材上に、該基材の法線に対し０〜30゜又は75〜
89゜の入射角で衝突せしめ単結晶ケイ素層を形成
することを特徴とする半導体の製造方法。 ２ イオン化蒸気粒子が蒸気粒子の0.5〜50％で
ある特許請求の範囲第１項記載の製造方法。 ３ 運動エネルギーが102〜103eVである特許請求
の範囲第１項又は第２項記載の製造方法。[Claims] Silicon is heated in a high vacuum evacuated to 15×10 -5 Torr or less, vaporized, and then ionized by bombarding the vapor with accelerated electrons from an electron radiation source, and further The ionized vapor particles are accelerated in an electric field to impart kinetic energy of 1 to 10 4 eV, and then placed on the substrate at an angle of 0 to 30 degrees or 75 degrees to the normal to the substrate.
A method for manufacturing a semiconductor, characterized in that a single crystal silicon layer is formed by colliding at an incident angle of 89°. 2. The manufacturing method according to claim 1, wherein the ionized vapor particles account for 0.5 to 50% of the vapor particles. 3. The manufacturing method according to claim 1 or 2, wherein the kinetic energy is 10 2 to 10 3 eV.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56094739A JPS57208127A (en) | 1981-06-18 | 1981-06-18 | Manufacture of semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56094739A JPS57208127A (en) | 1981-06-18 | 1981-06-18 | Manufacture of semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57208127A JPS57208127A (en) | 1982-12-21 |
| JPS6158968B2 true JPS6158968B2 (en) | 1986-12-13 |
Family
ID=14118479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56094739A Granted JPS57208127A (en) | 1981-06-18 | 1981-06-18 | Manufacture of semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57208127A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6230315A (en) * | 1985-07-31 | 1987-02-09 | Anelva Corp | Electron gun apparatus |
| JPS62229844A (en) * | 1986-03-31 | 1987-10-08 | Toshiba Corp | Thin-film deposition method |
| CA2147198A1 (en) * | 1995-04-18 | 1996-10-19 | Chettypalayam R. Selvakumar | Low temperature ion-beam assisted deposition method for realizing sige/si heterostructures |
-
1981
- 1981-06-18 JP JP56094739A patent/JPS57208127A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57208127A (en) | 1982-12-21 |
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