JPS6160460B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for testing a large-scale integrated circuit device, which includes an input section, an arithmetic section, an output section, a data memory section, an instruction mask ROM, and a control section. A large-scale integrated circuit device (hereinafter abbreviated as LSI) in which a control signal is output from a control unit according to the content, and the operation of each part is controlled by this control signal, that is, an LSI that is controlled by a microcomputer method. Concerning testing methods.

FIG. 1 is a diagram showing the basic configuration of an LSI that is controlled by a known microcomputer system, and includes an input section 1, an arithmetic section 2, an output section 3, a data memory section 4, an instruction mask ROM 5, and a control section 6. It consists of

Figure 2 shows the LSI shown in the basic configuration diagram of Figure 1.
This is a system block diagram of 7, in which 7 is an instruction mask ROM, 81 to 84 are latches,
9 is an instruction register that latches during the instruction execution cycle read from the ROM; 10
1 to 104 are multiplexers; 11 is a program counter; 12 is a stack for saving the contents of the program counter 11 when a subroutine is executed;
3 is a stack pointer (register) that specifies the address of stack 12; 14 is an instruction programmable logic array that is composed of an AND section and an OR section for decoding instruction words and is also programmable; 15 is a random access Memory (RAM), 16 is an X register, 17 is a Y register, 18 is an arithmetic logic unit that performs various processing decisions on data, and 19 is a unit that transfers data as it is according to instructions, or transfers data as it is, or transfers data between "1" and "1" of each bit. 20 is an accumulator, 21 is a temporary register that stores the contents of accumulator 20 when necessary, and 22 is a 1-bit flip-flop, which can be used arbitrarily during the program. program status, which can be
23 is a carry flag that is set when data is processed by the arithmetic logic unit and a carry from the most significant bit occurs; 24 is a zero flag that is set when the result of data processing is zero; 25 and 2
6 is a data bus, 27 to 29 are conveyors for comparing and determining two data, 30 is a programmable logic array, 31 is a decoder, 32 is a gate,
33 is a counter enable/disable flip-flop that is set and reset by a control command and makes an external signal count and stop; 34 is a counter that performs a counting operation in response to an external signal; 35 is a sense flip-flop which is set when the most significant digit of the counter 34 changes from "1" to "0", that is, it overflows. 36 is a synchronization circuit that sends out a set signal;
7 is a clock generator, A and B are input ports,
C to E are output ports, 38 and 39 are sense input terminals, 40 is a counter select input terminal for switching the function of the sense input terminal 38, 41 is an oscillator input terminal, 42 is a reset input terminal, 43 is a test input terminal, and 44, 45 is a power input terminal.

In an LSI equipped with the above system blocks,
According to the program written in ROM7,
A port, B port, sense input terminals 38, 39
Information is taken in from the outside by a combination of input signals applied to the
15, etc., and processes the result in the arithmetic unit together with information indicating the past history accumulated in the port 15, etc., and outputs the result as a control signal to various devices from an output terminal such as the C port, D port, or E port.

In addition, various parts such as input/output ports and arithmetic units are controlled by a program that combines instructions unique to microcomputers such as data transfer instructions, various operation instructions, input/output instructions, and control instructions to achieve a certain purpose. are doing.

As is clear from this, by writing a program for executing, for example, television control or clock control into the instruction mask ROM 7, the LSI has a control function according to the program. Therefore, from a structural point of view, it has general versatility, and as a whole, it is a dedicated LSI that executes control according to the intended purpose.

Figure 3 is a diagram showing the configuration when the above LSI is applied to clock control.
A 60Hz (or 50Hz) pulse obtained from the power supply is supplied as a time reference signal to the input section 1 of the LSI, this pulse is used to count time, and a signal for driving and controlling the time display section 46 is output from the output section 3. The time is displayed. Incidentally, in the case of clock control, the data memory must store time information that changes with time, and for this reason, the data memory section 4 is configured with a random access memory.

FIG. 4 is a diagram showing the state of allocation of data areas to the data memory section 4, and the time information is
Stored as binary coded decimal (BCD) data.
Also, an instruction mask that controls the LSI
A program that satisfies the flowchart shown in FIG. 5 is written into the ROM 5.

When using the LSI shown in Figure 2 for clock control, a 60Hz pulse is sent to the sense input terminal 38.
In addition, the change in this pulse is controlled by the control circuit according to the program procedure in the instruction mask ROM7 to perform the clock function, and the results are sent from output ports C and D to the clock display section to display the clock. do. At this time, the clock information shown in FIG. 4 is stored in the RAM 15, and the flowchart shown in FIG. 5 is realized using various instructions. In other words, by writing the program shown in Figure 5 into the instruction mask ROM, the part surrounded by the broken line in Figure 3 can be integrated into an LSI.
is an LSI dedicated to watches.

In this way, the LSI shown in the basic configuration of Figure 1 is
Easily dedicated by rewriting the ROM program
Since it is an LSI, it can shorten the development period and save development costs, and it tends to be widely applied.

By the way, when manufacturing such an LSI, testing is essential to determine its quality. For example, in order to determine the quality of the clock LSI explained using FIGS. 3 to 5, that is, to determine whether the LSI has the clock function correctly, it is necessary to 4 is functioning properly.

When data areas are allocated as shown in FIG. 4, each address in the data memory section 4 has the following functions.

(1) Addresses 4 and 5 (60Hz counter) A ROM-controlled sexagesimal counter that counts up at the positive edge of a 60Hz pulse, counting up once every second.
times overflow.

(2) Addresses 6 and 7 (Second Counter) This is a ROM-controlled sexagesimal counter that counts up when the 60Hz counter overflows, and stores seconds information.

(3) Addresses 8 and 9 (minute counter) Minute information is stored in a ROM-controlled sexagesimal counter that counts up when the second counter overflows.

(4) Address 10 (hour counter) Stores time information in a ROM-controlled hexadecimal counter that counts up when the minute counter overflows.

(5) Address 11 (AM/PM flag) This flag is inverted when the time counter overflows. In the case of AM, the least significant bit is "1", and in the case of PM, the least significant bit is "0", indicating morning and afternoon information. remember.

Therefore, in order to check the functions of the data memory section, all the functions shown in (1) to (5) above must be checked. In this case, it is necessary to confirm that the AM/PM flag changes correctly from "0" to "1" and from "1" to "0", and it takes at least 12 hours to bring about one change. A clock operation over a period of time is required. Therefore,
Testing over 24 hours is required to confirm whether the above two changes are being made correctly.

Furthermore, it is also necessary to test the instruction mask ROM 5. instruction mask
A program for realizing the flowchart shown in FIG. 5 and executing the clock function is written in the ROM 5. During testing, it is necessary to check whether this program has been written correctly.

Assuming that the instruction mask ROM is tested in the same manner as the data memory section described above, the dotted line box a in Figure 5
The part where the AM/PM flag = 1 takes the most time to test, and requires at least 12 hours of testing time.

In this way, the LSI explained with reference to Figures 1 to 5 can be easily created as a dedicated LSI by rewriting the ROM program, which is useful in terms of shortening the development period and saving development costs. From what I can see, it is excellent. However, it takes a very long time to test the manufactured LSI, which significantly reduces the above advantages.

In order to eliminate such inconveniences, it is conceivable to shorten the test time by inputting a pulse with a much higher frequency than a 60 Hz pulse during testing, for example. However, in order to perform testing using this method, the LSI must operate at a speed that is practically impossible. For this reason, a practically pointless increase in speed is required, leading to an increase in chip size. Furthermore, if the LSI has a built-in one-week timer or one-year timer, it is virtually impossible to test it by the above method of increasing the frequency of input pulses.

The present invention provides a test method that can completely eliminate all of the problems with LSIs described above. , an input means for directly inputting signals from the terminals used as input/output terminals to the control unit instead of the instruction memory in normal use, and an input means whose contents are constant without being affected by changes in the contents of the instruction mask ROM. A test-only ROM that is
and an output means for outputting the contents of the instruction mask ROM from the terminals used as input/output terminals in normal use, as well as the time history of the voltage applied to the test terminals and input/output terminals mentioned above. At least three types of test modes are controlled by a combination of signals, and in the first test mode, a signal is applied directly from the outside to the control unit via the input means, and each part except the ROM is operated to perform the test. In the second test mode, the contents of the ROM are outputted via the above-mentioned output means to test whether the writing is correct, and in the third test mode, the test-only ROM is accessed, and the LSI is It is characterized by a controlled residual test.

The test method of the present invention will be explained in detail below.

In the LSI having the basic configuration shown in FIG. 1, all instructions output from the instruction mask ROM are decoded by the control section, and necessary control is performed based on the decoding results. In the system block diagram shown in Figure 2, 7 is the instruction mask.
The contents are read into the instruction register 9, the contents of the instruction register 9 are decoded by the instruction programmable logic array 14, and necessary control is performed based on this result.

For example, in the case of an L (load) instruction, the contents of the instruction register 9 are decoded, and from the instruction programmable logic array 14, the contents M(X , Y) to the data bus 26, the data bus 2
Arithmetic logic unit 1 without changing the contents of 6.
8, a signal that controls the output of the arithmetic logic unit 18 to be input to the accumulator (ACC) 20, and if the loaded result is zero, the zero flag 24 is set; A control signal to reset the zero flag 24 is generated, and each part is controlled by these signals to set {A←M(X,Y)}, that is, the memory M(X,Y) specified by the X,Y register. The process of loading data into A is executed. In addition, in the case of the A (addition) instruction, instruction register 9
The contents of the instruction programmable logic array 14 are decoded and the contents of
RAM specified by Y registers 16 and 17
A control signal for outputting the contents M(X, Y) of 15 to the data bus 26, a control signal for outputting the contents of the accumulator to the data bus 25 via the multiplexer 103, and a truth/complete signal for outputting the contents of the accumulator to the data bus 25 without inverting the data on the data bus 25. A control signal that passes through the element 19 and is applied to the arithmetic logic unit 18, a control signal that adds the data on the data buses 25 and 26 and the carry flag 23, a control signal that inputs the carry information resulting from the addition to the carry flag 23, and the addition result is zero. Depending on whether the Y)+CF}, that is, carry-addition is performed between A and the data in memory M(X, Y), and the result is stored in A.

On the other hand, the contents of the instruction mask ROM 7 are created by combining the above instructions. Therefore, to judge whether an LSI is good or bad, it is important to check that each instruction is functioning correctly in terms of context, combination of numerical data, etc., and that the program is correctly written to the instruction mask ROM that supplies these instructions. This can be done by confirming two points:

According to the present invention, these two points can be confirmed (tested) in mass production.

FIG. 6 enables the test method of the invention
It is a diagram showing the configuration of the LSI, where 47 is a test terminal for test mode control, 48 is a test control section, and 49 is a diagram showing the configuration of the LSI.
is a test-only ROM added to the instruction mask ROM 5, and 50 and 51 are multiplexers. By the way, the illustrated test control section 48
has the configuration shown in FIG. The test mode control timing of this circuit will be explained with reference to FIG.

When the levels of the _sense input terminal SSO52 and the test terminal (TST) 47 are set to high level for one clock at the timing of t1, the D flip-flop 5
At 3, the output TF/ becomes TF1=1, while the output TF2 of the D flip-flop 54 becomes 0. Therefore, terminal a becomes high level and terminals b and c become low level. This state is the first test mode.

Next, when the levels of timing terminals 47 and 52 at _t2 are set to low level for one clock, TF1=
0, while TF2=1, terminal b becomes high level, and terminals a and c become low level. This state is the second test mode.

Further, when the level of the terminal 52 is set to high level at timing _t3 , TF1=1 and TF2=1, so that the terminal c becomes high level and the terminals a and b become low level. This state is the third test mode.

In this way, the test control section 48 can easily obtain different test modes by applying signals to the test terminal 47 and the sense input terminal 52 of the LSI used in the normal state. Regardless of the state of the outputs TF1 and TF2 of the D flip-flops 53 and 54, if the test terminal 47 is kept at a low level for two or more clocks, both TF1 and TF2 become "0" and the normal operation mode is entered. Therefore, under normal usage conditions, if a low-level signal is applied to the test terminal 47, even if TF1 and TF2 are set to "1" due to noise etc., it will be instantaneous. returns to normal operating mode.

Any one of the first to third test modes is set as described above, and the test under each test mode is as follows.

In the first test mode, the circuit shown in FIG. 9 is used, and the b
The microcomputer shown in the system block diagram of FIG. 2 is operated by switching signals from the A and B ports and inputting commands from the A and B ports. For example, in the case of load immediate instruction LI6, the instruction code is (01010110), and this instruction code is added to the A port (AI0-3) and the B port (AI0-3) as shown in Figure 9. .

FIG. 10 is a diagram showing an example of the test procedure in the first test mode (external command mode).
ACC is undefined (indicated by △△△△), and Epo is (〇〇〇〇). Next, the instructions shown in 2 to 7, LI5
(load immediate field 5 to A), E port output command OTE (output A data to E port), LI10, OTE, LI5, OTE
When you input , the contents of ACC change and this is output to E port. If the output of the E port changes as expected, it can be seen that the ACC and E port bits are set and reset by the LI and OTE commands.

In this way, by changing the internal state of the ACC or RAM, etc. using an instruction, and outputting this internal state change to the output port, the system block diagram shown in Figure 2 is created. Test that each part of the LSI is working correctly according to each instruction.

FIG. 11 is a diagram showing another method of inputting the above command, in which a transfer gate circuit composed of MOS transistors is used, and the sense input terminal 4
The command is input twice, when the level of 0 is high level and low level.

FIG. 12 is a timing chart when the instruction LI6 is input using this method, where SNS1 indicates the level of the sense input terminal 40, AI0 to AI3 indicate the level of the A port, and I1 to I8 indicate the instruction code.

Next, in the second test mode, the a signal obtained at the a terminal shown in FIG.
ROM is accessed.

FIG. 13 is a diagram showing a circuit used in the second test mode, and the LSI shown in the system configuration diagram of FIG. 2 is controlled by the test-only ROM 49 accessed by the a signal. Note that in the second test mode (test routine mode), the b signal is at a low level, and the multiplexer 50 shown in FIG. The A port and B port have the same function as in normal use, that is, the function as an input port. Note that the test program can be written in a part of the instruction mask ROM 5 in place of the test-only ROM.

The second test mode is dedicated to testing instructions that cannot be completely tested under the first test mode, such as instructions related to A port and B port.
Perform a self-test using a short program written to the ROM.

The first and second tests described above test whether all functions except the instruction mask ROM, that is, all instructions, function correctly.

Furthermore, in the third test mode, the multiplexer 51 of the LSI shown in FIG. 14 is switched by the c signal generated at the c terminal of the circuit shown in FIG. The program counter 11 is controlled to be incremented by +1 every clock by the signal d. By this control operation, the contents of the instruction mask ROM 5 are output to the C ports CO1 to CO7 in address order every clock. The instruction mask ROM 5 is tested by checking this output.

By performing the first to third tests in this way, the LSI whose system block diagram is shown in Fig.
Regarding this, it is possible to check whether all instructions function correctly and whether writing to the instruction mask ROM is correct, and therefore it is possible to judge whether the LSI is good or bad.

Note that in order to further increase the efficiency of the above-described test, a method of multiplexing and outputting the internal state of the LSI may be used in combination.

FIG. 15 is a diagram showing an example in which the contents of the program counter 11 are output from two types of output ports, the D port and the E port. As shown in the figure, a multiplexer 55 is provided, and only when the program counter 11 executes a discontinuous instruction such as a jump instruction, the contents are transferred to the D ports DO0 to DO7 and the E port.
output to EO0 to EO2, and in other cases general data, i.e. DO0 to DO7 data, EO0
- Test efficiency is improved by outputting EO2 data.

Furthermore, if the LSI shown in FIG. 2 has a built-in PLL circuit, it will have a built-in reference counter 56, selector counter 57, phase comparator 58, etc., as shown in FIG. To test such a PLL circuit, a low-pass filter and voltage-controlled oscillator (VCO) must be combined with an LSI to form a PLL loop, and the oscillation frequency (VCO) must be measured. By the way, it takes a considerable amount of time for the VCO to stabilize, so testing the LSI using the test method that measures the VCO takes time.

However, as shown in FIG. 17, if the outputs of the reference counter 56 and selector counter 57 are output to terminals 60 and 61 in test mode using a multiplexer, the functions of these counters can be tested in a short time. In addition, 6 in the figure
2 is a low-pass filter, and 63 is a VCO. In addition to these examples, registers, flags, etc.
If the internal state of the LSI is multiplexed and output in test mode, test efficiency will be improved.

As is clear from the above explanation, according to the test method of the present invention, even if the ROM of an LSI with the basic configuration shown in FIG. 1 is changed and various dedicated LSIs are manufactured, the By adding the ROM output mode test and the external instruction mode and test routine mode tests that are common to each product, it is possible to directly check the functions of each part of the LSI and test the dedicated LSI in a short time. become.

When testing the above LSI using a test program using an LSI tester,
It is necessary to create test programs for the first to third test modes described above. by the way,
The first test mode (external instruction test mode) and the second test mode (test routine mode) are common to each product type. Therefore, once the ROM is created, there is no need to create it again even if the ROM contents change. On the other hand, writing to the instruction mask ROM naturally changes as the product type changes. For this reason, each variety has its own characteristics.
It is necessary to create a program for testing the ROM output mode.

In the test method of the present invention, in ROM output mode
Since it is possible to output the contents of ROM in a certain order, it is possible to output the contents of ROM in a certain order.
If we find the expected value when the contents of are output,
A test program for testing the ROM is completed. Furthermore, the fact that a test program is generated from the contents of the ROM in this way means that the production of a test program can be computerized by simple software development.

For example, the contents of the dedicated LSI ROM program are
When manufacturing LSIs, test programs can be easily created by processing magnetic tape with a computer.

Furthermore, in the test method of the present invention, the timing and operating state of each part are not test-specific, but are extremely close to the actual usage state, and the functions of each part are tested in detail, so the test accuracy is extremely high. Become.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the basic configuration of an LSI that is controlled by a known microcomputer system, Figure 2 is a system block diagram of the LSI shown in Figure 1, and Figure 3 is a case in which the same LSI is applied to clock control. 4 is a diagram showing the state of allocation of data areas to the data memory section, FIG. 5 is a flowchart of clock control, and FIG. 6 is the configuration of an LSI that enables the test method of the present invention. 7 is a diagram showing the circuit configuration of the test control section, FIG. 8 is a diagram showing the timing of test mode control, FIG. 9 is a diagram showing the circuit used in the first test mode, and FIG. The figure shows an example of the test procedure in the first test mode,
Figure 11 is a diagram showing how to input commands;
The figure shows the timing diagram when inputting the instruction LI6,
Figure 13 shows the circuit used in the second test mode, Figure 14 shows the circuit used in the third test mode, and Figure 15 shows the circuit that outputs the contents of the program counter from the output port. The figures shown in FIG. 16 and FIG. 17 are diagrams for explaining a PLL circuit and a method for testing it. DESCRIPTION OF SYMBOLS 1... Input part, 2... Arithmetic part, 3... Output part, 4... Data memory part, 5, 7... Instruction mask ROM, 6... Control part, 81-84... Latch, 9
...Instruction register, 101-10
4, 50, 51, 55...multiplexer, 11...
Program counter, 12... Stack, 13... Stack pointer, 14... Instruction programmable logic array, 15... RAM,
16...X register, 17...Y register, 18...Logic operation unit, 19...Truth/complement, 20...Accumulator, 21...Temporary register, 22...Program status, 23...Carry flag, 24...Zero flag, 25, 26
...Data bus, 27-29...Compare, 30...Programmable logic array, 31...Decoder,
32...Gate, 33...Counter enable/disable flip-flop, 34...Counter,
35...Sense flip-flop, 36...Synchronization circuit, 37...Clock generator, 38, 39...Sense input terminal, 40...Counter select input terminal, 41...Oscillator input terminal, 42...Reset input terminal, 44, 45 ...Power input terminal, 46...Clock display section, 47...Test terminal, 49...Test only
ROM, 52...Sense input terminal, 53, 54...D
Flip-flop, 56...Reference counter, 57...
Selector counter, 58... Phase comparator, 60, 6
1...Test mode terminal, 62...Low pass filter, 63...VCO.

Claims (1)

[Claims] 1. A large-scale integrated circuit has one test terminal dedicated to the test mode, and an input for directly inputting signals to the control unit from the terminal used as an input terminal in normal use in place of the instruction memory. means and
Only for tests whose contents remain constant without being affected by changes in the instruction mask ROM contents.
Use the above instruction mask from the ROM and the terminals used as input/output terminals in normal use.
In addition to adding an output means for outputting the contents of the ROM, at least three types of test modes are controlled by a combination of signals including the time history applied to the test terminals and input/output terminals, and the first test In the second test mode, a signal is applied directly from the outside to the control unit via the input means mentioned above to operate each part except the ROM, and in the second test mode, the contents of the ROM are outputted via the output means mentioned above. The large-scale integrated circuit is characterized in that, in a third test mode, the test-dedicated ROM is accessed, and the test-dedicated ROM controls the large-scale integrated circuit to perform a remaining test. How to test equipment. 2. The method for testing a large-scale integrated circuit device according to claim 1, wherein the internal state in the test mode is output from a terminal used in the normal use state.