JPS6161259B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a balanced transformerless (hereinafter referred to as BTL)
Regarding integrated circuit devices equipped with a
It is designed to increase power.

Conventionally, various BTL circuits have been proposed. Figure 1 shows a power amplifier circuit equipped with a BTL circuit suitable for IC (integrated circuit), where 10 is a driver circuit and 20 is a power amplifier circuit.
is the BTL driven by this driver circuit 10
The circuit 30 is a speaker driven by the BTL circuit 20. In the BTL circuit 20, 21, 2
2, 23, and 24 are all NPN transistors, and transistors 21 and 24 are connected to the speaker 3, which is the load, as shown by the broken line A during a certain half period of the input signal.
0, and the transistors 22 and 23 also supply power to the speaker 30 during the next (before or after) half cycle of the input signal half cycle as shown by the dashed line B, so that a so-called push-pull operation takes place. It's summery. The driver circuit 10 is for driving the bases of the transistors 21, 22, and 24 so that such a push-pull operation is performed. Note that 25 is a terminal for supplying the power supply potential +Vcc to the collectors of the transistors 21 and 23, 26 is a terminal for supplying a reference potential (ground potential GND) to the emitters of the transistors 22 and 24, and 27 is the emitter of the transistor 21. The first output terminal (OUT) is connected to the connection point between the transistor 23 and the collector of the transistor 22;
The second output terminal (OUT) is connected to the connection point between the emitter of the transistor 24 and the collector of the transistor 24.

When converting the circuit with the above configuration into an IC,
Until now, transistors have been arranged on IC chips as shown in Figure 2. In FIG. 2, the same parts as in FIG.
4 are built in and are electrically insulated from each other, island-like regions 31, 32, 33, and 34 are the power supply potential terminal 25 and the reference potential terminal 2, respectively.
6. A wiring layer made of Al or the like corresponding to the first output terminal 27 and the second output terminal 28, the hatched parts are contact areas, and the x marks are terminals 25, 26, 2.
7, 28 corresponding wiring layers 31, 32, 33, 3
The connection points with 4 are shown respectively. According to the illustrated transistor arrangement, pairs of transistors 21 and 24, 22 and 23 are arranged in parallel near the driver circuit 10, and the emitter diffusion layer E and collector/contact diffusion layer C of each transistor are connected to the driver circuit 10. 10 (note that the base diffusion layer is not shown). Then, a power supply potential wiring layer 31 interconnecting the collector of the transistor 21 and the collector of the transistor 23 and the transistor 22 are provided.
The reference potential wiring layer 32 that interconnects the emitter of the transistor 21 and the emitter of the transistor 24 is arranged so that the intermediate portions of each layer intersect with each other in an insulating relationship, and the emitter of the transistor 21 and the collector of the transistor 22 A first output wiring layer 33 that interconnects the two output wiring layers 33 and a second output wiring layer 34 that interconnects the emitter of the transistor 23 and the collector of the transistor 24 are located across the intersection of the wiring layers 31 and 32. are placed on both sides of it.

In the above arrangement, the wiring layer 31 and the emitter, base, and collector electrode layers (not shown) of each transistor are usually formed of a first metal vapor deposition layer, and the wiring layers 32, 33, and 34 are formed of two layers. The eye is formed with a metal vapor deposited layer. The need for two-layer wiring or cross wiring in this way is for transistors 21 and 2.
Since transistors 3, 22 and 24 cannot be arranged in pairs, transistors 21 and 24, 2 are connected as shown in the figure.
This is because 2 and 23 have no choice but to be juxtaposed as a pair. That is, if the transistors 21 and 23 and 22 and 24 are arranged in pairs in the driver circuit 10, the transistors 21 and 2 will be connected to each other in each pair.
3 or 22 and 24 to the driver circuit 10, the amount of heat returned to the driver circuit 10 in each transistor pair becomes unbalanced, making it impossible to ensure proper operation. It is necessary to arrange the transistors 21 and 24 and 22 and 23 in pairs and to balance the amount of heat feedback.

However, according to the transistor arrangement/connection pattern shown in FIG. 2, there is a problem in that power-up is hindered because the wiring resistance leading to the terminal connection positions indicated by the x marks is large. In the power ICs currently in use, the collector saturation resistance of the power transistor is quite small, approximately 0.4Ω, and it is not easy to reduce this to several tens of milliohms from a process standpoint. Therefore, in order to achieve power-up, it is desirable to reduce the emitter wiring resistance and collector wiring resistance of the output transistor as much as possible, but in the arrangement shown in Figure 2, the resistance of the wiring layers 31 and 32 is ignored. It's so big that it can't be seen.
As an example, the wiring resistance along side a is approximately 10mΩ, and b
If the wiring resistance along the side is approximately 68mΩ, wiring layer 3
Transistor 21 from terminal point 25 (x mark) of 1
Or the wiring resistance to the far collector of 23 is approximately
78 mΩ (10Ω + 68Ω), and the transistor 22 or 24 is connected from the terminal extraction point 26 (x mark) of the wiring layer 32.
The wiring resistance to the emitter is approximately 44Ω (10Ω+68/
2Ω).

One way to reduce such large wiring resistance is to increase the area of the wiring layer.
This will increase the dead space, which is not a good idea from the perspective of improving the degree of integration.

Therefore, an object of the present invention is to provide a novel power IC that can minimize wiring resistance without impairing the balance of thermal feedback and without increasing the area of wiring layers.

In order to achieve this objective, the present invention utilizes two-layer wiring technology and also adds innovation to the arrangement pattern and wiring pattern of the emitter layer and collector contact layer of the four output transistors that constitute the BTL circuit. Hereinafter, embodiments shown in the accompanying drawings will be described in detail.

FIG. 3 shows a power supply according to an embodiment of the present invention.
This figure illustrates a plane corresponding to FIG. 2 of the IC, and the same parts as in FIG. 2 are given the same or corresponding symbols. One of the main features of the device of FIG. 3 is that each transistor 21, 22,
23 and 24, an emitter diffusion layer E and a collector/contact diffusion layer C (both are normally
N ⁺ type diffusion layer) is arranged to extend approximately parallel to the driver circuit 10, and another feature is that a pair of output wirings are arranged approximately perpendicularly to the extension direction of the diffusion layers E and C. In addition to arranging the layers 43 and 44, a wiring layer 41 for power supply potential and a wiring layer 42 for reference potential are arranged between both wiring layers 43 and 44, intersecting each other in an insulating manner. What should be further noted is that the two output wiring layers 43 and 44 are arranged on the outside, and the power supply potential (Vcc) wiring layer 41
and a reference potential (ground potential in this embodiment) wiring layer 42 are arranged inside so as to be sandwiched between the two output wiring layers. That is,
Conventionally, as shown in FIG.
Because the wiring layer for the power supply potential and the wiring layer for the reference potential were arranged on the outside so as to sandwich the power supply potential wiring layer, the wiring resistance was large. The wiring resistance of the reference potential wiring layer and the reference potential wiring layer is made small, and the γcs of the transistor is made small. Usually, the wiring layer 41, an emitter (not shown), a base,
Each electrode layer of the collector is the first metal layer (e.g.
wiring layers 42, 43, 4
4 is formed by the second metal vapor deposition layer. Each terminal connection position indicated by an x mark, that is, each wiring layer 41, 4
In the center part of 2, 43, 44, bonding
Terminals 25, 26, 27, 28 made of wire etc.
are connected to each other.

According to the transistor arrangement/connection pattern shown in FIG. 3, the transistors 21 and 24, 22 and 23 that supply power to the load in the same half cycle are arranged at approximately the same distance from the driver circuit 10, so the amount of heat feedback is There is almost no imbalance. Since each of the wiring layers 41 to 44 is contained within the transistor forming area, the wiring layer area does not increase significantly compared to the case of FIG. 2, and therefore, the dead space does not increase. Moreover, especially regarding the wiring layers 41 and 42, since the length of the broken line is shortened, a remarkable effect of reducing the wiring resistance by almost half can be obtained. That is, as an example, if the wiring resistance along side a is approximately 34 mΩ (this corresponds to the wiring resistance in section b/2 in FIG. 3), then The wiring resistance to the far collector of the transistor 21 or 23 is approximately 34 mΩ, and the terminal extraction point 26 of the wiring layer 42
The wiring resistance from the cross mark to the emitter of the transistor 22 or 24 is approximately 17 mΩ (34/2 mΩ). Comparing these numbers 34mΩ and 17mΩ with the numbers 78mΩ and 44mΩ, respectively, mentioned above with respect to Figure 2, in the case of Figure 3 according to the present invention,
It is clear that the wiring resistance is approximately half that of the case shown in the figure. Therefore, according to the transistor arrangement and connection pattern shown in FIG. 3, it is possible to increase power while reducing wiring resistance.

FIG. 4 shows the power of another implementation of the invention.
This figure shows the planar arrangement of the IC, and the same parts as in FIG. 3 are given the same reference numerals. Also,
A cross section taken along the line ``-'' and a cross section taken along the line ``-'' in FIG. 4 are shown in FIGS. 5 and 6, respectively.
In FIG. 4, 51 is a wiring layer for power supply potential, 52
A, 52B, 52C are wiring layers for reference potential, 53,
Reference numeral 54 indicates an output wiring layer, and B indicates a base diffusion layer. The device of this embodiment differs from that of FIG. 3 in that the transistors 21, 22, 23, 2
The number of emitter diffusion layers E, base diffusion layers B, and collector/contact diffusion layers inside 4 is one each larger than the other, and secondly, the wiring layer 51 for power supply potential is composed of a second wiring layer. With,
The reference potential wiring layer is composed of a first wiring layer 52A and second wiring layers 52B and 52C.

As an example, the internal configuration of the transistor 22 is
To explain the diagram, a silicon semiconductor substrate 50
After forming an N ⁺ type diffusion layer 56 on the surface of the P type layer 55, an N ^- type layer 57 is epitaxially grown thereon, and a P type base diffusion layer B, N ⁺ is formed in this N ^- type layer 57. In addition to forming a type collector/contact diffusion layer C, an emitter diffusion layer E is formed within the base diffusion layer B. The surface of the substrate is covered with an insulating film 59 made of silicon oxide or the like, and the insulating film 59 has emitters, bases,
Openings are provided to expose the respective electrode forming positions of the collector, and electrode layers 60, 61, 62, 63, and 64 each made of a first metal vapor deposition layer are arranged inside each opening. These electrode layers 60 to 64
is covered with a suitable interlayer insulating film 65, and on this insulating film 65, an output wiring layer 5 connecting the emitter of the transistor 21 and the collector of the transistor 22 is formed.
3 is placed. Note that the internal configuration described above regarding the transistor 22 is similar to that of the other transistors 2.
The same applies to 1, 23, and 24.

On the other hand, the cross wiring section is connected to the board as shown in FIG.
50 P ⁺ type isolation diffusion regions 58 . A wiring layer 52A made of a first metal vapor deposition layer is formed on the insulating film 59 covering the isolation region 58, and an interlayer insulating film 65 is formed over the wiring layer 52A. The interlayer insulating film 65 is provided with openings that expose the contact areas near both ends of the wiring layer 52A, and the wiring layers 52B and 52C, which are made of the second metal vapor deposition layer, are connected through the respective openings. It is in ohmic contact with the wiring layer 52A. The wiring layer 51 for power supply potential consisting of the second metal vapor deposition layer is connected to the wiring layers 52B and 5.
2C on the interlayer insulating film 65.

As mentioned above, the power ICs described above with reference to Figs. 4, 5, and 6 are basically constructed according to the same principle as the device shown in Fig. 3, and have their own unique characteristics. Based on the transistor placement and connection pattern, (1) the amount of heat feedback is balanced;
Excellent effects such as (2) no substantial increase in the area of the wiring layer and (3) significant reduction in wiring resistance can be obtained.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a power amplifier circuit to be converted into an IC, and Figure 2 is a plan view of the IC when the circuit in Figure 1 is converted into an IC according to the conventional technology.
FIG. 3 is a plan view of an IC when the circuit shown in FIG. 1 is converted into an IC according to one embodiment of the present invention, and FIG. 4 is a plan view of an IC formed from the circuit shown in FIG. Therefore, the plan view of the IC when it is converted into an IC, Figure 5, is as follows.
A sectional view taken along the line - in Fig. 4, and Fig. 6 is a sectional view taken along the - line in Fig.
FIG. 2 is a cross-sectional view taken along line - in the figure. 10...Driver circuit, 21, 22, 23, 24
...Transistor for BTL circuit configuration, 25...Power supply potential terminal, 26...Reference potential terminal, 27, 28...Output terminal, 31, 41, 51...Wiring layer for power supply potential, 3
2, 42, 52A to 52C... wiring layer for reference potential,
33, 34, 43, 44, 53, 54...output wiring layer, E...emitter diffusion layer, B...base diffusion layer,
C... Diffusion layer for collector contact.

Claims (1)

[Claims] 1 has four transistors for configuring a balanced transformerless circuit, and the 4
A pair of transistors 21 and 24 that supply power to the load during a certain half period of the input signal among the two transistors.
and another pair of transistors 22 and 23 which supply power to the load in the half cycle next to the half cycle, the emitter layer and the collector contact layer of each transistor are arranged in close proximity. A pair of output wiring layers are arranged spaced apart from each other so as to extend in a certain direction and are substantially perpendicular to the extending direction of the emitter layer and the collector contact layer, and a power supply potential wiring layer and a reference potential wiring layer are provided. An integrated circuit device characterized in that the layers are arranged between the output wiring layers so that a portion of each layer intersects with each other in an insulating relationship.