JPH0769399B2 - LSI test method - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention makes it possible to carry out a test for each block by dividing a logic element inside an LSI into a plurality of blocks with a predetermined number of input pins and output pins in common. Regarding the test method of LSI.

[Technical Background of the Invention and Problems Thereof] In recent years, as the integration of LSIs has advanced, the means for testing internal logic elements has become a problem. Conventional LSI in this case
The structure of the internal test circuit is shown in FIG. In the figure, 21 is LS
I and 22 are a plurality of input pins, 23 is the same output pin, 24 is a test dedicated pin, 25 is an input line switching circuit, and 26 is an output line switching circuit. In the test operation in the configuration of FIG. 2, the input line switching circuit 25 and the output line switching circuit 26 are switched and controlled by the signal from the test dedicated pin 24, and the duplicated input pin 2 is used.
2. The output pin 23 is selectively used to input a signal that cannot normally be input or output directly from the outside or directly output to the outside to facilitate the test.

Recently, however, the scale and complexity of LSIs have advanced, and along with this, it has become necessary to divide the inside of the LSI into several blocks and perform a test for each block. In order to enable this block-by-block test, it has conventionally been necessary to multiplex (use switching) test pins corresponding to the number of blocks and input pins and output pins. Therefore, conventionally, there has been a problem that the number of test pins is increased and the number of effective signal pins is decreased accordingly, which is a great obstacle to effective utilization of limited pins.

[Object of the Invention] The present invention has been made in view of the above circumstances, and makes it possible to carry out a test for each block by dividing a logic element inside an LSI into a plurality of blocks with a predetermined number of input pins and output pins being common. In an LSI, one test pin is effectively used without increasing the number of test pins, and the limited signal input / output pins are effectively used. Normal mode in /
An object of the present invention is to provide an LSI test method that enables switching of test modes and setting control of block designation information for selectively circuit-connecting a block to be tested to the input / output pins.

[Summary of the Invention] The present invention is an LSI in which logical elements inside an LSI are divided into a plurality of blocks with a predetermined number of input pins and output pins in common, and a test can be performed for each block. Test pin, a flip-flop for storing a block designating code input from a part of predetermined pins among the input pins, and a normal mode / selective mode for enabling each bit output of the flip-flop. A test mode switching gate and a selection circuit for selectively connecting one arbitrary block between the input / output pins are provided, and one of the test pins determines a predetermined one of the input pins. Each block of the flip-flop is controlled by setting and controlling the block designation code input from some of the pins With the configuration that selectively enables the output, this effectively uses only one test pin without increasing the number of test pins, and efficiently executes the test operation in block units inside the LSI. it can.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit block diagram showing an embodiment of the present invention. Here, the internal logic element of the LSI is divided into four blocks into four blocks, and the configuration is shown as an example in which the input pins and the output pins are quadrupled to facilitate the test. 1 in the figure
Is an LSI, 2 is a plurality of input pins, 3 is also a plurality of output pins, and 4 is only one test pin. 5 is input simultaneously from two specific pins of the input pins 2
It is a flip-flop (F / F) that sets a bit block designation code at the rising edge (“false” → “true”) of the test signal of the test pin 4. A decoder 6 decodes the output of the flip-flop 5. Reference numeral 7 is a gate which controls the output of the decoder 6, and makes the output signal of the decoder 6 valid while the test signal of the test pin 4 is "true". Reference numeral 8 denotes a block selection line that supplies an output signal of the decoder 6 via the gate 7 as a block designation signal to an input line selection circuit 9 and an output line selection circuit 10 described later. 9 receives the selection signal “true” of the corresponding block selection line 8 in the test mode (when the signal on the test pin 4 is “true”), and connects the input pin 2 to the corresponding block. Is selectively connected to the circuit, and in other normal operation (when the signal on the test pin 4 is "false"), the selection signal "common to all blocks on the input / output signal selection line 11"true"
In response to this, the input line selection circuit connects the input pin 2 and all the blocks (0 to 3). In the test mode, 10 receives the selection signal “true” of the corresponding block selection line 8 to selectively connect the circuit between the corresponding block and the output pin 3, and outputs in the other normal operation. This is an output line selection circuit that receives a selection signal "true" common to all blocks on the line selection circuit 10 and circuit-connects all the blocks (0 to 3) and the output pin 3. Reference numeral 11 is an input output signal selection line for inverting the signal on the test pin 4 and supplying it to the input line selection circuit 9 and the output line selection circuit 10 as an input output selection signal common to all blocks in the normal operation mode. is there. Reference numeral 12 is a block obtained by dividing logical elements inside the LSI, and is divided into four blocks here.

Here, the test operation in one embodiment will be described. First, a two-bit block designating code is given to two predetermined specific pins of the input pins 2, and then a “true” value test signal is supplied to the test pin 4, thereby The block designation code on the specific pin is latched by the flip-flop 5. The output of the flip-flop 5 is decoded by the decoder 6. That is, if the output of the flip-flop 5 is “false” for both 2 bits of MSB and LSB, it is block 0; if MSB is “false” and LSB is “true”, block 1; and if MSB is “true” and LSB is If "false", block 2; if both 2 bits of MSB and LSB are "true", block 3
Selection signal is output.

Here, if the test signal of the test pin 4 is “true”,
During that period, the gate 7 is opened, and the signal output from the decoder 6 is supplied to the input line selection circuit 9 and the output line selection circuit 10 via the block selection line 8, and the "true" value among them is output. Only the selection circuit that has received the signal is selectively connected to the circuit, and the corresponding block is connected as a test target between the input pin 2 and the output pin 3.
That is, when the output of the flip-flop 5 is "false" for both 2 bits of MSB and LSB, the output of the decoder 6 causes the block 0 to selectively switch between the input pin 2 and the output pin 3 as a test target circuit. When the MSB is connected and the MSB is “false” and the LSB is “true”, the block 1 is selectively connected between the input pin 2 and the output pin 3 in the same manner as described above, and the MSB
Is “true” and LSB is “false”, the block 2 is selectively connected between the input pin 2 and the output pin 3 in the same manner as described above, and 2 bits of MSB and LSB are both “true”. In some cases, the block 3 is selectively connected between the input pin 2 and the output pin 3 in the same manner as described above. In this way, the block to be tested is selected, and the input pin 2 and the output pin 3 are selected.
After the circuit is connected between them, an input signal for testing the block is applied to the input pin 2 so that the test result is output from the output pin 3. And the above 1
When the test of the block is completed, the test signal on the test pin 4 is set to “false” and then the “true” test signal is supplied again to specify the block to be the next test target. By latching the designated code in the flip-flop 5 via the input pin 2, it becomes possible to test an arbitrary block designated in the same manner as above. In this way, by setting the signal supplied to the test pin 4 to a true value only during the test, the signal line of the input pin 2 can be effectively used to specify the block to be tested and set the test mode.

When the signal on the test pin 4 remains in the "false" state, the gate 7 is closed and the input / output signal selection line 11 is replaced.
The above signal becomes a "true" value and all blocks (0 to
3) is a circuit connection target of the input pin 2 and the output pin 3 in common, and becomes a normal operation mode (normal mode).

In this way, with only one test pin, the input pin and the output pin can be multiplexed to test each divided block in the LSI, without reducing the number of effective signal pins for normal operation. The block unit test can be performed efficiently and quickly.

In the above embodiment, the output of the flip-flop 5 is decoded by the decoder 6 and then supplied to the input line selection circuit 9 and the output line selection circuit 10 via the gate 7 and the block selection line 8. However, for example, the decoder 6
May be omitted and the block may be selected corresponding to the output bit of the flip-flop 5.

As described above in detail, according to the LSI test method of the present invention, L
In an LSI that allows logical elements inside the SI to be divided into multiple blocks with a predetermined number of input pins and output pins in common, and test can be performed for each block, only one test pin and the above input pins , A flip-flop for storing a block designation code input from some of the predetermined pins, a normal mode / test mode switching gate for selectively enabling each bit output of the flip-flop, and And a selection circuit for selectively connecting one block of the input / output pins between the input / output pins.
This test pin controls the setting of the block designation code input from some of the predetermined pins among the input pins in the flip-flop, and controls the gate to output each bit of the flip-flop. By selectively activating, the test operation can be efficiently performed in block units inside the LSI by effectively using only one test pin without increasing the number of test pins.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional LSI internal test mechanism. 1 ... LSI, 2 ... input pin, 3 ... output pin, 4 ...
Test pin, 5 …… Flip-flop (F / F), 6 ……
Decoder, 7 ... Gate, 8 ... Block selection line, 9 ...
Input line selection circuit, 10 output line selection circuit, 11 input / output signal selection line, 12 block.

Claims (1)

[Claims] Claim: What is claimed is: 1. In an LSI in which a logic element inside an LSI is divided into a plurality of blocks with a predetermined number of input pins and output pins in common, and a test can be carried out for each block. A flip-flop that holds a block designation code for selecting and designating each block that is input from the input pin according to the input signal, and the output of this flip-flop is enabled by the signal input from the test pin. Gate and the output bit content of the flip-flop enabled by this gate, and selects one of the plurality of blocks to enable the input / output of a signal via the input pin and the output pin of the block. The test circuit is equipped with a selection circuit, and the test pins are controlled to switch to the test mode inside the LSI by using the test pins and the test signals input through the input pins. LSI test scheme and performs a setting control of a target block designation information.