JPS6210461B2 - - Google Patents
Info
- Publication number
- JPS6210461B2 JPS6210461B2 JP4400179A JP4400179A JPS6210461B2 JP S6210461 B2 JPS6210461 B2 JP S6210461B2 JP 4400179 A JP4400179 A JP 4400179A JP 4400179 A JP4400179 A JP 4400179A JP S6210461 B2 JPS6210461 B2 JP S6210461B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- line
- signal
- tste
- pcm line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000003780 insertion Methods 0.000 claims description 32
- 230000037431 insertion Effects 0.000 claims description 32
- 238000012360 testing method Methods 0.000 claims description 25
- 238000010998 test method Methods 0.000 claims description 5
- 238000000605 extraction Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/22—Arrangements for supervision, monitoring or testing
- H04M3/24—Arrangements for supervision, monitoring or testing with provision for checking the normal operation
- H04M3/244—Arrangements for supervision, monitoring or testing with provision for checking the normal operation for multiplex systems
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Monitoring And Testing Of Exchanges (AREA)
- Time-Division Multiplex Systems (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、時分割交換機におけるPCM回線の
試験及び交換機とPCM回線のインターフエース
回路の試験のための回線試験方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a line test method for testing PCM lines in a time-division exchange and testing an interface circuit between the exchange and the PCM line.
第１図を参照すれば、時分割交換機に接続され
るPCM回線、および交換機とPCM回線のインタ
ーフエース回路の従来の試験方式は時分割スイツ
チネツトワーク（TDSW）１、交換機とPCM回
線のインターフエース回路（DTI０，１）２，
３、回線試験装置（TSTE―Ａ、TSTE―Ｂ）
４，５および他局の交換機（NW）６を備える。
Referring to Figure 1, the conventional testing methods for PCM lines connected to a time division switch and the interface circuit between the switch and the PCM line are the time division switch network (TDSW) 1, the interface circuit between the switch and the PCM line, and the interface circuit between the switch and the PCM line. Circuit (DTI0,1)2,
3. Line testing equipment (TSTE-A, TSTE-B)
4, 5, and a switch (NW) 6 for another station.
PCM回線及びDTI0２の出力路の試験を行う場
合、DTIの試験チヤネルを指定し且つ、他局の
TSTE―Ｂ５の番号を他局に送りTSTE―Ａ４―
TDSW１―DTI0２―PCM回線―DTI1３―NW６
―TSTE―Ｂ５を接続せしめる。この接続の方法
は一般の交換接続と全く同じで、特にその接続の
ために必要な機器については図に示していないし
詳細な言及はしない。この状態で、TSTE―Ａ４
は、TSTE―Ｂ５より送信されて来る信号を受信
確認することによつて全体の通信路の良否判定を
行う。又PCM回線及びDTIの入方路の試験を行
う場合は他局TSTE―Ｂ５よりTSTE―Ａ４に着
信させ、TSTE―Ａ４よりの信号をTSTE―Ｂ５
で受信確認することにより、全体の通話路の良否
判定を行う。 When testing the PCM line and DTI 0 2 output path, specify the DTI test channel and
Send the TSTE-B5 number to another station and TSTE-A4-
TDSW1-DTI 0 2-PCM line-DTI 1 3-NW6
-TSTE- Connect B5. This connection method is exactly the same as a general exchange connection, and the equipment required for this connection is not shown in the diagram or described in detail. In this state, TSTE-A4
determines the quality of the entire communication path by confirming the reception of the signal transmitted from TSTE-B5. Also, when testing the PCM line and DTI input route, the signal from another station TSTE-B5 is received from TSTE-A4, and the signal from TSTE-A4 is sent to TSTE-B5.
By confirming reception at , the quality of the entire communication path is determined.
以上の説明で判るように、従来の回線試験方式
ではDTI及びPCM回線を含めた良否判定はでき
るが、不良の場合、交換機側の障害か伝送路側の
障害かの判定が出来ないという問題点があつた。
As can be seen from the above explanation, conventional line testing methods can determine the pass/fail of DTI and PCM lines, but in the case of a defect, it is not possible to determine whether the fault is on the exchange side or on the transmission line side. It was hot.
本発明の目的は、PCM回線およびPCM回線と
交換機のインターフエース回路の試験を行う際、
PCM回線側即ち伝送路の試験あるいはインター
フエース回路側即ち交換機の試験を別々に行える
手段を与えることにより上記欠点を解決すること
にある。 The purpose of the present invention is to
The object of the present invention is to solve the above drawbacks by providing means for separately testing the PCM line side, that is, the transmission line, or the interface circuit side, that is, the exchange.
本発明によれば、PCM回線のチヤネル対応に
信号の挿脱可能な信号挿脱回路を設け、一方
PCM回線と該PCM回線の交換機側インターフエ
ース回路との間に該PCM回線側と該インターフ
エース回路側を同時に上記信号挿脱回路に引き込
む回路を設けることにより、第１にPCM回線側
を試験する場合は、該引き込み回路によりPCM
回線及びインターフエース回路を該信号挿脱回路
に引き込み、PCM回線の全チヤネルの信号は該
信号挿脱回路を経由して、インターフエース回路
に戻るようにしておき、一方、該PCM回線の任
意に指定される１チヤネルの信号は該信号挿脱回
路により抽出せしめあるいは該指定チヤネルへ特
定信号を挿入せしめることによりPCM回線側の
チヤネル毎の試験を行うことを可能とし、また第
２にインターフエース回路側を試験する場合は、
該引き込み回路により、インターフエース回路、
PCM回線を該信号挿脱回路に引き込み、インタ
ーフエース回路の全チヤネルの信号は該信号挿脱
回路を経由してPCM回線に戻るようにしてお
き、一方インターフエース回路の指定された１チ
ヤネルの信号は該信号挿脱回路により抽出せし
め、あるいは該指定チヤネルへ特定信号を挿入せ
しめることによりインターフエース回路側のチヤ
ネル毎の試験を行うことを可能とすることにより
伝送路側及び交換機側を独立に試験可能とした回
線試験方式が得られる。
According to the present invention, a signal insertion/extraction circuit capable of inserting/extracting signals is provided corresponding to a channel of a PCM line, and one
First, the PCM line side is tested by providing a circuit between the PCM line and the exchange side interface circuit of the PCM line to simultaneously draw the PCM line side and the interface circuit side into the signal insertion/removal circuit. If the PCM
Lines and interface circuits are connected to the signal insertion/removal circuit, and the signals of all channels of the PCM line are returned to the interface circuit via the signal insertion/removal circuit. By extracting the signal of one designated channel by the signal insertion/removal circuit or by inserting a specific signal into the designated channel, it is possible to test each channel on the PCM line side. If testing the side,
The lead-in circuit provides an interface circuit,
The PCM line is drawn into the signal insertion/removal circuit, and the signals of all channels of the interface circuit are returned to the PCM line via the signal insertion/removal circuit, while the signal of one specified channel of the interface circuit is is extracted by the signal insertion/removal circuit, or by inserting a specific signal into the specified channel, it is possible to test each channel on the interface circuit side, thereby making it possible to test the transmission line side and the exchange side independently. A line test method can be obtained.
次に本発明の実施例について図面を参照して説
明する。
Next, embodiments of the present invention will be described with reference to the drawings.
第２図を参照すれば本発明の一実施例は時分割
スイツチネツトワーク（TDSW）１、アナログ
用の出力トランク（OGT）１３、入力トランク
（ICT）１４、PCM回線と交換機とを直接デイジ
タル形式のままインターフエースする回路
（DTI0、DTI1）２，３、回線試験装置（TSTE―
Ａ、TSTE―Ｂ）１０，５、他局の交換スイツチ
ネツトワーク（NW）６、切替回路のリレー接点
t0およびt1を有し、PCM回線のチヤネル対応に信
号の挿脱が可能な信号挿脱回路１１、および
PCM回線側及びインターフエース回路側
（DTI0）を同時に該信号挿脱回路１１に引き込む
ための引き込み回路１２を備えている。 Referring to FIG. 2, one embodiment of the present invention includes a time division switch network (TDSW) 1, an output trunk (OGT) 13 for analog, an input trunk (ICT) 14, and a PCM line and switch directly connected to the switch in digital form. Circuits that interface as they are (DTI 0 , DTI 1 ) 2, 3, line test equipment (TSTE-
A, TSTE-B) 10, 5, Exchange switch network of other station (NW) 6, Relay contact of switching circuit
a signal insertion/removal circuit 11 having t 0 and t 1 and capable of inserting/removing signals corresponding to a PCM line channel;
A pull-in circuit 12 is provided for simultaneously pulling the PCM line side and the interface circuit side (DTI 0 ) into the signal insertion/removal circuit 11.
なお符号Ａ，Ｂ，Ｃは説明に便のために付与さ
れたものであり、またＤ，ＥはTSTE―Ａのスイ
ツチの入端子を示す。 Note that the symbols A, B, and C are given for convenience of explanation, and D and E indicate the input terminals of the switch of TSTE-A.
今、PCM回線側の特定チヤネルの試験を行う
場合、該特定チヤネルの指定及び相手局試験装置
TSTE―Ｂ５の番号を設定してプログラム制御に
より引き込み回路１２のリレー接点t0，t1を動作
せしめ且つ、TSTE―Ａ１０の端子Ｄと信号挿脱
回路１１のＣとの間を接続せしめる。同時に相手
局に番号を送出し相手局TSTE―Ｂ５に指定され
た特定チヤネルを介し着信せしめる。上記交換動
作手順は本発明に直接関係しないので詳しく言及
するのはさける。即ち、被試験チヤネルはTSTE
―Ａ１０の端子Ｄ―TDSW１―信号挿脱回路１
１のＣ―信号挿脱回路１１のＢ―t0・メーク接点
―PCM回線―DTI1３―NW６―TSTE―Ｂ５で接
続される。一方、他のチヤネル例えばCGT１３
―DTI0２―DTI1３あるいはICT１４―DTI0２―
DTI1３間で通話しているチヤネルに対しては、
信号挿脱回路１１のＡ―Ｂで信号をバイパスさせ
ることにより影響を与えないようにしている。又
信号挿脱回路１１のＣの個所は、チヤネル指定情
報により、Ａ―Ｂ間で疎通されている信号列中の
特定チヤネルの信号が抽出できる機能と、Ｃより
TSTE―Ａ１０よりの信号Ａ―Ｂ間の信号列中に
挿入できるような機能とで構成される。例えば
TSTE―Ａ１０より送信した信号は信号挿脱回路
１１でPCM回線の特定チヤネルに挿入され、相
手局TSTE―Ｂ５で受信しチエツクすることが可
能となる。以上のような形でPCM回線側の特定
チヤネルの試験が可能となる。 Now, when testing a specific channel on the PCM line side, specify the specific channel and the partner station test equipment.
The number of TSTE-B5 is set and the relay contacts t 0 and t 1 of the pull-in circuit 12 are operated by program control, and terminal D of TSTE-A 10 and C of the signal insertion/removal circuit 11 are connected. At the same time, the number is sent to the other station and the other station TSTE-B5 receives the call via the designated specific channel. Since the above exchange operation procedure is not directly related to the present invention, a detailed description thereof will be omitted. In other words, the channel under test is TSTE
-Terminal D of A10-TDSW1-Signal insertion/removal circuit 1
1 C - Signal insertion/removal circuit 11 B - t 0 /make contact - PCM line - DTI 1 3 - NW6 - TSTE - Connected with B5. On the other hand, other channels such as CGT13
-DTI 0 2-DTI 1 3 or ICT14-DTI 0 2-
For channels communicating between DTI 1 and 3,
By bypassing the signal at A-B of the signal insertion/removal circuit 11, no influence is caused. In addition, the point C of the signal insertion/removal circuit 11 has the function of extracting the signal of a specific channel in the signal train communicated between A and B based on the channel specification information, and
It consists of a function that can be inserted into the signal train between signals A and B from TSTE-A10. for example
The signal transmitted from the TSTE-A10 is inserted into a specific channel of the PCM line by the signal insertion/removal circuit 11, and can be received and checked by the partner station TSTE-B5. In the manner described above, it is possible to test a specific channel on the PCM line side.
一方、DTI0２の特定チヤネルの試験を行う場
合、該特定チヤネルの指定及び自局回線試験装置
TSTE―Ａ１０の端子Ｅの端子番号を設定して、
プログラム制御により、引き込み回路１２のリレ
ー接点t0，t1を動作せしめ、且つTSTE―Ａ１０
の端子Ｄと信号挿脱回路１１のＣとの間を接続せ
しめ、同時に、DTI0２の指定された特定チヤネ
ルとTSTE―Ａ１０の端子Ｅ間を接続する。即ち
被試験チヤネルはTSTE―Ａ１０の端子Ｄ―
TDSW１―信号挿脱回路１１のＣ―信号挿脱回
路１１のＡ―t1・メーク接点―DTI0２―TDSW
１―TSTE―Ａ１０の端子Ｅで接続される。この
場合も先の場合と同様、他の通話チヤネルは、信
号挿脱回路１１のＡ―Ｂを介し疎通される。この
状態で、TSTE―Ａ１０の端子Ｄより送信した信
号をTSTE―Ａ１０の端子Ｅで受信し、一方
TSTE―Ａ１０の端子Ｅより送信した信号を
TSTE―Ａ１０の端子Ｄで受信することにより
DTI0２の指定チヤネルの正常性即ち交換機側の
正常性が試験できる。 On the other hand, when testing a specific channel of DTI 0 2, the specification of the specific channel and the own station line test equipment are required.
Set the terminal number of terminal E of TSTE-A10,
By program control, the relay contacts t 0 and t 1 of the pull-in circuit 12 are operated, and the TSTE-A10
A connection is made between the terminal D of the signal insertion/removal circuit 11 and C of the signal insertion/removal circuit 11, and at the same time, a connection is made between the designated specific channel of the DTI 0 2 and the terminal E of the TSTE-A10. In other words, the channel under test is terminal D- of TSTE-A10.
TDSW1 - C of signal insertion/removal circuit 11 - A of signal insertion/removal circuit 11 - t 1 /Make contact - DTI 0 2 - TDSW
1-TSTE-Connected at terminal E of A10. In this case, as in the previous case, other communication channels are communicated via AB of the signal insertion/removal circuit 11. In this state, the signal sent from terminal D of TSTE-A10 is received at terminal E of TSTE-A10, and one
The signal sent from terminal E of TSTE-A10
By receiving at terminal D of TSTE-A10
The normality of the designated channel of DTI 0 2, that is, the normality of the exchange side, can be tested.
以上述べた如く、回線（伝送路）側、交換機側
の試験が独立にでき、障害の切り分けが可能とな
る。 As described above, the line (transmission path) side and the exchange side can be tested independently, making it possible to isolate the fault.
本実施例では、TSTE―Ａ、TSTE―Ｂなるも
のを利用しての試験の方法を説明したが、本特許
の請求範囲はPCM回線側及びPCM回線と交換機
とのインターフエース回路回路間に引き込む回路
を設け、且つ、それによりPCM回線のチヤネル
対応の信号挿脱機能を有する信号挿脱回路に回路
側、交換機側に引き込んで試験を行う全ての方式
に及ぶ。 In this embodiment, a test method using TSTE-A and TSTE-B has been explained, but the scope of the claims of this patent is drawn between the PCM line side and the interface circuit between the PCM line and the exchange. It covers all methods of testing by installing a circuit and connecting it to the circuit side and the exchange side into a signal insertion/extraction circuit that has a signal insertion/extraction function compatible with PCM line channels.
本発明は以上説明したように、回線側と交換機
側を同時に引き込む回路及びPCM回線のチヤネ
ル毎に信号の挿脱可能な信号挿脱回路を設けるこ
とにより回線側、交換機側の試験を独立に行え且
つ障害の切り分けが可能とする効果がある。
As explained above, the present invention allows testing of the line side and the exchange side to be performed independently by providing a circuit that connects the line side and the exchange side at the same time, and a signal insertion/removal circuit that can insert/remove signals for each channel of the PCM line. Moreover, it has the effect of making it possible to isolate the failure.
第１図は従来の試験方式を示すブロツク図、第
２図は本発明の一実施例を示したブロツク図であ
る。
１：時分割スイツチネツトワーク（TDSW）、
２，３：PCM回線と交換機のインターフエース
回路（DTI0、DTI1）、５，１０：回線試験装置
（TSTE―Ａ、TSTE―Ｂ）、１３：アナログ用出
トランク（OGT）、１４：アナログ用入トランク
（ICT）、１１：信号挿脱回路、Ａ，Ｂ，Ｃ：信号
挿脱回路１１の端子、１２：引き込み回路、t0，
t1：切り替えリレー接点、Ｄ，Ｅ：TSTE―Ａ１
０の端子、６：交換ネツトワーク（NW）。
FIG. 1 is a block diagram showing a conventional test method, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1: Time division switch network (TDSW),
2, 3: PCM line and exchange interface circuit (DTI 0 , DTI 1 ), 5, 10: Line test equipment (TSTE-A, TSTE-B), 13: Outgoing trunk for analog (OGT), 14: Analog Commercial trunk (ICT), 11: Signal insertion/extraction circuit, A, B, C: Terminals of signal insertion/extraction circuit 11, 12: Lead-in circuit, t 0 ,
t 1 : Switching relay contact, D, E: TSTE-A1
0 terminal, 6: Exchange network (NW).
Claims (1)
形式のまま交換を行わしめる交換方式に於て、
PCM回線のチヤネル対応に信号挿脱可能な信号
挿脱回路を設け、さらにPCM回線と該PCM回線
の交換機側インターフエース回路の間に、該
PCM回線側と該インターフエース回路側を同時
に前記信号挿脱回路に引き込む引き込み回路を設
け、該引き込み回路によりPCM回線及びインタ
ーフエース回路を該信号挿脱回路に引き込み、
1PCM回線の全チヤネルの信号は該信号挿脱回路
を経由して、PCM回線およびインターフエース
回路のいずれか一方に供給しておき、また、
PCM回線の任意に指定された１チヤネルの信号
は該信号挿脱回路により抽出せしめあるいは、該
指定チヤネルへ特定信号を挿入せしめることによ
りPCM回線側のチヤネル毎の信号の授受を行な
うことにより該チヤネルの正常性の試験を行うこ
とを特徴とする回線試験方式。1 In a time-division exchange, in which the PCM line is directly exchanged in digital format,
A signal insertion/removal circuit is provided for each PCM line channel, and a signal insertion/removal circuit is provided between the PCM line and the exchange side interface circuit of the PCM line.
providing a pull-in circuit that simultaneously pulls the PCM line side and the interface circuit side into the signal insertion/removal circuit, and draws the PCM line and the interface circuit into the signal insertion/removal circuit by the pull-in circuit;
The signals of all channels of one PCM line are supplied to either the PCM line or the interface circuit via the signal insertion/removal circuit, and
The signal of one arbitrarily designated channel of the PCM line can be extracted by the signal insertion/removal circuit, or the signal can be exchanged for each channel on the PCM line side by inserting a specific signal into the designated channel. A line test method characterized by testing the normality of the line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4400179A JPS55136759A (en) | 1979-04-11 | 1979-04-11 | Line test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4400179A JPS55136759A (en) | 1979-04-11 | 1979-04-11 | Line test system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55136759A JPS55136759A (en) | 1980-10-24 |
| JPS6210461B2 true JPS6210461B2 (en) | 1987-03-06 |
Family
ID=12679463
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4400179A Granted JPS55136759A (en) | 1979-04-11 | 1979-04-11 | Line test system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55136759A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03102752U (en) * | 1990-02-08 | 1991-10-25 |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6365752A (en) * | 1986-09-06 | 1988-03-24 | Fujitsu Ltd | Test system for digital transmission line interface device |
| JPS6480149A (en) * | 1987-09-22 | 1989-03-27 | Nec Corp | Subscriber line concentrator interface |
-
1979
- 1979-04-11 JP JP4400179A patent/JPS55136759A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03102752U (en) * | 1990-02-08 | 1991-10-25 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55136759A (en) | 1980-10-24 |
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