JPS6211791B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having a structure in which elements are formed in a semiconductor layer on an insulating substrate.

Generally, in structures in which a semiconductor layer is provided on an insulating substrate, such as SOS (Silicon on Sapphire), the crystallinity of the silicon layer is considerably inferior to that of bulk silicon. Specifically, the crystal defect density of the silicon layer of SOS is 10 ⁸ to 10 ⁹ /cm ² ,
This is due to a misfit due to the difference in crystal structure between sapphire and silicon. Thus, a high crystal defect density shortens the carrier lifetime, which is two to three orders of magnitude smaller than that of bulk silicon. This does not pose a problem when the SOS device operates using majority carriers, but when it operates using minority carriers, it increases generation and recombination currents and deteriorates device characteristics. For this reason, product development for devices using SOS technology has been focused on static circuit type MOS integrated circuits, and dynamic circuit type MOS integrated circuits and bipolar integrated circuits have not been developed.

In addition, compressive strain is introduced into the silicon layer of SOS due to the difference in thermal expansion between silicon and sapphire during cooling during crystal growth, and the mobility of carriers in the silicon layer is low due to the large crystal defect density as described above. Smaller than bulk silicon. Of these two factors that affect mobility, the former factor due to compressive strain physically deteriorates the band structure of the silicon layer, so there is essentially no room for improvement other than the selection of crystal orientation. However, it is becoming possible to reduce the latter crystal defect density using crystal growth technology. One of the improvements to such crystal growth technology is optimizing the SOS crystal growth conditions. Crystal growth conditions include crystal growth temperature, crystal growth rate, purity of silane gas for crystal growth and atmospheric gas, etc., and optimization of these is necessary. However, even if crystal growth is performed under such optimized conditions, a considerable amount of crystal defects still exist in the resulting silicon layer, making it difficult to improve the characteristics even if a device is manufactured. stomach. In order to overcome this problem, the present inventor conducted various studies and found that a semiconductor layer with a thin film thickness (approximately 0.2 to 0.4 μm) suitable for device formation was grown on an insulating substrate by vapor phase epitaxy, etc. By implanting ions of silicon, germanium, inert substances, etc. into the semiconductor layer or near the interface of the insulating substrate, the deep part of the semiconductor layer can be etched while keeping the surface of the semiconductor layer relatively high-quality crystal. By making it amorphous and then applying heat treatment, it was possible to grow solid-phase crystals using the surface of the semiconductor layer with good crystallinity, which is separate from the surface of the insulating substrate, as a seed, and it was possible to form a thin semiconductor layer with crystallinity on the insulating substrate. . Although the semiconductor layer formed in this way has a reduced crystal defect density compared to a semiconductor layer obtained by optimizing conventional crystal growth conditions, when considered as a substrate for device manufacturing, it does not necessarily have a high crystal defect density and crystallinity. It wasn't completely satisfying.

Therefore, as a result of further intensive research in light of the above problems, the inventors of the present invention focused on the fact that the crystallinity of the surface of a semiconductor layer grown on an insulating substrate becomes better as the film thickness increases. A thick semiconductor layer is grown by a vapor phase growth method, etc., and the surface of the semiconductor layer with extremely good crystallinity is used as a seed by implanting ions such as silicon into this semiconductor layer and subjecting it to heat treatment in the same way as described above. We have discovered that it is possible to obtain a thick semiconductor layer with intrinsic crystal growth, excellent crystallinity, and high carrier mobility. However, the semiconductor layer formed in this way is thick and becomes an obstacle to miniaturization when forming elements, so at least a part of the semiconductor layer is etched in the film thickness direction and elements are formed in the thin semiconductor layer region. In particular, we have discovered a method for manufacturing semiconductor devices that have significantly superior electrical characteristics and can be highly integrated.

That is, the present invention includes a process of growing a thick semiconductor layer on an insulator, a process of ion-implanting silicon, germanium, or an inert substance into the semiconductor layer, and a process of heat-treating the semiconductor layer to grow a specific crystal, and then growing a semiconductor layer. The method is characterized by comprising a step of etching at least a portion of the semiconductor layer in the film thickness direction, and a step of forming an element in the etched thin semiconductor layer region.

Insulators used in the present invention include, for example, single-crystal sapphire or spinel substrates, amorphous sapphire, spinel, or glass substrates, or insulators such as silicon oxide films and silicon nitride films provided on semiconductor substrates. Examples include membranes and the like. However, as an insulator, single crystal sapphire,
The use of a spinel substrate is effective because a semiconductor layer having a surface with better crystallinity can be formed during growth of the semiconductor layer.

When growing the semiconductor layer in the present invention, it is necessary to make the film thick enough because the semiconductor layer is to have a surface with excellent crystallinity. The thickness of such a semiconductor layer varies slightly depending on the growth conditions, but since the surface crystallinity is maximized when the film thickness is about 2 to 10 μm or more, the thickness can be made to be 1.0 μm or more considering the allowable range of crystallinity. desirable. As a means for growing this semiconductor layer, an epitaxial growth method may be used when the insulator is single crystalline, and a normal vapor phase growth method may be used when the insulator is amorphous.

Ion implantation in the present invention is used to maintain the surface of the semiconductor layer in a crystalline state, to make the deep part (in the layer or near the insulator interface) amorphous, and to create a structure that allows solid-phase crystal growth using the crystals on the surface as seeds. Let's do it. Suitable impurities for such implantation are inert substances such as silicon, germanium, or argon.

The heat treatment in the present invention is carried out in order to use crystals on the surface of the semiconductor layer as seeds to grow solid-phase crystals in the deep amorphous portion. As such a heat treatment means, for example, a normal heat treatment method or a method of heating by irradiating with an energy beam such as a laser beam or an electron beam can be adopted.

Etching in the present invention thins at least the element formation region of a thick semiconductor layer to miniaturize the element.
This is done to obtain a film thickness suitable for improving high frequency characteristics. However, if only a part of the thick semiconductor layer is etched in the film thickness direction and the other regions remain thick, this thick semiconductor region can be used for functional parts different from the thin semiconductor layer region (for example, low-resistance wiring, high-voltage elements, etc.). etc.).

Next, embodiments of the present invention will be described with reference to the drawings.

Example 1 [] First, as shown in FIG.
Vapor phase epitaxial growth at 950°C to a thickness of 1.0
A crystalline silicon layer 2 of .mu.m was grown. The silicon layer 2 thus obtained had much better crystallinity on the surface than in the deeper part.

[] Next, silicon ions were implanted into the silicon layer 2 at an acceleration voltage of 560 keV and a dose of 1×10 ¹⁵ /cm ² . In this case, the sapphire substrate 1 was tilted at an angle of 7° with respect to the ion beam so as not to cause channel ring. By such ion implantation, as shown in FIG. 1B, good quality crystals in an as-grow state remained on the surface of the silicon layer 2, and the deep portion became amorphous silicon 3'. Note that during silicon ion implantation, the acceleration voltage and dose are high, so the silicon layer 2 is
℃ or higher, resulting in the inconvenience that incomplete solid-phase crystal growth occurs during this ion implantation. In such a case, it is necessary to cool the silicon layer 2 and maintain it at a low temperature, either by cooling it to 77° with liquid nitrogen or by cooling it with a Freon gas refrigerant. Continuing,
Heat treatment was performed at a temperature of 560° C. for 2 hours in an N ₂ gas atmosphere. At this time, solid phase crystal growth of amorphous silicon occurs at a rate of about 100 Å/min using the high quality silicon crystal on the surface of the silicon layer 2 as a seed.
The high quality surface crystallinity during epitaxial growth was spread throughout, and a silicon layer 2' with significantly excellent crystallinity was formed.

[] Next, the portion of the solid-phase crystal grown silicon layer 2' where the device was to be formed was selectively etched by 0.7 μm in the film thickness direction by photolithography using KOH as an etchant to form a thin silicon layer region 4 with a thickness of 0.3 μm. Continuing, thin silicon layer region 4
A p-type region 5 and an n-type region 6 were formed by selectively doping boron and arsenic to produce a pn junction diode. Thereafter, the thick (1.0 μm thick) silicon layer 2' portion in contact with the p-type region 5 is doped with boron at a high concentration, and the thick silicon layer 2' portion in contact with the n-type region 6 is doped with arsenic at a high concentration. A p ⁺ type region 7 and an n ⁺ type region 8 were formed by doping at a concentration (as shown in FIG. 1c).

Although the pn junction diode obtained in Example 1 was manufactured in the thin silicon layer region 2' (normally, crystallinity is poor near the sapphire interface), the crystallinity was significantly improved. To be there,
The reverse breakdown voltage is high and the reverse leakage current is also small. In addition, a pn junction diode has a small junction area, and accordingly, the junction capacitance can be reduced, so it can be used as a diode for ultra-high frequencies. Moreover, it was formed in the thick silicon layer.
The p ⁺ type region 7 and the n ⁺ type region 8 can be used as electrodes or wiring. If used as wiring,
It is possible to lower resistance and enable high-speed operation.

Furthermore, in Example 1, an i layer (intrinsic layer) is formed between the p-type region 5 and the n-type region 6 to form a p-i-n type (or p-v-n type, p-π-
n-type), it becomes possible to manufacture pin diodes for ultra-high frequencies.

Example 2 The thin silicon layer region 4 in the solid phase crystal grown silicon layer 2' on the sapphire substrate 1 obtained in Example 1 was doped with boron to make it p-type,
A gate electrode 10 made of polycrystalline silicon was formed on this region 4 with a gate oxide film 9 interposed therebetween. Subsequently, using the gate electrode 10 as a mask, the p-type silicon layer region 4 was selectively doped with arsenic to form an n-type source 11 and drain 12, thereby forming an n-channel MOS transistor. Thereafter, the thick silicon layer portions on the source and drain 11 and 12 sides were heavily doped with arsenic to form n ⁺ regions 8 ₁ and 8 ₂ (as shown in FIG. 2).

In the MOS transistor obtained in Example 2, the crystallinity of the thin silicon layer region 4 forming the source, drain, and channel regions is extremely good, so that the drain breakdown voltage is improved, the drain leakage current is reduced, and the mobility is improved. I was able to achieve this. Moreover, by forming the source and drain in the thin silicon layer region, the junction capacitance is reduced, and the n ⁺ type region 8 ₁ , 8
By using resistor ₂ as the source and drain lead electrodes, a MOS transistor capable of high-speed operation was obtained. Furthermore, by applying such a structure to an integrated circuit, higher integration can be expected.

Example 3 The solid phase crystal grown silicon layer 2' on the sapphire substrate 1 obtained in Example 1 was selectively etched in the film thickness direction to form a thin silicon layer region 4' with a thickness of 0.4 μm. Next, the silicon layer region 4' is selectively doped with arsenic to form an n-type collector region, and further boron is selectively doped into the same region to form a p-type base region 13 and an n ⁺ A type emitter region 14 was formed to produce an npn type bipolar transistor. Thereafter, the portion of the thick silicon layer in contact with the collector region was doped with arsenic at a high concentration to form an n ⁺ region 8' as a collector lead-out electrode (as shown in FIG. 3).

The obtained npn bipolar transistor has high emitter injection efficiency and significantly improved current amplification factor.

Example 4 The solid phase crystal grown silicon layer on the sapphire substrate 1 obtained in Example 1 was selectively etched in the film thickness direction to form a thin silicon layer region 4' with a thickness of 0.4 μm. Next, after doping the entire surface with arsenic to make it n-type, an n-type thin silicon region 4' is formed.
When a p-type region 5 ₁ , an n-type region 6 ′, and a p-type region 5 ₂ were sequentially formed by selectively doping boron, arsenic, and boron into a part of - I was able to create the n switch (SCR).

Note that the semiconductor layer of the semiconductor device manufactured according to the present invention is not limited to the structure of Examples 1 to 4 above. For example, as shown in FIG.
A semiconductor device may be manufactured using a structure in which the solid phase crystal grown silicon layer 2' is selectively etched to form a thin silicon layer region 4, and then an epitaxial layer 15 is formed thereon. As shown in FIG. 6, the solid phase crystal grown silicon layer 2' of the sapphire substrate 1 is selectively etched to form a thin silicon layer region 4, and Si ₃ N ₄ ,
A structure in which an insulating layer 16 of SiO ₂ , Al ₂ O ₃ or the like is provided and then a solid phase crystal grown silicon layer 17 is formed on this insulating layer 16 according to the first embodiment may be used. In such a structure, elements can be formed in both the thin silicon layer region 4 of the lower solid phase crystal grown silicon layer 2' and the upper solid phase crystal grown silicon layer 17, making it possible to manufacture three-dimensional integrated circuits. .

As described in detail above, according to the present invention, a semiconductor device having various effects listed below can be manufactured.

(1) While maintaining a good crystalline state, a small area of p-
Since an n-junction can be formed, the pn junction capacitance can be reduced, making it suitable for ultra-high frequencies, and making it possible to manufacture high-speed, high-density integrated circuits.

(2) By improving crystallinity, it is possible to reduce leakage current, improve breakdown voltage, and improve carrier lifetime, making it possible to manufacture high-performance devices and operate using a small number of carriers.
It also becomes possible to manufacture MOS dynamic RAM, bipolar devices, p-n-p-n switch elements, etc.

(3) When the thickness of the silicon layer becomes thinner for devices with an SOS structure, how to lower the wiring resistance becomes a very big problem. In contrast,
When etching a thick semiconductor layer to form a thin semiconductor layer region, if you etch the thick semiconductor layer so that it remains and make the thick semiconductor layer part n ⁺ type and p ⁺ type and use it for wiring, the element formation area can be Even when thinned, the layer resistance does not increase, making it extremely effective for ultra-high-speed LSIs.

(4) By forming two or more solid-phase crystal-grown semiconductor layers in the film thickness direction, a three-dimensional integrated circuit with fewer steps can be manufactured.

[Brief explanation of the drawing]

1A to 1C are cross-sectional views showing the manufacturing process of a diode in Example 1 of the present invention, and FIGS. 2 to 4 are MOSs obtained in Examples 2 to 4 of the present invention, respectively.
transistor, bipolar transistor, p-n
-A sectional view showing a pn switch element, and FIGS. 5 and 6 are sectional views of an SOS showing a modification of the present invention. DESCRIPTION OF SYMBOLS 1... Sapphire substrate (insulator), 2... Silicon layer, 2'... Solid phase crystal growth silicon layer, 3... Amorphous silicon layer, 4... Thin silicon layer region, 5, 5
_{1,5 2} ...p type region, 6,6'...n type region, 10
...gate electrode, 11...n type source, 12...n type drain, 13...p type base region, 14...n ⁺ type emitter region.

Claims (1)

[Claims] 1 A step of growing a thick semiconductor layer on an insulator, a step of ion-implanting silicon, germanium, or an inert substance into this semiconductor layer, and a step of heat-treating the semiconductor layer to grow a solid-phase crystal, and then at least one step of the semiconductor layer. 1. A method of manufacturing a semiconductor device, comprising the steps of: etching a portion of the semiconductor layer in the film thickness direction; and forming an element in the etched thin semiconductor layer region.