JPS621238B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timer function of a digital display type electronic watch.

Recent digital display type electronic watches have become more and more multi-functional, making them more complex to operate and requiring a large number of externally operated switches. Therefore, as a future problem, it has become necessary to simplify the operability as much as possible.

The purpose of this invention is to provide a clock with a timer function that solves the problem and is easy to operate. The timer function displays the elapsed time and gives a warning when the set time has elapsed, and also requires a monitor display of the set time. Conventionally, one external operation switch was required to perform this monitor display. However, externally operated switches (hereinafter referred to as "switches") increase costs, and at the same time, as the number of switches to be operated increases, the spacing between the switches becomes smaller in a small watch case, making it difficult to operate and understand the function of each switch. It becomes difficult to do so. In order to compensate for the above-mentioned drawbacks, the present invention saves the number of switches and simplifies the operability by monitoring the set time when the timer is in use.

As described above, the present invention not only improves the operability of increasingly complex multi-function digital display type electronic watches, but also greatly contributes to reducing the cost of watch cases by reducing the number of switches.

Next, specific embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a switch arrangement diagram of the present invention. _S1 is a switch for starting and stopping the timer function. _S2 is a mode changeover switch.
SA, SB indicate each step-down position of Reuse S,
At the SA position, the normal display state is taken, and at the SB position, the correction state is taken.By rotating the reuse S in this correction state SB, the correction pulse generation circuit 4j, which will be described later, is activated.
The correction pulse is configured to be generated from.

FIG. 2 shows a display section of the present invention. In time display mode, press switch S ₂ to switch to timer function display.
By pulling it out to the position and rotating the Reuse S, a timer set mode can be used in which the timer time is set. Further, after setting the timer time, push the reuse S into the SA position and issue a timer start command by pressing the switch _S1 , thereby setting the timer operation mode as shown in C. By pulling out the reuse S again to the SB position in the mode in which the timer is operating, a timer monitor mode is set in which the timer time set in the mode I can be monitored.

When the timer is returned to the reuse SA position, the timer enters the timer operation mode H, which displays the remaining time during operation, and performs subtraction counting operation until the remaining time reaches 0. When the remaining time reaches 0, the timer warning circuit 10, which will be described later, is activated. It emits sound.

Incidentally, the timer counting operation can be stopped by pressing switch _S1 in the above modes.

FIG. 3 is a block wiring diagram of the present invention. Reference numeral 1 designates an oscillation circuit, which sends a signal a of a reference frequency (32768 Hz) to a frequency dividing circuit 2, and the frequency dividing circuit 2 creates a 1 Hz signal b. 3 is a time system counting counter, which converts the 1 Hz signal b into a time signal k. 4 is an input control circuit, which closes the switches S ₁ , S ₂ and the reuse S at the pulled out position SB.
SB' and reuse S at this pull-out position SB.
Switch group SB that moves in conjunction with the rotation operation of
N is clock-controlled by the input control clock c of the frequency dividing circuit 2 to generate each control signal. signal d
is a time adjustment signal, e is a timer counting circuit control signal group, f is a timer latch read signal, and g is a display switching signal group. Reference numeral 5 denotes a timer counting circuit, which is composed of an up-down counter, and is configured to set a set time using a timer counting circuit control signal group e and a 1 Hz signal b, and perform timer operations such as start and stop. 6 is a timer latch circuit, which reads the latch with the latch read signal f while the timer counting circuit 6 is being corrected;
It stores the set time, which is the output signal of the timer display signal group h of the timer counting circuit 5, and outputs a preset signal i of the timer counting circuit 5 at the time of repeat. 7 is a display switching circuit, which receives time display signals k,
Either the timer display signal j or the timer latch display signal (timer monitor display signal) q is selected as the display signal l by the signal of the display switching signal group g and sent to the decoder 8, and the seven segment signal m
The digital display body 9 is configured to display the image on the digital display 9. 11 is a timer warning circuit;
The zero detection circuit 10 detects that the timer display signal j has become 0, and when the detection signal p reaches the "H" level, an audible warning is issued.

FIG. 4 is a specific circuit diagram of the input control circuit of the present invention.

4a, 4b, and 4d are D-type flip-flops (hereinafter referred to as DFF). Switch S ₁ is DFF4a
The switch _S2 is connected to the D input of DFF4b. 4c is a NAND gate, which receives the outputs of DFFs 4a and 4b and whose output is connected to the D input of DFF 4d. The clock inputs of DFF4a, 4b, 4d are connected to the input control clock c of frequency divider circuit 2, and the opening/closing of switches _S1 , _S2 are converted into one shot signals by DFF4a, 4b, 4d and NOR gates 4e, 4h. ing. When the switch SB' is closed (the reuse pull-out position SB is in a corrected state), the NOR gates 4e and 4h are closed to prevent the input signals from the switches S ₁ and S ₂ from passing through. Switch SB-N is a rotary switch that operates in conjunction with switch SB', and is a reuse type switch.Rotary switch SB
The rotor of the rotary switch SB-N is switched at three points in one rotation, but in this example, the rotor of the rotary switch SB-N is sped up from the Reuse S via a speed increasing gear (not shown). , Reuse 1
The rotor of the rotary switch SB-N is set to rotate approximately 50 to 60 times.
The opening and closing of each contact of the rotary switch SB-N is converted into a one-shot pulse by a correction pulse generation circuit 4j, and the contact is connected to the input of an AND gate 4k. AND gate 4k is a switch
The gate 4k is connected to SB', and only while the switch SB' is closed, the gate 4k is opened to allow the correction pulse to pass. 4i is a flip-flop (hereinafter referred to as FF) whose output state is inverted by a clock, and its output is inverted by a one-shot signal (output of NOR gate 4k) caused by opening and closing of switch _S2 . FF4
When the Q output of i is “H” level (i.e., q ₁ =
When the Q output is at the "L" level (that is, when q ₁ is at the "L" level), the display is switched to a timer display. 4g
is for start/stop of timer counting circuit 5.
It is FF. 4l is a DFF whose D input is connected to _VDD . The clock input of DFF4l is
The AND gate 4t is connected to the output of the AND gate 4t, which opens the gate when the output of the FF4i is at the "H" level (that is, the timer display state), and when the switch SB' is closed and is in the correction state, the AND gate 4t opens the gate (AND gate After the first pulse is output, the output Q of DFF4l becomes "H" level. Since the reset terminal of the DFF 4l is connected to the switch SB' via the inverter 4u, it is always in the reset state (that is, the output Q of the DFF 4l is at the "L" level) except in the correction state. The output signal _e3 of the AND gate 4s is
This is a preset signal for the timer counting circuit 5, and the contents of the counter of the timer counting circuit 5 are read through only the first correction pulse in the timer correction state.
Match with timer latch signal group i. 4r is an AND gate for creating a correction pulse signal _e2 for the timer counting circuit 5, and
The set time of the timer counting circuit 5 is corrected through the correction pulses starting from the pulse number. 4q is an AND gate, and the AND gate 4q opens when the time is displayed (when the Q output of FF4i is at "H" level).
By rotating the reuse S at the SB position of the reuse S, the correction pulse d from the correction pulse generation circuit 4j is applied to the AND gate 4k and the AND gate 4q.
The signal is applied to the time counting circuit 3 through the time correction circuit 3, and the time is corrected. 4p is an AND gate, which pulls out the reuse S to the SB position so as to close the switch SB' when the output of FF4i is at the "H" level, and applies the display switching signal _g3 from the AND gate 4p to the display switching circuit 7 to lock the timer latch. The contents of the circuit 6 (timer monitor display signal q) are displayed on the digital display 9.
4n is an AND gate and is in timer mode (FF
4i output is “H” level) and the switch is
When SB' is open, the signal input through the inverter 4m causes the display switching signal _g2 , which is the output of the AND gate 4n, to go to "H" level, and the timer display signal j, which is the content of the timer counting circuit 5, is digitally converted. It is displayed on the display unit 9. Also, switch
When the output Q of the FF 4i is set to the "H" level by the operation _S2 , the display switching signal _g1 of the "H" level is supplied to the display switching circuit 7, and the digital display 9 displays the time. Furthermore, when the output Q of the DFF4l is at the "H" level, it becomes the timer latch read signal f and the up/down switching signal _e4 of the counter of the timer counting circuit 5.
Make the counter count up.

Next, the operation will be explained. First, open and close switch _S2 in time display mode, and set the output of FF4i to “H”.
level (timer display state). Next, when the switch SB' is closed to enter the correction state, the display switching signal _g3 goes to the "H" level, and the timer set mode becomes LOW. In this state, the output Q of the DFF4l is still at the "L" level, but when the switch SB-N starts rotating, the output Q of the DFF4l goes to the "H" level with the first correction pulse.
At the same time as setting the timer latch circuit 6 to the latch read state (that is, setting the state of the latch read signal f to the "H" level), a signal of e ₄ = "H" level is applied to the UP/DOWN terminal of the timer counting circuit 5. The timer counting circuit 5 is designated for up counter operation. The second and subsequent pulses of the correction pulses of the switch SB-N are applied to the input of the timer counting circuit 5 as a timer correction pulse signal e ₂ through the AND gate 4r, and are applied to the counter of the timer counting circuit 5 and the timer latch circuit. Simultaneously change the memory contents of the 6 latches and set the timer time. After completing the setting, return the reuse S to the SA position, open the switch SB, set the output Qe ₁ of the FF4g to "H" level by pressing the switch _S1 , start the timer, and output the 1Hz signal b from the frequency divider circuit 2. is counted by the timer counting circuit 5 to set the timer operation mode C. At this time
Since DFF4l has been reset by the output signal of inverter 4u, the output Q of DFF4l is at "L" level. The timer counting circuit 5 is set to a down-counting state by the up-down switching signal e ₄ =“L” level. When the reuse S is pulled out to the SB position again and the switch SB' is closed before the counter contents of the timer counting circuit 5 reach 0, the display switching signal _g3 goes to "H" level and the display switching circuit 7 switches the digital display 9 on. The display content takes the timer monitor mode which displays the contents of the timer monitor display signal q, but DFF4l
Since the output Q remains at the "L" level, the counter of the timer counting circuit 5 continues to count down. When the reuse S is pushed into the SA position again, the switch SB' is opened, and the content displayed on the digital display 9 is the timer counting circuit display signal j.
The timer operation mode is set to display the contents of .
Further, the timer count progresses and the timer counting circuit 5
When the timer display signal j becomes 0, the zero detection circuit 1
The output signal p of 0 becomes "H" level, and the timer warning circuit 11 generates a sound.

As described above, in the present invention, the external operation switch required for setting the timer time in the timer counting circuit also functions as a switch for displaying the contents of the set timer time on a monitor when the timer counting operation state is entered. , "timer time"
The switch required to set the "timer time" and the switch for monitoring the "timer time" have the same "timer time".
The switches have common and strongly related functions, which can increase the user's understanding of the functions of the switches that have these dual functions, greatly reducing the number of erroneous operations. Since there is no need to provide an independent dedicated monitor switch, the number of external operation switches for the entire electronic watch can be reduced, and the intervals between the external operation switches installed on the watch case as well as the watch case can be adjusted to make it easier to operate. The number of externally operated switches, which was one of the important causes of cost increase in the past, can be reduced by one by processing the circuit, and the cost can be reduced accordingly. It has effects such as measuring.

[Brief explanation of the drawing]

FIG. 1 is a plan view of the electronic wristwatch of the present invention, FIG. 2 is a display state diagram showing a typical display state of the electronic wristwatch of FIG. 1, FIG. 3 is a block wiring diagram of the present invention, and FIG. 3 is a detailed circuit diagram of the main parts of FIG. 3; FIG. DESCRIPTION OF SYMBOLS 1... Oscillation circuit, 2... Frequency division circuit, 3... Time counting circuit, 4... Input control circuit, 5... Timer counting circuit, 6... Timer latch circuit, 7... Display switching circuit, 8... ...Decoder, 9...Display device,
10...Zero detection circuit, 11...Timer, warning circuit, S...Reuse, _S1 , _S2 , SB'...External operation switch, SA, SB...Push/pull position of reuse S.

Claims (1)

[Claims] 1. A timer counting circuit that has a function of switching and displaying a time display function and a timer display function on the same display device, a first external operation switch that switches between the time display function and the timer display function, and the counting circuit. and a second external operation switch for setting the timer time in a timer latch circuit, the electronic timepiece comprising an output of a circuit means for storing the operation state of the first external operation switch and the second external operation. The gate means receives the operation output of the switch as an input, and has a switching control signal input terminal connected to the output of the gate means, and displays time information and the timer count to the display device according to the type of the switching control signal. The gate means includes a display switching circuit that selects and outputs one of the contents of the circuit and the contents of the timer latch circuit, and the gate means has circuit means for storing the operation state of the first external operation switch on one side. circuit means for generating a control signal for outputting time information to the display switching circuit when in one state, and for storing the operating state of the first external operation switch to the display switching circuit when in the other state; circuit means for generating a control signal for outputting the contents of the timer counting circuit and for storing the operation state of the first externally operated switch is in the other state and when the second externally operated switch is operated; A digital display type electronic timepiece, characterized in that it is configured to generate a control signal for causing the display switching circuit to output the contents of the timer latch circuit when an output is generated.