JPS6213817B2 - - Google Patents
Info
- Publication number
- JPS6213817B2 JPS6213817B2 JP56191132A JP19113281A JPS6213817B2 JP S6213817 B2 JPS6213817 B2 JP S6213817B2 JP 56191132 A JP56191132 A JP 56191132A JP 19113281 A JP19113281 A JP 19113281A JP S6213817 B2 JPS6213817 B2 JP S6213817B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit board
- electrodes
- insulator
- solder bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07231—Techniques
- H10W72/07236—Soldering or alloying
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
この発明は、集積回路基板をフリツプチツプ方
式で、セラミツク基板に実装する際の製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a manufacturing method for mounting an integrated circuit board on a ceramic substrate using a flip-chip method.
従来この種の製造方法としては、第1図A〜F
に示すものがあつた。図において、1は集積回路
基板、2は集積回路基板側電極、3は絶縁膜、4
は電気メツキの際集積回路基板側に電位を与える
ためのCr―Cu等の導電性物質、5は電極部を選
択的にメツキするための絶縁体、7はハンダバン
プ、6はハンダと導電性物質4の接続を強化する
ためのCu等の金属、8はセラミツク基板、9は
セラミツク基板の電極である。 Conventionally, this type of manufacturing method is shown in Figures 1 A to F.
I found the one shown here. In the figure, 1 is an integrated circuit board, 2 is an electrode on the integrated circuit board side, 3 is an insulating film, and 4 is an integrated circuit board.
is a conductive material such as Cr-Cu for applying a potential to the integrated circuit board side during electroplating, 5 is an insulator for selectively plating the electrode part, 7 is a solder bump, and 6 is solder and a conductive material 4 is a metal such as Cu to strengthen the connection, 8 is a ceramic substrate, and 9 is an electrode of the ceramic substrate.
次に、製造過程について説明する。 Next, the manufacturing process will be explained.
工程(A)
第1図Aに示すように、集積回路基板1上に
Al等の電極2を形成し、絶縁膜3により、電極
2の部分以外をマスクする。Step (A) As shown in Figure 1A, on the integrated circuit board 1
An electrode 2 made of Al or the like is formed, and a portion other than the electrode 2 is masked with an insulating film 3.
工程(B)
第1図Bに示すように、全面にCr―Cu等の導
電性物質4を蒸着する。Step (B) As shown in FIG. 1B, a conductive material 4 such as Cr--Cu is deposited on the entire surface.
工程(C)
絶縁体5により電極部2以外の部分をマスク
し、導電性物質4に電位を与え、電気メツキによ
り、第1図Cに示すようにCu等の金属6及びハ
ンダバンプ7を形成する。Step (C) Parts other than the electrode part 2 are masked with an insulator 5, a potential is applied to the conductive substance 4, and a metal 6 such as Cu and a solder bump 7 are formed by electroplating as shown in FIG. 1C. .
工程(D)
エツチング液により第1図Dに示すように絶縁
体5及び導電性物質4をエツチングする。Step (D) The insulator 5 and the conductive material 4 are etched using an etching solution as shown in FIG. 1D.
工程(E)
加熱することにより、ハンダバンプ7を溶か
し、第1図Eのように形を整える。Step (E) By heating, the solder bumps 7 are melted and shaped as shown in FIG. 1E.
工程(F)
ハンダバンプ7を溶かし集積回路基板1と、セ
ラミツク基板8を第1図Fに示すように接合す
る。Step (F) Solder bumps 7 are melted and integrated circuit board 1 and ceramic substrate 8 are joined as shown in FIG. 1F.
従来の製造方法は、以上の様に構成されている
ので、第1図Fに示す様に、ハンダバンプ7が横
方向に広がり、高さhが小さくなる。そのため、
集積回路の動作時、集積回路基板の温度が上昇す
ると、集積回路基板1と、セラミツク基板8の熱
膨張係数の違いから生じる横方向の応力を、ハン
ダバンプ7の弾性で吸収することが出来ないた
め、集積回路基板の周辺部でバンプがはがれる等
の欠点があつた。 Since the conventional manufacturing method is configured as described above, as shown in FIG. 1F, the solder bump 7 spreads laterally and the height h becomes smaller. Therefore,
When the temperature of the integrated circuit board increases during operation of the integrated circuit, the elasticity of the solder bumps 7 cannot absorb the lateral stress caused by the difference in coefficient of thermal expansion between the integrated circuit board 1 and the ceramic board 8. However, there were drawbacks such as bumps peeling off at the periphery of the integrated circuit board.
この発明は、上記の様な従来のものの欠点を除
去するためになされたもので、集積回路の発熱の
結果発生する横方向の応力をハンダバンプ7の弾
性で吸収することができる様に、ハンダバンプを
細長く形成するための製造方法を提供することを
目的としている。 This invention was made in order to eliminate the above-mentioned drawbacks of the conventional ones, and the solder bumps are designed so that the elasticity of the solder bumps 7 can absorb the lateral stress generated as a result of the heat generation of the integrated circuit. It is an object of the present invention to provide a manufacturing method for forming an elongate shape.
以下、この発明の一実施例を図について説明す
る。第2図a〜eにおいて1は集積回路基板、2
は集積回路基板側電極、3は絶縁膜、4は電気メ
ツキの際、集積回路基板側に電位を与えるための
Cr―Cu等の導電性物質、5は電極2の部分を選
択的にメツキするための絶縁体、7はハンダバン
プ、6はハンダと4の導電性物質の接続を強化す
るためのCu等の金属、8はセラミツク基板、9
はセラミツク基板側の電極である。 An embodiment of the present invention will be described below with reference to the drawings. In Fig. 2 a to e, 1 is an integrated circuit board, 2
is an electrode on the integrated circuit board side, 3 is an insulating film, and 4 is an electrode for applying a potential to the integrated circuit board side during electroplating.
A conductive material such as Cr-Cu, 5 an insulator for selectively plating the electrode 2, 7 a solder bump, and 6 a metal such as Cu to strengthen the connection between the solder and the conductive material 4. , 8 is a ceramic substrate, 9
is the electrode on the ceramic substrate side.
次に本発明の製造工程について説明する。 Next, the manufacturing process of the present invention will be explained.
工程(a)
第2図aに示すように集積回路基板1の上に電
極2を形成し、絶縁膜3により電極2の部分以外
をマスクする。Step (a) As shown in FIG. 2a, an electrode 2 is formed on an integrated circuit substrate 1, and a portion other than the electrode 2 is masked with an insulating film 3.
工程(b)
第2図bに示すように全面にCr―Cu等の導電
性物質4を蒸着する。Step (b) As shown in FIG. 2b, a conductive material 4 such as Cr--Cu is deposited on the entire surface.
工程(c)
電極2の部分以外をマスクする絶縁体5を厚く
(例えば50μm程度)形成し、導電性物質4に電
位を与え、電気メツキにより、第2図cに示すよ
うにCu等の金属6及びハンダバンプ7を形成す
る。Step (c) A thick insulator 5 (for example, about 50 μm) is formed to mask the area other than the electrode 2, a potential is applied to the conductive material 4, and a metal such as Cu is formed by electroplating as shown in FIG. 2c. 6 and solder bumps 7 are formed.
工程(d)
ハンダバンプ7を溶かし集積回路基板1とセラ
ミツク基板8を第1図dに示すように接続する。Step (d) Solder bumps 7 are melted to connect integrated circuit board 1 and ceramic substrate 8 as shown in FIG. 1d.
工程(e)
エツチング液により第2図eに示すように絶縁
体5及び導電性物質4をエツチングする。なお、
上記実施例では電気メツキによるハンダバンプ形
成プロセスに対する製造法を示したが、蒸着によ
るハンダバンプロ形成プロセスにおいては、全面
に形成する電気メツキのための導電体4は不要で
あるので、絶縁体5が収縮性を持つならば、集積
回路基板1とセラミツク基板8を接合後、絶縁体
5を除去せずそのまま残しておいてもよい。Step (e): The insulator 5 and the conductive material 4 are etched using an etching solution as shown in FIG. 2e. In addition,
In the above embodiment, a manufacturing method for a solder bump formation process by electroplating was shown, but in the solder bump formation process by vapor deposition, the conductor 4 for electroplating, which is formed on the entire surface, is not required, so the insulator 5 shrinks. If it has properties, the insulator 5 may be left as is without being removed after the integrated circuit board 1 and the ceramic substrate 8 are bonded.
以上のように、この発明によれば、ハンダバン
プ7の高さhを長くすることができるので、集積
回路の動作時の発熱が原因となつて生じる。集積
回路基板及びセラミツク基板間の応力をハンダバ
ンプ7の弾性により吸収することができる。 As described above, according to the present invention, the height h of the solder bumps 7 can be increased, so that heat generation during operation of the integrated circuit is caused. The stress between the integrated circuit board and the ceramic board can be absorbed by the elasticity of the solder bumps 7.
第1図A〜Fは、従来のフリツプチツプ実装構
造の製造方法を説明するための断面図、第2図a
〜eは本発明の一実施例によるフリツプチツプ実
装構造の製造方法を説明するための断面図であ
る。
1は集積回路基板、2は電極、3は絶縁膜、4
は導電性物質、5は絶縁体、6は金属、7はハン
ダバンプ、8はセラミツク基板、9は電極、な
お、図中同一符号は同一または相当部分を示す。
FIGS. 1A to 1F are cross-sectional views for explaining a conventional method of manufacturing a flip-chip mounting structure, and FIG.
-e are cross-sectional views for explaining a method of manufacturing a flip-chip mounting structure according to an embodiment of the present invention. 1 is an integrated circuit board, 2 is an electrode, 3 is an insulating film, 4
5 is a conductive material, 5 is an insulator, 6 is a metal, 7 is a solder bump, 8 is a ceramic substrate, and 9 is an electrode. In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (1)
形成し、上記基板に設けられた電極部以外をマス
クする厚い絶縁体を形成し、電気メツキにより上
記電極部にハンダバンプを形成し、集積回路基板
側の電極と、セラミツク基板側の電極とをハンダ
バンプの融解により接続した後、上記絶縁体及び
導電性物質を除去することを特徴とするフリツプ
チツプ実装構造の製造方法。 2 集積回路基板に設けられた電極部以外にマス
クする厚い絶縁体を形成し、蒸着等により該電極
部にハンダバンプを形成し、集積回路基板側の電
極とセラミツク基板側の電極とをハンダの融解に
より接続した後、上記絶縁体を除去することを特
徴とするフリツプチツプ実装構造の製造方法。[Claims] 1. A conductive material is uniformly formed on the entire surface of an integrated circuit board, a thick insulator is formed to mask areas other than the electrode parts provided on the board, and the electrode parts are covered with electroplating. A method for manufacturing a flip-chip mounting structure, which comprises forming solder bumps, connecting electrodes on the integrated circuit board side and electrodes on the ceramic substrate side by melting the solder bumps, and then removing the insulator and conductive substance. 2. Form a thick insulator to mask areas other than the electrodes provided on the integrated circuit board, form solder bumps on the electrodes by vapor deposition, etc., and melt the solder between the electrodes on the integrated circuit board side and the electrodes on the ceramic substrate side. 1. A method for manufacturing a flip-chip mounting structure, which comprises removing the insulator after the connection is made.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56191132A JPS5892229A (en) | 1981-11-27 | 1981-11-27 | Manufacture of flip chip mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56191132A JPS5892229A (en) | 1981-11-27 | 1981-11-27 | Manufacture of flip chip mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5892229A JPS5892229A (en) | 1983-06-01 |
| JPS6213817B2 true JPS6213817B2 (en) | 1987-03-28 |
Family
ID=16269405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56191132A Granted JPS5892229A (en) | 1981-11-27 | 1981-11-27 | Manufacture of flip chip mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5892229A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63293867A (en) * | 1987-05-26 | 1988-11-30 | Matsushita Electric Works Ltd | Semiconductor device |
-
1981
- 1981-11-27 JP JP56191132A patent/JPS5892229A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5892229A (en) | 1983-06-01 |
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