JPS6213875B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal processing circuit suitable for application to a VTR for receiving, recording and reproducing television broadcasts.

First, with reference to Figures 1 and 2, the conventional
Let's explain the video signal processing circuit in a VTR. FIG. 1 is a characteristic curve diagram of a modulator that performs FM modulation of a video signal to be recorded and reproduced on a VTR using, for example, a 10.7 MHz carrier wave. In general, the modulation characteristics of FM modulators have poor linearity compared to FM modulators, and curve 1
become that way. In Fig. 1, the modulated input signal voltage V _io is plotted on the horizontal axis, and the frequency f of the modulated signal is plotted on the vertical axis.
are being taken. Therefore, when the video signal 2 is supplied as a modulation input signal to the FM modulator, an FM modulated signal 3 with distorted modulation characteristics is taken out as its output. Next, this modulation effect will be explained with reference to FIG. Generally, video signals to be recorded and reproduced in a VTR are pre-emphasized before being FM modulated to emphasize their high frequency components. Therefore, in the pre-emphasized video signal, as shown in FIG. 2A, a certain degree of overshoot and undershoot occurs in the rising and falling portions of the retrace period in the video signal. As shown in Fig. 1, the linearity of the modulation characteristics of the FM modulator is poor, so the reproduced waveform after FM demodulation shown in Fig. 2B is quite different from the pre-emphasized waveform in Fig. 2A; The undershoot of the level becomes large, and the overshoot of the rising part becomes small. When this signal is de-emphasized, the waveform shown in FIG. Also, the waveform is considerably rounded at the rising edge. When such a video signal is recorded and reproduced on a VTR, it becomes as shown in FIG. 2D, and the undershoot portion 4 is further emphasized depending on the characteristics of the VTR. Therefore, there is a strong possibility that this waveform distortion may disturb the operation of the synchronization separation circuit in the VTR reproduction system.

Therefore, the inventor of the present invention performed waveform processing on a video signal obtained by receiving radio waves from television broadcasting using a simple circuit configuration, thereby reliably shaping the horizontal synchronizing signal part, and making it possible to reliably shape the horizontal synchronizing signal part, which can be used, for example, in a VTR. We have devised a video signal processing circuit that prevents the operation of the synchronization separation circuit in the playback system from being disturbed when applied.

Hereinafter, an example in which such a video signal processing circuit is applied to a VTR will be explained in detail with reference to FIGS. 3 to 6. FIG. 3 is a system diagram showing the main parts of the recording system of the tuner-equipped VTR. The received signal received by antenna 5 is supplied to tuner 6.
The tuner 6 includes a high frequency amplification circuit, a frequency converter, an intermediate frequency amplification circuit, a video detection circuit, and the like. The color video signal from the tuner 6 is supplied through the AGC circuit 7 to a separation circuit 8 having a wave unit configuration, where it is separated into a luminance signal and a carrier color signal. The luminance signal is then supplied to a pedestal clamp circuit 9 and a synchronous separation circuit 10.

11 indicates a video signal processing circuit, and a comparison circuit 30
Transistors 12, 13 and resistor 1 that constitute
It is composed of 4. And transistor 1
The base of transistor 2 is connected to the output terminal of pedestal clamp circuit 9, and the base of transistor 13 is connected to the output terminal of synchronous separation circuit 10. The collectors of the transistors 12 and 13 are connected to the power supply +B, and the emitters of the transistors 12 and 13 are commonly connected to the input terminal of the pre-emphasis circuit 15 and grounded via the current limiting resistor 14.

Therefore, the composite video signal (composite luminance signal) which is the output of the pedestal clamp circuit 9 is supplied to the base of the transistor 12, while the synchronous separation circuit 10
The horizontal synchronizing signal obtained from the horizontal synchronizing signal is supplied to the base of the transistor 13, and these signals are compared by a level comparison circuit 30.

Next, the operation of this level comparison circuit 30 will be explained with reference to FIG. Curve 2 in Figure 4A
0 indicates the composite video signal voltage which is the output of the pedestal clamp circuit 9, where the undershoot section 4 exists as described above. Also, curve 2
1 is the output voltage of the synchronization separation circuit 10, which is a horizontal synchronization signal shaped from the received video signal, and the synchronization signal portion 24 thereof is rectangular.
Therefore, the undershoot portion 4 of the curve 20 and the front porch portion 22 of the horizontal synchronization signal are set to be below the curve 21, and the horizontal synchronization signal portion 2
3 is set to be above the curve 21. Therefore, in this level comparison circuit 30, curve 2
If the potential of 0 is V ₂₀ and the potential of curve 21 is V ₂₁ , then
When V ₂₀ ≧ V ₂₁ , the transistor 13 is turned off, and the output of the level comparison circuit 11 is the curve 20.
When V ₂₀ <V ₂₁ , the transistor 12 is turned off and the level comparison circuit 30 outputs the pedestal or sync chip level which is the potential of the curve 21 . Therefore, as the output of the level comparison circuit 11, a video signal whose waveform is shaped as shown by a curve 25 as shown in FIG.
is supplied to As mentioned above, this signal is first emphasized in its high frequency components in the pre-emphasis circuit 15, and then supplied to the FM modulator 16, where it is
The FM modulated signal is combined with the low frequency converted carrier color signal, and is recorded on a magnetic tape via a recording amplifier 17 and a magnetic head 18.

As a result, when receiving and recording television broadcasts with the tuner 6 of a VTR, even if the received video signal falls below the pedestal level except for the horizontal synchronization signal part due to poor reception, the Since the received video signal is supplied to the video signal processing circuit and recorded on the magnetic tape after waveform shaping, there is no risk of disturbing the synchronization separation circuit in the VTR playback system.

By the way, as far as the above-described video signal processing circuit 11 is concerned with the operation of replacing the undershoot portion 4 of the video signal with the pedestal level, the base of the transistor 13 is connected to the resistor 26, as shown in FIG.
27 may be used to provide a fixed bias.

Next, assuming that the video signal processing circuit 11 is supplied with a video signal of a small amplitude, the operation in that case will be explained with reference to FIG.

When the potential of the input signal 29 is higher than the base bias potential of the transistor 13 indicated by the broken line 30,
A voltage corresponding to the signal 29 is taken out to the output terminal 31, and when the potential of the signal 29 is lower than the base bias potential of the transistor 13, a voltage corresponding to this base bias potential is taken out to the output terminal 31. Therefore, when a small amplitude video signal 29 is supplied to the input terminal 28, a voltage shown by a curve 32 can be extracted from the output terminal 31.

By the way, in sections a and c, the transistor 13
is off, and transistor 12 is off in section b. However, there is a period during which transistors 12 and 13 are both active, so when the amplitude of input signal 29 is small, transistor 13 is off. The transition from OFF to OFF of transistor 12 does not occur quickly. Therefore, output terminal 3
1, the voltage obtained in section a is as shown in curve 32.
When moving from section b to section b and from section b to section c, the waveform becomes sluggish.

In view of this point, the present invention proposes a signal processing circuit suitable for DC coupling and capable of high-speed switching.

Hereinafter, one embodiment of the present invention will be described in detail with reference to FIG. 7, and the explanation with respect to FIGS. do.

In this embodiment, as shown in FIG. 7, a current adjustment resistor 34 and a feedback capacitor 33 are newly added to the circuit shown in FIG. 5. That is, while connecting the feedback capacitor 33 between the collector of the transistor 12 and the base of the transistor 13,
The collector of transistor 12 is connected to power supply +B via resistor 34. By varying the resistance value of the resistor 34, the amount of feedback of the alternating current component can be varied.

Next, the operation of the circuit shown in FIG. 7 will be explained with reference to FIG. 8. First, in section a, the potential of the signal 35 supplied to the input terminal 28 gradually decreases, and the voltage of the transistor 13 shown by the dashed-dotted curve 36 gradually decreases.
When the base potential of transistor 12 becomes equal to
Since the base current of the transistor 12 decreases, the collector potential of the transistor 12 increases (section a). In this way, this voltage change is transmitted to the base of the transistor 13 via the feedback capacitor 33, so that
The base potential rises, transistor 13 suddenly turns on, and the potential of output terminal 31 suddenly comes to be dominated by transistor 13 (section b).
Then, when the potential of the signal 35 again exceeds the potential of the curve 36, the potential of the output terminal 31 is dominated by the potential of the curve 35. In this case as well, the voltage change is transmitted via the feedback capacitor 33, and the transition from section b to section c occurs abruptly in the same way as the transition from section a to section b.

Therefore, even if the signal 35 with a small amplitude is supplied to the video signal processing circuit 11, the output terminal 31 receives the curve 38.
Since the voltage indicated by is extracted, there is a sudden change when moving from section a to section b and when moving from section b to section c.

According to the present invention described above, it is possible to obtain a signal processing circuit suitable for DC coupling and capable of high-speed switching.

When the present invention is applied to a video signal processing circuit, an input composite video signal and a horizontal synchronization signal separated from the input composite video signal are supplied to a level comparison circuit, so that the signal from the level comparison circuit is Even if the output composite video signal is supplied to the pre-emphasis circuit, the horizontal synchronization signal part of the received video signal of the television broadcast is reliably shaped, and then this video signal is FM modulated and recorded on the magnetic tape, so the circuit configuration is This makes it possible to effectively prevent the operation of the synchronization separation circuit in the reproduction system from being disturbed.

[Brief explanation of the drawing]

Figure 1 is a modulation characteristic curve diagram of an FM modulator in a conventional VTR, Figure 2 is a diagram showing the waveform processing method of a video signal in a recording system of a conventional VTR, and Figure 3 is a diagram showing a video signal developed by the inventor. FIG. 4 is a waveform diagram for explaining the operation of FIG. 3, FIG. 5 is a circuit diagram for explaining the present invention, and FIG. FIG. 7 is a waveform diagram for explaining FIG. 5, FIG. 7 is a circuit diagram of an embodiment of the present invention, and FIG. 8 is a waveform diagram for explaining FIG. 11 is a video signal processing circuit, 12 is a transistor as a switching element, 13 is a transistor differentially connected to the transistor 12, 14 is a resistor, 30 is a level comparison circuit, 33 is a feedback capacitor, 34 is a resistor It is.

Claims (1)

[Claims] 1 During the connection between first and second transistors whose commonly connected emitter electrodes are grounded via a first resistor, and the first resistor and the commonly connected emitter electrode. An output terminal is derived from the point, and when the level of the input signal applied to the base electrode of the first transistor exceeds the voltage level applied to the base electrode of the second transistor, the first In the signal processing circuit configured to make the transistor conductive and obtain the input signal from the output terminal, a second resistor is inserted between the collector electrode of the first transistor and the power supply, and the A signal processing circuit characterized in that a connection midpoint between the collector electrode of the first transistor and the second resistor and the base electrode of the second transistor are connected via a feedback capacitor.