JPS6214993B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video signal processing circuit suitable for application to a VTR for receiving, recording and reproducing television broadcasts, and in particular, the present invention relates to a video signal processing circuit which is suitable for application to a VTR that receives television broadcasts, records and reproduces them, and in particular has a simplified circuit configuration to reduce horizontal synchronization signals in received video signals of television broadcasts. The purpose is to propose something that can reliably reshape parts.

First, with reference to Figures 1 and 2, the conventional
Let's explain the video signal processing circuit in a VTR. FIG. 1 is a characteristic curve diagram of a modulator that performs FM modulation of a video signal to be recorded and reproduced on a VTR using, for example, a 10.7 MHz carrier wave. In general, the modulation characteristics of FM modulators have poor linearity compared to FM demodulators, and curve 1
become that way. In Figure 1, the horizontal axis represents the modulated input signal voltage Vin, and the vertical axis represents the frequency f of the modulated signal.
are being taken. Therefore, when the video signal 2 is supplied as a modulation input signal to the FM modulator, an FM modulated signal 3 with distorted modulation characteristics is taken out as its output. Next, this modulation effect will be explained with reference to FIG. Generally, video signals to be recorded and reproduced in a VTR are pre-emphasized before being FM modulated to emphasize their high frequency components. Therefore, as shown in FIG. 2A, the video signal to which the frienphasis has been applied has a certain degree of overshoot and undershoot in the rising and falling portions of the retrace period in the video signal. As shown in Figure 1, the linearity of the modulation characteristics of the FM modulator is poor, so the reproduced waveform after FM demodulation shown in Figure 2B is quite different from the pre-emphasized waveform in Figure 2A, and the sync chip level is very low. The undershoot of the curve becomes larger, and the overshoot of the rising part becomes smaller. When this signal is de-emphasized, the waveform shown in FIG. Also, the waveform is considerably rounded at the rising edge. When such a video signal is recorded and reproduced on a VTR, it becomes as shown in FIG. 2D, and the undershoot portion 4 is further emphasized depending on the characteristics of the VTR. Therefore, there is a strong possibility that this waveform distortion may disturb the operation of the synchronization separation circuit in the VTR reproduction system.

In view of the above, the present invention uses a simple circuit configuration to process the waveform of a video signal obtained by receiving radio waves from television broadcasting, and reliably shapes the horizontal synchronizing signal part. When applied to
This is intended to prevent the operation of the synchronization separation circuit in the reproduction system from being disturbed.

Hereinafter, an example in which the video signal processing circuit of the present invention is applied to a VTR will be explained in detail with reference to FIGS. 3 and 4. FIG. 3 is a system diagram showing the main parts of the recording system of the tuner-equipped VTR. The received signal received by the antenna 5 is supplied to the tuner 6.
The tuner 6 includes a high frequency amplification circuit, a frequency converter, an intermediate frequency amplification circuit, a video detection circuit, and the like. The color video signal from the tuner 6 is supplied through the AGC circuit 7 to a separation circuit 8 having a wave unit configuration, where it is separated into a luminance signal and a carrier color signal. The luminance signal is then supplied to a pedestal clamp circuit 9 and a synchronous separation circuit 10.

11 This is a video signal processing circuit according to the present invention, and is composed of transistors 12 and 13 and a resistor 14, which constitute a comparison circuit 30. The base of the transistor 12 is connected to the pedestal clamp circuit 9.
The base of the transistor 13 is connected to the output terminal of the synchronous separation circuit 10. The collectors of each of transistors 12 and 13 are connected to the power supply +B.
The respective emitters are commonly connected to the input terminal of the pre-emphasis circuit 15 and grounded via the current limiting resistor 14.

Therefore, the composite video signal (composite luminance signal) which is the output of the pedestal clamp circuit 9 is supplied to the base of the transistor 12, while the synchronous separation circuit 10
The horizontal synchronizing signal obtained from the horizontal synchronizing signal is supplied to the base of the transistor 13, and these signals are compared by a level comparison circuit 30.

Next, the operation of this level comparison circuit 30 will be explained with reference to FIG. Curve 2 in Figure 4A
0 indicates the composite video signal voltage which is the output of the pedestal clamp circuit 9, where the undershoot section 4 exists as described above. Also, curve 2
1 is the output voltage of the sync separation circuit 10, which is a horizontal sync signal shaped from the received video signal, and the sync signal portion 24 is rectangular. Therefore, the undershoot portion 4 of the curve 20 and the front porch portion 22 of the horizontal synchronizing signal are set to be below the curve 21, and the horizontal synchronizing signal portion 23 is set to be above the curve 21. Therefore, in this level comparison circuit 30, if the potential of the curve 20 is V ₂₀ and the potential of the curve 21 is V ₂₁ , then V ₂₀ ≧
When V ₂₁ , the transistor 13 is turned off, and the potential of the curve 20 is taken out as the output of the level comparison circuit 11 . When V ₂₀ <V ₂₁ , the transistor 13 is turned off.
2 is turned off, and the pedestal portion or sync chip level, which is the potential of the curve 21, appears as the output of the level comparison circuit 30. Therefore, as the output of the level comparison circuit 11, a video signal whose waveform has been shaped as shown by a curve 25 as shown in FIG. 4B is taken out, and this signal is supplied to the pre-emphasis circuit 15. As described above, this signal is first emphasized in its high frequency components in the pre-emphasis circuit 15 and then supplied to the FM modulator 16, where the FM modulated signal is combined with the low frequency converted carrier color signal. The data is recorded on a magnetic tape via a recording amplifier 17 and a magnetic head 18.

As a result, when receiving and recording television broadcasts with the tuner 6 of a VTR, even if the received video signal falls below the pedestal level except for the horizontal synchronization signal part due to poor reception, the Since the received video signal is supplied to the video signal processing circuit and recorded on the magnetic tape after waveform shaping, there is no risk of disturbing the synchronization separation circuit in the VTR playback system.

Thus, according to the video signal processing circuit of the present invention,
By supplying the input composite video signal and the horizontal synchronization signal separated from the input composite video signal to the level comparison circuit, even if the output composite video signal from the level comparison circuit is supplied to the pre-emphasis circuit, television broadcasting is not possible. After reliably shaping the horizontal synchronization signal part of the received video signal, this video signal is FM modulated and recorded on the magnetic tape.
By simplifying the circuit configuration, it is possible to effectively prevent the operation of the synchronization separation circuit in the reproduction system from being disturbed.

[Brief explanation of the drawing]

Figure 1 is a modulation characteristic curve diagram of an FM modulator in a conventional VTR, Figure 2 is a diagram showing a video signal waveform processing method in a recording system of a conventional VTR, and Figure 3 is an application of the video signal processing circuit of the present invention. Comes with a chiyuna
FIG. 4 is a system diagram of the main parts of the recording system of the VTR, and is a waveform diagram for explaining the operation of FIG. 11 is a video signal processing circuit, and 30 is a level comparison circuit.

Claims (1)

[Claims] 1 It has a pair of transistors whose emitter electrodes are connected in common, and a clamped input video signal is applied to one base electrode of the pair of transistors, and a clamped input video signal is applied to the other base electrode, and the input video signal is separated from and shaped from the above input video signal. The video signal processing circuit is characterized in that the output video signal is obtained from the emitter electrode with a component extending lower than the potential applied to the other base electrode removed.