JPS6214108B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a junction field effect semiconductor device, particularly a vertical SIT or FET, and an integrated circuit thereof, and a method of manufacturing the same.

Taking inverted SIT as an example, SITL with a lateral bipolar transistor (BJT) as a load exhibits ultra-low power consumption and delay time product of 1 to 2 fJ/gate on the low power side, and sub-1 second on the high speed side. It exhibits high speed and has performance that surpasses I ² L.

This performance is achieved by a relatively easy process of 2 to 5 μm rule, but it goes without saying that higher performance can be achieved by further miniaturization, but there are some problems with miniaturization. One of these is the reduction of the channel width (gate spacing) due to the reduction of the gate area, and the other is the formation of a fine drain region with high positional accuracy within the reduced gate spacing. One way to reduce the gate area is to narrow the selective diffusion apertures used to form the gate region, but this has technical limitations, and the other method is to reduce the channel cross-sectional area. , resulting in reduced gate spacing. If the opening for drain region formation is too large within the reduced channel cross-sectional area,
If there is a misalignment, the gate high impurity density region and the drain high impurity density region overlap, resulting in an extremely large gate-drain junction capacitance, making it impossible to improve performance despite miniaturization. Therefore, the hole for the drain region is 1μ.
Position accuracy of less than m is required, and even the accuracy of ±0.5 μm obtained by normal ordination alignment, for example, becomes difficult. A similar problem occurs between the source and gate in the upright type SIT, and the FET
is also the same. In SITL, reduced gate spacing is required to obtain a normally-off type, but even in a normally-on type, it is possible to improve gate voltage control efficiency (η) and increase gm. It is still necessary.

The present invention has been made in view of these circumstances, and provides a junction field effect semiconductor device having the same performance as a miniaturized device using an easy manufacturing method. One of the objectives is to obtain a junction field effect semiconductor device with sufficiently narrow gate spacing without appreciably increasing the capacitance.
Another object is to provide a structure and manufacturing method that allows direct contact to a narrow gate portion surrounding the drain or source in order to minimize gate contact openings that increase gate area. Conventionally, in SIT, the gate region was first formed and then the drain or source (main electrode) region was formed, but in the present invention, polycrystal is used for the main electrode region, and an insulating film is formed on the top and side surfaces of the polycrystal. It is used as a mask for impurity diffusion in gate formation, and allows contact with wiring in the gate region by covering the polycrystal, and insulating it with the insulating film.

The present invention will be explained in detail below using the drawings.

FIG. 1 shows the structure of a field effect semiconductor device according to the present invention, using a vertical SIT or FET as an example.

FIG. 1a is a plan view of the semiconductor device of the present invention, and the insulating film is omitted for simplicity. Figure 1b and 1st
Figure c is the A-A' line of the plan view of Figure 1 a, respectively.
A sectional view taken along line B-B' is shown. For example, inverted
To describe it as SIT, the n ⁺ source region 12, which is one of the main electrodes, is connected to the substrate or buried layer, and the other main electrodes, which are the drain n ⁺ polycrystalline layer 1 and the n ⁺ drain region 11 provided on the surface. It consists of n ^- regions 13 which are sandwiched to form channel regions, and n ⁺ drain region 11 is surrounded by p ⁺ gate regions 14 and 114 provided on the surface.

The gate electrode 4 is in contact with the p ⁺ gate region 14 in a U-shape, and the n ⁺ polycrystalline layer 1 has a second insulating film such as SiO ₂ or Si ₃ N ₄ on the top surface and a third insulating film on the side surfaces. Insulated. Further, the n ⁺ polycrystalline layer 1 is insulated from the first p ⁺ gate region 114 by the first insulating film 7 . According to this structure, the gate spacing w
is approximately the width of the drain n ⁺ the width of the polycrystalline layer 1 and the third side of the side
It depends on the insulating film, and the main factor in miniaturization is how thinly the n ⁺ polycrystalline layer 1 can be cut.
Even with the current technology, it is easy to achieve a minimum thickness of 1 to 2 μm. Further, in the contact of the p ⁺ gate region 14, since the portion 14 that effectively functions as a gate directly contacts the gate electrode 4, it is possible to eliminate a wasteful portion of the p ⁺ region for a contact hole.

Furthermore, in terms of capacity, it goes without saying that it is preferable that the first, second, and third insulating films be thick.

The inverted n-channel SIT has been described above as an example, but it can easily be applied to upright type, p-channel, and FET.

The advantages of the structure of the present invention are further clarified by the manufacturing method described below. Figure 2 a~
Fig. 1a shows the steps of an example of the manufacturing method according to the present invention for realizing the SIT structure shown in Fig. 1.
A cross-sectional view taken along line A-A' of (n ⁺ source region 11
) is shown. In FIG. 2a, n ^- is grown on the n ⁺ source region 11 by epitaxial growth.
After depositing the region 13 and covering it with the oxide film 7, the
A cross section of a 1p ⁺ gate region 114 formed by selective diffusion and oxidation is shown. In preparation for post-processing, it is desirable that the first p ⁺ gate region 114 be shallow and that the oxide film 7, which is the first insulating film, be thick.
method, plasma deposition, etc. are also effective.

In FIG. 2b, a hole is opened in the future SIT part of the oxide film 7, and the Si polycrystalline layer 1, 101 and the second insulating film 1 are opened.
7,117 (for example, thermal oxidation with oxide film or nitride film,
CVD method, etc.) is deposited using well-known methods, and then
A cross section is shown in which the second insulating film 17 and the Si polycrystalline layer 1 in a portion that should become the U-shaped 2p ⁺ gate region 14 are removed. The Si polycrystalline layer 1, 101 is an n ⁺ -doped polycrystal or a low impurity density polycrystal, and the second insulating film 17,
An n-type impurity was diffused in advance before the 117 deposition. It is desirable that the impurity added in preparation for the subsequent process has a small diffusion coefficient, and As, Sb, or B is used in the case of p-type. In addition, an n ⁺ polycrystalline layer 101 other than the one serving as the drain n ⁺ polycrystalline layer 1
The ^gate region 14 may be completely removed or left as shown in FIG. Depends on the good. When the line width is advantageous, as shown in Figure 2b,
When positional accuracy is more advantageous than line width, use n ⁺ polycrystalline layer 1
01, it is better to remove the insulating film 117. In this step, the n ⁺ drain region 11 and the second p ⁺ gate region 1
The position, size, or width of 4 is almost determined. FIG. 2c shows an oxide film 27 formed on the side surfaces of the polycrystalline layers 1 and 101 and the surface of the n ^- region 13 by thermal oxidation.
and 37 are shown.

For thermal oxidation, steam oxidation or high-pressure oxidation is preferable in order to reduce expansion due to diffusion in other regions, and the oxide film 27 on the side surface of the polycrystalline layer 1, 101 is better than that on the single crystal n ^- region 13. It's thicker.

Since the polycrystalline layers 1 and 101 are doped with n-type impurities at a high density, this tendency is remarkable, for example.
It can grow 1.3 to 2 times as thick.

The surface side of the polycrystalline layer 1, 101 is covered with a second insulating film 17,
Since it is coated with 117, oxidation hardly progresses. In Figure 2d, the directional plasma etching,
By ion etching, etc., the n ^- region 13 is removed without removing much of the oxide film 27 on the side surface of the polycrystalline layer 1,101.
The upper oxide film 37 is removed. At this time, the second insulating films 17 and 117 are also etched, so it is necessary to make them at least sufficiently thicker than the oxide film 37, or to use a material that is less likely to be etched. A 2p ⁺ gate region 14 is formed by selective diffusion or the like using the opening in this step, and the cross section in which the drain electrode 1' is also wired at the same time as the gate electrode 4 is shown in FIG. 2e. It is preferable that the diffusion formation of the 2nd p ⁺ gate region be carried out in a non-oxidizing atmosphere or dry oxygen, and that no oxide film be formed or that it be formed only thinly. In this sense, high current ion implantation is preferable to boron glass deposition.

Through the above steps, an inverted SIT is completed, but as mentioned above, the gate spacing w
The gate area and gate area are determined by the masking process and selective etching process shown in FIG. 2b, and the oxidation process shown in FIG. 2c, and the dimensions and positions are determined in a self-aligned manner. Therefore, it is possible to perform SIT with the smallest possible size in the mask process, and even in current photolithography, for example, 2 μm x 2 μm, 1 μm x 2 μm.
n ⁺ drain region and channel cross-sections of m can be realized. Furthermore, the width of the n ^- region between the p ⁺ gate region and the n ⁺ drain region is determined by the thickness of the third insulating film (the oxide film 27 in the case of FIG. 2), and in this case,
It is advantageous because it can take advantage of the fast oxidation of n ⁺ polycrystals,
For example, a width of 0.3 to 0.5 μm can also be determined by self-alignment. The reduction in capacitance is achieved by appropriately increasing the thickness of the first, second, and third insulating films,
The area of the 2p ⁺ gate region 14 can be advantageously made smaller by about 2×1/2 third insulating film thickness than the opening width shown in FIG. 2b.

FIG. 3 shows a cross-sectional view for explaining another embodiment of the manufacturing method of the present invention. In Figure 3a,
n ^- region 13 on n ⁺ source region 12 (not shown)
Selective oxide films 7, 1 are formed using Si ₃ N ₄ films 8, 48 on top.
A cross section of 07 is shown. This selective oxidation may be performed after the n ^- region 13 is dug once, and in this case, it is effective in reducing the capacitance and carrier accumulation. Next, the Si ₃ N ₄ film 48 is removed through a mask process, a first p ⁺ gate region 114 is formed by diffusion (FIG. 3b), and the Si ₃ N ₄ film 8 is etched on the entire surface.
is removed, a hole is opened in the SIT portion, and a polycrystalline layer 1, an oxide film 17, and a Si ₃ N ₄ film 18 are deposited (FIG. 3c).

In this case, the polycrystalline layer 1 may have a low impurity density (p
It is preferable that the density is lower than that of the n ^- region 13 for n-type and n-type, but it may be relatively high (although it can be actively used depending on the case). In the latter case, the impurities are removed from the oxide film 17.
forms added to it, e.g. doped oxide or
A spincoat diffusion source is used, or multiple polycrystalline layers with low density and high density are also possible.

In the next step, the polycrystalline layer 1 and the second insulating film (multilayer of oxide film 17 and Si ₃ N ₄ film 18) are left on the area that is to become the n ⁺ drain region 11 and for interconnection, and the field oxide film 107 is removed. In between, the n ^- region 13 is exposed to prepare for the future formation of the 2p ⁺ gate region 14 (FIG. 3d). By selective oxidation, polycrystalline layer 1
Oxide films 27 and 3 are formed on the exposed side of the n ^- region 13.
7 (FIG. 3e), holes are opened by directional etching to form the 2p ⁺ gate region 14 (FIG. 3f), and each electrode is attached (FIG. 3g).
The gate electrode 4 is usually made of metal such as Al, Pt, Al--Si, etc., but p-type Si polycrystal can also be used as a diffusion source and wiring for the second p ⁺ gate region 14.

In the process example shown in FIG. 3, the Si ₃ N ₄ film 18 is disposed on the polycrystalline layer 1, and the oxide film 27 on the side surface can be made sufficiently thick, and the second insulating film may be multilayered. and the opposite arrangement, for example, a thick layer on the Si ₃ N ₄ film 18
CVDSiO ₂ membrane 17 was also used and was shown to be more effective in reducing capacitance.

As described above, according to the manufacturing method of the present invention, a miniaturized SIT with a size close to the minimum size that can be processed in a mask process can be realized with low capacitance in a self-aligned manner by using a polycrystalline drain. .

The present invention is applicable not only to the above-mentioned inverted type but also to the upright type, not only to the n-channel but also to the p-channel, and not only to the SIT.
FETs and other field-effect semiconductor devices with similar channel structures (e.g. SIT thyristors and memories), as well as ICs containing them (e.g. ^I2L SITLs loaded with lateral bipolar transistors, other SITLs, analog SITs) IC, also FET-IC)
It can be applied to Furthermore, the manufacturing method according to the present invention can be applied to an upright type or an ^inverted type bipolar transistor, and as described above, in FIG.
If an n-type impurity is added to the oxide film 17 thereon, manufacturing can be easily performed, and the process of the present invention may be applied after forming the base region in the conventional manner.

The present invention provides a high-performance miniaturized field effect semiconductor device that can be realized through a simple process and a method for manufacturing the same, which is effective for increasing the speed and reducing power consumption of ICs, and is useful for ICs for watches, microprocessors, etc. The range of applications is extremely wide, including memory, A/D, D/A converters, and other peripheral ICs.

[Brief explanation of the drawing]

Figure 1a is a plan view illustrating the structure of an inverted SIT according to the present invention, and Figures 1b and 1c are cross-sectional views taken along lines A-A' and B-B' in Figure 1a, respectively. It is. FIGS. 2a to 2e are cross-sectional views of SIT manufacturing process examples according to the present invention, and FIGS. 3 a to 3g are process cross-sectional views of other manufacturing method examples of the present invention. 1...Drain polycrystalline layer, 4...Gate electrode,
7...First insulating film, 8, 18...Si ₃ N ₄ film, 11
...n ⁺ drain region, 12...n ⁺ source region,
13...n ^- region, 14...2p ⁺ gate region, 1
14...1p ⁺ gate region, 17...2nd insulating film (oxide film), 27...3rd insulating film (oxide film), 3
7, 107, 117...Oxide film, 101...Polycrystalline layer.

Claims (1)

[Claims] 1. A first gate region of opposite conductivity type with high impurity density is selectively formed on the main surface of a low impurity density region of one conductivity type, and the main surface of the low impurity density region is covered with a first insulating film. forming a polycrystalline layer and a polycrystalline layer over the entire surface of the opening and the first insulating film; a step of depositing a second insulating film and removing at least a predetermined portion of the second insulating film and the polycrystalline layer in which a second gate region will be formed in the future in the opening portion to expose the low impurity density region; a step of forming a thermal oxide film on the side surface of the removed portion of the polycrystalline layer and an exposed portion of the low impurity density region; and an oxide film formed in the step that is thinner than the other portions on the exposed portion of the low impurity density region. selectively forming a second gate region of opposite conductivity type with high impurity density so as to overlap a part of the first gate region; and a step of forming a gate electrode on at least a part of the second gate region; A method for manufacturing a junction field effect semiconductor device comprising the step of forming one main electrode through an opening in a second insulating film on a polycrystalline layer. 2. The method of manufacturing a junction field effect semiconductor device according to claim 1, wherein at least one layer of the second insulating film is a Si ₃ N ₄ film. 3. The polycrystalline layer has a low impurity density when deposited, and one conductivity type impurity is added to the surface of the polycrystalline layer at a high density after deposition and before coating with the second insulating film. A method for manufacturing a field effect semiconductor device according to claim 1 or 2.