JPS6215959B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a sample-and-hold circuit that is often used in the input section of an A/D converter, and which holds and outputs a value corresponding to an input signal applied during a sample period during a hold period. This is related to the improvement of.

1 to 3 are electrical circuit diagrams showing conventional sample-and-hold circuits.

Figure 1 shows an inverting sample-and-hold circuit, Figure 2 shows a non-inverting sample-and-hold circuit, and Figure 3 shows an inverting sample-and-hold circuit.
The figures each show sample and hold circuits in the system of FIG. 2 with an input buffer added thereto.
A common problem with these is that the sample and hold circuit output is connected to the amplifier (A11, A21, A31, A
32, etc.) causes an error. For example, in Fig. 3, if the input signal voltage of amplifier A31 is Vin and the input offset voltage is Vos ₃₁ , the sample-and-hold circuit output is expressed as Vout = Vin - Vos ₃₁ , and the error for the offset is the difference between the sampling time and the hold voltage. expressed in the output of time.

As mentioned above, in order to obtain sufficient accuracy using a sample-and-hold circuit configured to cause errors due to amplifier offset, an expensive amplifier with a small offset voltage and its temperature coefficient is required. It was hot. Furthermore, it is difficult to integrate such a high-performance amplifier and a switch circuit into one unit, and as a result, there has never been a simple sample-and-hold IC with good performance.

The present invention aims to solve the above-mentioned problems, and aims to realize a sample-and-hold circuit in which the offset of the amplifier does not appear as an output error even when a low-performance amplifier is used.

In order to achieve the above object, the first gist of the present invention is to provide an input terminal to which an input signal is applied, a first switch having one end connected to this input terminal, and a first switch connected to the other end of the first switch. a capacitor having one end connected to the one end thereof, an inverting amplifier having the other end connected to the input terminal thereof, a second switch connecting the output terminal of the inverting amplifier to the input terminal; a third switch connected to the output terminal and the one end of the capacitor, the first and second switches are closed during the sample period, the third switch is opened, and the third switch is opened during the hold period. The sample and hold circuit has first and second switches open and the third switch closed.

The second gist of the present invention is an input terminal to which an input signal is applied, a first switch having one end connected to the input terminal, and a first switch having the other end connected to the input terminal. a first buffer, a capacitor whose one end is connected to the output terminal of the first buffer, an inverting amplifier whose other end is connected to its input terminal, and an output terminal of the inverting amplifier and the input terminal. a second switch connected to the inverting amplifier; a first sample-and-hold circuit connected to the output terminal of the inverting amplifier; and an output terminal of the first sample-and-hold circuit and the input terminal of the first buffer. and a third switch to be connected, during the sample period, the first and second switches are closed, the third switch is opened, and the first sample-and-hold circuit is placed in a hold mode. During the section, the first and second switches are open, the third switch is closed, and the first sample and hold circuit is in the sample mode.

The present invention will be explained below based on the drawings.

FIG. 4 is an electrical circuit diagram showing one embodiment of the present invention. 41 is an input terminal to which an input signal voltage is applied, S41 is a first switch whose one end is connected to this input terminal 41, C41 is a charging capacitor whose one end is connected to the other end of this first switch S41, and A41 is a capacitor for charging. The other end of this capacitor C41 is connected to its inverting input terminal, and S42 is an operational amplifier used as an inverting amplifier.
A second switch S43 connected to the output terminal 43 of the operational amplifier A41 and the inverting input terminal of the operational amplifier A41
A third switch 42 is connected to the output terminal 43 of the capacitor C41 and the one end of the capacitor C41; This is a command terminal.

During sampling, that is, switches S41 and S42 are closed,
When the input signal Vin is applied to the input terminal 41 with the switch S43 open, when the offset voltage of the amplifier A41 is Vos ₄₁ , the capacitor C41 is charged to a charging voltage of Vc=Vin-Vos ₄₁ (1). At this time, the amplifier A41 functions as a non-inverting amplifier with a gain of 1 whose non-inverting input terminal is connected to the common, and the output Vout from the terminal 43 becomes Vout=Vos ₄₁ (2).

On the other hand, during hold, switches S41 and S42 are open, and switch S43 is closed, and during sampling, the voltage that is the sum of the charging voltage vc charged in capacitor C41 and the offset Vos ₄₁ of amplifier A41 is
It is output from the output terminal 43 as Vout. In other words, the output voltage at this time is Vout = Vc + Vos ₄₁ (3). Substituting equation (1) into equation (3) yields Vout = Vin - Vos ₄₁ + Vos ₄₁ = Vin (4), and the offset is canceled and does not appear in the output.

FIGS. 5 1 to 4 show time charts of various parts of the sample-and-hold circuit shown in FIG. 4, and show the pattern when the input signal Vin changes from Vin1 to Vin2.

The sample-and-hold circuit configured as described above has the advantage that an output can be obtained in which the influence of the offset of the amplifier is canceled during holding. Furthermore, although an inverting amplifier is used, a non-inverting output can be obtained. Furthermore, since it is easy to use a high-speed inverting amplifier, a high-speed sample-and-hold circuit can be realized. Furthermore, since it is not affected by offset even if a low-performance amplifier is used, it is easy to integrate it into an IC or the like.

FIG. 6 shows a second embodiment of the invention, in which the amplifier A41 in the first embodiment (FIG. 4) is replaced by
This uses the inverter A61, which is a CMOS logic element. Components that are the same as those in FIG. 4 are designated by one reference numeral, and their explanation will be omitted. In this case, inverter A61
The threshold voltage acts as an offset, but this is also canceled in the same way as described above, so it does not affect the output voltage Vout during hold. Its features are also similar to those of the first embodiment.

FIG. 7 is an electric circuit diagram showing a modification of the embodiment shown in FIG. 6. By dividing the output of inverter A61 by resistors R71 and R72 and feeding it back, a gain of G=R71+R72/R72 is obtained. (The S/H command signal circuit is omitted in the figure).

FIG. 8 is an electrical circuit diagram showing a third embodiment of the present invention, which is the circuit of FIG. 6 except that a buffer is provided on the input side and a first sample-and-hold circuit is provided on the output side. Components that are the same as those in FIG. 6 are designated by the same reference numerals and their explanation will be omitted.

A81 is a first buffer whose input is connected to the first switch S41 and whose output is connected to the capacitor C41, SH1 is a first sample-and-hold circuit whose input terminal is connected to the output terminal of the inverter 61, and S82 is a first buffer whose input terminal is connected to the capacitor C41. This is the third switch to which the output terminal of the first sample-and-hold circuit SH1 is connected. In the sample and hold circuit SH1, S81 is a switch whose one end is connected to the output terminal of the inverter A61, C81 is a holding capacitor whose one end is connected to the other end of the switch S81 and the other end is connected to a common, and A82. is a second buffer whose input terminal is connected to the other end of the switch S81, and its output is output as Vout and is also connected to the switch S82.

During sampling, switches S41 and S42 are closed, and switches S81 and S82 are opened. input signal
Vin is connected to capacitor C41 via buffer A81.
to charge. The sample-and-hold circuit SH1 enters the hold mode, and the capacitor C81 holds the charge voltage charged during the previous hold, so this is transferred to Vout via the buffer A82.
is output as In addition, the buffer A81 and A
82 may be something simple such as a source follower.

During hold, switches S41 and S42 open and switches S81 and S82 close, so Vout is output based on the voltage charged in capacitor C41 during the previous sample, and at the same time, the sample and hold circuit SH1 in sample mode Capacitor C81 is also charged.

Fig. 5 shows a time chart of the output of the sample and hold circuit in Fig. 8. Due to the function of the sample and hold circuit SH1, the output Vout
No ripples occur during the transition from the sample interval to the hold interval, and an output without offset error can always be obtained. Furthermore, the presence of the input buffer A81 prevents the settling time of the output Vout from changing due to the input signal source impedance. Other features are similar to the embodiment shown in FIG.

In the embodiment shown in FIG. 8, input buffer A81 or sample/hold circuit may be used as necessary.
Only one of SH1 may be used.

As described above, according to the present invention, it is possible to realize a sample-and-hold circuit with a simple configuration in which the offset of the amplifier does not appear as an output error even when a low-performance amplifier is used. In addition, since it is an inverted type, it has excellent advantages such as high-speed operation and easy integration.

[Brief explanation of the drawing]

1 to 3 are electrical circuit diagrams showing conventional sample-and-hold circuits, FIG. 4 is an electrical circuit diagram showing a first embodiment of the present invention, and FIGS. 5 1 to 4 are circuit diagrams of FIG. 4. A time chart to explain the operation of
5. FIG. 5 is a time chart for explaining the operation of the circuit in FIG. 8, FIG. 6 is an electric circuit diagram showing a second embodiment of the present invention, and FIG. 7 is a modification of the circuit in FIG. 6. FIG. 8 is an electrical circuit diagram illustrating a third embodiment of the present invention. 41...Input terminal, Vin...Input signal, S4
1, S42, S43, S82...Switch, C4
1...Capacitor, A41, A61...Inverting amplifier, SH1...Sample/hold circuit, A81
...Batsuhua.

Claims (1)

[Claims] 1. An input terminal to which an input signal is applied, a first switch to which one end is connected to the input terminal, a capacitor to which the other end of the first switch is connected, and the capacitor. an inverting amplifier whose other end is connected to its input terminal; a second switch which is connected to the output terminal of the inverting amplifier and the input terminal; and a second switch which is connected to the output terminal of the inverting amplifier and the one end of the capacitor. and a third switch, the first and second switches are closed and the third switch is opened during the sample period, the first and second switches are opened during the hold period, and the third switch is opened during the hold period. A sample/hold circuit in which the switch is closed. 2. The sample-and-hold circuit according to claim 1, which uses an inverter as an inverting amplifier. 3. An input terminal to which an input signal is applied, a first switch having one end connected to this input terminal, a first buffer having the other end connected to the input terminal, and this first buffer. a capacitor having one end connected to the output terminal of the inverting amplifier, and an inverting amplifier having the other end connected to the input terminal of the capacitor;
a second switch connected to the output terminal of the inverting amplifier and the input terminal; a first sample-and-hold circuit connected to the output terminal of the inverting amplifier; and an output terminal of the first sample-and-hold circuit. and a third switch connected to the input terminal of the first buffer, and during the sample period, the first and second switches are closed, the third switch is open, and the third switch is connected to the input terminal of the first buffer. The first sample and hold circuit is placed in a hold mode, the first and second switches are opened during the hold period, the third switch is closed, and the first sample and hold circuit is placed in a sample mode. sample and hold circuit. 4. The sample-and-hold circuit according to claim 3, which uses an inverter as an inverting amplifier.