JPS6216013B2 - - Google Patents
Info
- Publication number
- JPS6216013B2 JPS6216013B2 JP60093604A JP9360485A JPS6216013B2 JP S6216013 B2 JPS6216013 B2 JP S6216013B2 JP 60093604 A JP60093604 A JP 60093604A JP 9360485 A JP9360485 A JP 9360485A JP S6216013 B2 JPS6216013 B2 JP S6216013B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- silicon
- substrate
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置における電極上の層間絶縁
膜とチヤネル領域上のゲート絶縁膜との形成法に
関し、さらに詳しくはそれぞれ膜厚の異なる絶縁
膜を同時に形成しようとするものである。特に本
発明の適用により半導体装置の高耐圧化ならびに
配線間容量の低減化を実現するものである。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method for forming an interlayer insulating film on an electrode and a gate insulating film on a channel region in a semiconductor device, and more specifically, the present invention relates to a method for forming an interlayer insulating film on an electrode and a gate insulating film on a channel region in a semiconductor device. It is intended to be formed at the same time. In particular, by applying the present invention, it is possible to increase the breakdown voltage of a semiconductor device and reduce the capacitance between wirings.
第1図に本発明の実施例を示す。説明の便宜
上、基板にシリコンを用いる。第1図aに示すよ
うに第1導電型のシリコン基板1の表面全体に熱
酸化SiO2膜で代表されるフイールド絶縁膜2を
形成する。しかる後にトランジスタを形成する部
分の素子領域3の部分のフイールド絶縁膜をよく
知られた写真蝕刻法のエツチングによつて除去す
る。この時最初のフオトマスクを必要とする。さ
らに素子領域を覆うSiO2で代表されるゲート絶
縁膜2−1を形成し、さらに全体を覆う多結晶シ
リコンで代表されるゲート電極4を被着し、既知
の写真蝕刻法によつて後にゲートとする電極部4
を残して他を除去する。ここで第2のフオトマス
クを用いる。このときゲート部だけではなくフイ
ールド酸化膜2上にも残存せしめてこれを他の電
極として用いることもできる。
FIG. 1 shows an embodiment of the present invention. For convenience of explanation, silicon is used as the substrate. As shown in FIG. 1a, a field insulating film 2 typified by a thermally oxidized SiO 2 film is formed over the entire surface of a silicon substrate 1 of a first conductivity type. Thereafter, the field insulating film in the element region 3 where the transistor is to be formed is removed by etching using a well-known photolithography method. At this time, you will need your first photomask. Furthermore, a gate insulating film 2-1, typically made of SiO 2 , is formed to cover the device region, and a gate electrode 4, typically made of polycrystalline silicon, is deposited to cover the entire device region, and the gate electrode 4 is then deposited using known photolithography. Electrode section 4
Leave the remaining and remove the others. Here, a second photomask is used. At this time, it is possible to leave it not only on the gate portion but also on the field oxide film 2 and use it as another electrode.
その後ゲート4をマスクとしてゲート絶縁膜2
−1をエツチングによつて除去し、しかる後に水
蒸気を含んだO2中で酸化するとbに示すように
シリコン基板1上にはSiO2の絶縁膜2−2が、
多結晶シリコン4上にはSiO2のゲート保護膜6
が形成される。あらかじめゲート電極には高濃度
のリンを添加しておくと、ゲート保護膜6が絶縁
膜2−2より厚く形成される。不純物濃度として
は1018/cm3以上、より好ましくは1020/cm3以上で
ある。たとえば、700℃で7時間上記の酸化を行
なうと、ゲート多結晶Si上には2800ÅのSiO2膜7
が、基板上には500ÅのSiO2膜を成長することが
できる。 After that, using the gate 4 as a mask, the gate insulating film 2 is
-1 is removed by etching and then oxidized in O2 containing water vapor, an insulating film 2-2 of SiO2 is formed on the silicon substrate 1 as shown in b.
A gate protective film 6 of SiO 2 is formed on the polycrystalline silicon 4.
is formed. If a high concentration of phosphorus is added to the gate electrode in advance, the gate protective film 6 is formed thicker than the insulating film 2-2. The impurity concentration is 10 18 /cm 3 or more, more preferably 10 20 /cm 3 or more. For example, if the above oxidation is carried out at 700°C for 7 hours, a 2800 Å SiO 2 film 7 will be formed on the gate polycrystalline Si.
However, a 500 Å SiO 2 film can be grown on the substrate.
しかる後に、Si−SiO2界面を良好なものとする
ため乾燥酸素中1000℃で10分熱処理し、基板上の
SiO2膜厚を600Åとする。 After that, heat treatment was performed at 1000℃ for 10 minutes in dry oxygen to improve the Si-SiO 2 interface.
The SiO 2 film thickness is 600 Å.
本方法を適用することにより電極上の層とチヤ
ネル領域上のゲート絶縁膜の形成が同時に行なえ
るため第1層と第2層の多結晶Si間の容量が小さ
くかつ耐圧の高い構造を得ることができる。たと
えば実験により耐圧40V以上が得られている。 By applying this method, the layer on the electrode and the gate insulating film on the channel region can be formed simultaneously, resulting in a structure with low capacitance between the first and second polycrystalline Si layers and a high breakdown voltage. I can do it. For example, experiments have shown that a breakdown voltage of 40V or more has been achieved.
しかる後にcに示すように、第2の多結晶Si8
を被着し、写真蝕刻法によつて一部を残し他は除
去する。このとき第3のフオトマスクを必要とす
る。このとき電極8に多結晶シリコンを用いる
と、多結晶シリコンに添加した不純物によつてあ
るいは多結晶シリコン上から不純物を添加するこ
とによつて第2導電型の領域9を形成することが
できる。また電極8を被着する前に既知の熱拡散
法やイオン打込み法によつてあらかじめ領域9を
形成しておくこともできる。本発明ではどちらで
も可能である。 Thereafter, as shown in c, the second polycrystalline Si8
Then, using photolithography, some parts are left and the others are removed. At this time, a third photomask is required. If polycrystalline silicon is used for the electrode 8 at this time, the second conductivity type region 9 can be formed by adding an impurity to the polycrystalline silicon or by adding an impurity from above the polycrystalline silicon. Further, before depositing the electrode 8, the region 9 can be formed in advance by a known thermal diffusion method or ion implantation method. In the present invention, either is possible.
さらにその後にdに示すように、コンタクト穴
11を形成して、最後に金属配線10を形成す
る。ここで第4、第5のフオトマスクを要する。 Further thereafter, as shown in d, contact holes 11 are formed, and finally metal wiring 10 is formed. Here, fourth and fifth photomasks are required.
なお、第1図で示されている構造は、多結晶Si
4の直下のSi表面の反転層を蓄積電極、多結晶Si
8の直下のSi表面を転送電極、9をデータ線10
をワード線とするメモリ・セルを形成している
が、本発明の骨子は、他の素子、たとえば、ソー
スおよびドレインの2つの拡散層をもち、その間
に第1図4,8で示された2種類以上の多結晶Si
によるゲート電極が介在することを特徴とする
MOSトランジスタ、あるいは電荷転送装置
(CTD)などに用いることができる。 The structure shown in Figure 1 is made of polycrystalline Si.
The inversion layer on the Si surface directly under 4 is used as a storage electrode, and polycrystalline Si
The Si surface directly under 8 is the transfer electrode, and 9 is the data line 10.
However, the gist of the present invention is to have two diffusion layers for other elements, such as a source and a drain, between which the memory cells shown in FIGS. 4 and 8 are formed. Two or more types of polycrystalline Si
characterized by the presence of a gate electrode
It can be used for MOS transistors, charge transfer devices (CTD), etc.
第2図は横軸に酸化温度をとり、たて軸に高濃
度にリンがドープされたシリコンの表面に形成さ
れる湿式酸化膜をとつた図である。パラメータと
して基板シリコン表面10Ω・cm、P型(100面)
上に形成する酸化膜をとり、それぞれ500Å、
1000Åおよび1500Åについて示してある。第2図
から明らかなように、不純物濃度によつて酸化速
度が異なる選択酸化は酸化温度が900℃以下の場
合について著しい。またこのような特性が得られ
る不純物濃度として1×1020cm-3以上が望まし
い。 FIG. 2 is a diagram in which the horizontal axis represents the oxidation temperature, and the vertical axis represents the wet oxide film formed on the surface of silicon doped with a high concentration of phosphorus. Parameters are substrate silicon surface 10Ω・cm, P type (100 sides)
Remove the oxide film to be formed on top, each with a thickness of 500Å,
Shown for 1000 Å and 1500 Å. As is clear from FIG. 2, selective oxidation, in which the oxidation rate varies depending on the impurity concentration, is significant when the oxidation temperature is 900° C. or lower. Further, it is desirable that the impurity concentration to obtain such characteristics is 1×10 20 cm −3 or more.
このように膜厚が異なりそれぞれ別の役割をも
つ絶縁膜を同時に形成することは、従来おこなわ
れてこなかつた。そのためにこのような選択酸化
法を用いることは半導体装置を実現するプロセス
工程においてその工程数が減少し従来の製造方法
にくらべて経済的効果は極めて大きい。また従来
ゲート絶縁膜として湿式酸化膜を用いることもそ
の酸化膜の性質が半導体装置の特性上好ましくな
いことからおこなわれてこなかつた。しかしなが
ら今回湿式熱酸化膜もその後の熱処理工程を経る
ことにより、従来の乾式熱酸化膜とほとんどわか
らない性質のゲート絶縁膜を実現し得ることが分
つた。
In the past, it has not been possible to simultaneously form insulating films having different thicknesses and each having a different role. Therefore, the use of such a selective oxidation method reduces the number of steps in the process steps for realizing a semiconductor device, and has an extremely large economic effect compared to conventional manufacturing methods. Further, conventionally, the use of a wet oxide film as a gate insulating film has not been carried out because the properties of the oxide film are unfavorable in view of the characteristics of the semiconductor device. However, it has now been discovered that by subjecting the wet thermal oxide film to a subsequent heat treatment process, it is possible to create a gate insulating film with properties that are almost indistinguishable from those of conventional dry thermal oxide films.
第1図は本発明の実施例を示す図である。第2
図は本発明に用いた選択酸化法の条件を示す図で
ある。
FIG. 1 is a diagram showing an embodiment of the present invention. Second
The figure shows the conditions of the selective oxidation method used in the present invention.
Claims (1)
面上に第1の絶縁膜を形成し、該第1の絶縁膜上
に前記シリコン半導体基板の不純物濃度より高
く、1018/cm3以上の不純物濃度をもつ第1のシリ
コン膜を、所定の一部をおおうように被着し、前
記第1の絶縁膜の一部をエツチングして前記基板
主表面の一部を露出し、該露出部と前記第1のシ
リコン膜上に、該第1のシリコン膜上での膜厚が
該露出部での膜厚よりも厚くなるように第2の絶
縁膜を形成し、さらに該第2の絶縁膜上に電極膜
を被着し、前記基板上に二層の電極を有する構造
を得る半導体装置の製造方法であつて、上記第2
の絶縁膜は、湿式酸化によつて第1の酸化膜を形
成する工程と乾式酸化によつて第2の酸化膜を形
成する工程とによつて形成されることを特徴とす
る半導体装置の製造方法。1. A first insulating film is formed on the main surface of a silicon semiconductor substrate having one main surface, and an impurity with an impurity concentration higher than that of the silicon semiconductor substrate and 10 18 /cm 3 or more is formed on the first insulating film. A first silicon film having a high concentration is deposited to cover a predetermined part, a part of the first insulating film is etched to expose a part of the main surface of the substrate, and a part of the main surface of the substrate is exposed. A second insulating film is formed on the first silicon film so that the film thickness on the first silicon film is thicker than the film thickness in the exposed portion, and further the second insulating film is A method for manufacturing a semiconductor device to obtain a structure having two layers of electrodes on the substrate by depositing an electrode film thereon, the method comprising:
Manufacturing of a semiconductor device, wherein the insulating film is formed by a step of forming a first oxide film by wet oxidation and a step of forming a second oxide film by dry oxidation. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9360485A JPS6110255A (en) | 1985-05-02 | 1985-05-02 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9360485A JPS6110255A (en) | 1985-05-02 | 1985-05-02 | Manufacturing method of semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11471976A Division JPS5340291A (en) | 1976-09-27 | 1976-09-27 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6110255A JPS6110255A (en) | 1986-01-17 |
| JPS6216013B2 true JPS6216013B2 (en) | 1987-04-10 |
Family
ID=14086929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9360485A Granted JPS6110255A (en) | 1985-05-02 | 1985-05-02 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6110255A (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4932635A (en) * | 1972-07-21 | 1974-03-25 | ||
| JPS5019363A (en) * | 1973-06-21 | 1975-02-28 |
-
1985
- 1985-05-02 JP JP9360485A patent/JPS6110255A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6110255A (en) | 1986-01-17 |
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