JPS6217243B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a sequence program display device for a general-purpose sequencer for use in electric power, substation, water treatment, and general industries. The sequence device is shown in FIG. In the figure, 1 is a central processing unit (hereinafter abbreviated as CPU), 2 is a CPU memory, and 3 is a sequence program loader, which are connected to a bus 10 via a sequence program rotor interface 4. The program rotor 3 is a device that performs functions such as loading sequence programs, corrections such as additions and deletions, display, and searches. Logic part 5 surrounded by dotted line
is composed of a logical bus interface 51, and a logical operation section 52, a control information section 53, and a sequence program memory 54 connected to this interface 51 via a logical bus 11. 6 is
The RIO control unit is connected to the bus 10 and serves to manage the exchange of control signals with external equipment (not shown). The sequence program shown in Table 1 below is now loaded into such a sequence device using the sequence program loader 3.

[Table] When loading the sequence program shown in Table 1, it is converted into an object code and the object code is sent to the program loader 3, loader interface 4, bus 10, logic section bus interface 51, bus 11 to the sequence program memory 54 as shown in FIG. In FIG. 2, bits 0 to 11 indicate opera codes, and bits 12 to 15 indicate op codes. For example, numbers 0 to 6 are the No. 1 line, and numbers 7 to 15 are the No. 1 line.
2 lines, etc. are stored. When displaying the sequence program stored in this way on the program loader 3, “1”,
It was displayed as a code of “0”. For example, when displaying "*M1702A" shown at address 5 in FIG. 2, "1 000 011 111 000 010" was displayed. The operator looked at this code and translated it to see if it was "*M1702A". The work of an operator to translate what is represented by the codes of "1" and "0" in this way is time consuming and requires a great deal of effort.
Additionally, as systems have expanded in scale and become more complex in recent years, the amount of data has increased and translation has become more complex.
Such a display method could not deal with the problem. The present invention has been made in view of the above circumstances, and its purpose is to eliminate the need for an operator to translate when displaying a sequence program stored in a sequence device, and to shorten the working time. The purpose is to provide a display device for such sequence programs. The present invention will be described in detail below with reference to FIGS. 3 and 4. Figure 3 shows the sequence program display device.
It is installed in the sequence program loader 3 shown in FIG. In Fig. 3, 31 is a display, in this example
It is now possible to display 32 characters. 32
is a shift register which, when first data is input from a control circuit 34 (described later) via a register 33, stores the data and displays it on the display 31, and outputs an RDY signal indicating completion of storage to the control circuit 34. Based on the RDY signal, the control circuit 34
When the th data is output to the register 33, the shift register 32 shifts the 1st data to the left, stores the data in the register 33 in the location where the 1st data was stored, and displays on the display 31 that the data should be output. . Below, 32 characters are displayed in the same manner. When a right shift signal is input from the terminal T1 in this display state, the data stored in the shift register 32 is shifted to the right by 1 in synchronization with the clock signal from the clock pulse generation circuit 35.
At the same time, the right shift signal is also input to the control circuit 34, and the data to be displayed is output to the register 33. The shift register 32 stores this data at the left end and displays it on the display 31. The same holds true when a left shift signal is input from the terminal T2. A control circuit 34 surrounded by a dashed line includes a control section S, a code conversion circuit K, a character memory circuit M1, and a one-line memory circuit M2. When the control unit S inputs a line number signal from the terminal T3, it inputs data for one line of the corresponding line number from the sequence program memory 54 shown in FIG. 1, and stores the data for one line in the memory circuit M2. do. Then, one word at a time is extracted from this memory circuit M2, converted into several characters via a code conversion circuit K, and stored in the character memory circuit M1. This code conversion circuit K translates one word of data represented by "1" and "0" into a code of several characters. For example, the second
1 of “1 000 011 111 000 010” at address 5 in the diagram
Translating the word data becomes "*M1702A". Change this to “052” (*), “115” (M), “061”
(1), “067” (7), “060” (0), “062” (2), “101”
”(A)
7 characters of ASCII code (ASCII
CODE) and stored in the character memory circuit M1 as shown in FIG. This character memory circuit M1 can store 256 to 512 characters. If one line of data is 64 words, 448 (64×7=448) characters are stored in the character memory circuit M1. Then, the control section S takes out data one by one from the stored character memory circuit M1 and outputs it to the register 33.The shift register 32 takes this data and returns the RDY signal to the control section S, and then the next data is input to the register. Output to 33. At this time, the control unit S controls the first address F of the character memory circuit M1 that was first output.
I remember P. Further, data is outputted one after another, and when the 32nd character is outputted, the last address L and P of the last outputted character memory circuit M1 is stored. Now, last address L.P.
Assume that the code “060” in FIG. 4 is shown.
At this time, when a left shift signal is input to the control unit S from the terminal T2, the control unit S executes the last address L・P=last address L・P+1, indicates the code “062”, and stores this in the register 33. Output data. First address F・P also first address F・P = first address +1
This is the address where the command was executed. The operation of the device configured as described above will be explained next. In addition to the code area shown in FIG. 2, the sequence program memory 54 has memory addresses, and each line has memory areas for elements such as +, ×, →, I, and O. Therefore, its designation and reading are performed by read and write commands for memory addresses. Therefore, when a line designation is input from the key top as the loader 3, the internal logic converts it to a certain address in the memory area.
That is, when a line number signal is input to the control unit S from the terminal T3, the control unit S stores one line of data corresponding to the input line number signal from the sequence program memory 54 into one line of memory. Stored in circuit M2. The data stored in the memory circuit M2 is extracted one word at a time, converted into a code for several characters via the code variable circuit K, and stored in the character memory circuit M1. This is applied to all the data for one line. conduct. Then, data is extracted one by one from the character memory circuit M1 and output to the register 33. shift register 3
2 stores the data in this register 33, and when the shift register 32 stores 32 characters, the stored data is output to the display 31 and displayed. At this time, when a right shift signal is input from the terminal T1, the control section S executes the first address F.P=first address F.P-1 and transfers the data at the first address F.P to the register 33. Output to. The shift register 32 shifts the stored data one place to the right, inputs the data in the register 33 to the left end, and displays it on the display 31. Further, when a left shift signal is input from the terminal T3, the control section S executes the last address L.P=last address L.P+1 and outputs the data at the last address L.P to the register 33.
The shift register 32 shifts the stored data by one position to the left, inputs the data in the register 33 to the right end, and displays it on the display 31. By inputting the left/right shift signals from the terminals T1 and T2 in this manner, the data stored in the sequence program memory 54 can be quickly retrieved. The data to be displayed on the display 31 can be displayed by rotating one line of data, and since the memory area (memory for storing sequence programs) and the display are connected in a chain, the left and right It is also possible to continuously display the data contents for each line number by giving a shift instruction. The speed of the shift is also determined by the speed changeover switch of the clock pulse generation circuit 35.
This can be done by switching SW. As described above, according to the present invention, a sequence program is stored in a sequence program memory as a complex code, and the stored code can be displayed in an easy-to-read format for the operator without the operator having to translate and judge it. This function has excellent advantages such as being able to display the required data more quickly than the shift function, shortening the operator's work time, and being able to handle a large amount of data.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram showing the sequence device, Figure 2
FIG. 3 is a map diagram showing the sequence program memory of the sequence device, FIG. 3 is a configuration diagram showing an embodiment of the present invention, and FIG. 4 is a map diagram of the character memory circuit M1 for explaining the present invention. be.
1 is the CPU, 2 is the CPU memory, 3 is the program loader, 4 is the program loader interface, 5
is a logic section, 51 is a logic bus interface, 52
53 is a logic operation section, 53 is a control information section, 54 is a sequence program memory, 6 is a PIO control section, 31 is a display, 32 is a shift register, 33 is a register, 34 is a control circuit, 35 is a clock pulse generator, S is a In the control section, K is a code conversion circuit, M1 is a character memory circuit, and M2 is a memory circuit for one line.

Claims (1)

[Claims] 1. In a sequencer device that loads the object code of a sequence program from a program loader into a sequence program memory and displays the loaded sequence program on the program loader, a display device that displays a character on the program loader; A shift register that outputs a storage signal to a display and shifts the storage signal left and right using a shift signal synchronized with a clock signal from a clock pulse generation circuit, and a control circuit that outputs a signal to this shift register via the register. A one-line memory section that stores one line of data from the sequence program memory, a code conversion section that converts one line of data in this memory section into a character, and a code conversion section that converts the control circuit into a character. A display of a sequence program characterized in that a control circuit is configured by a control section that stores a converted character in a character memory section, selects a character in the character memory section based on the shift signal, and outputs it to the register. Device.