JPS6219107B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a video signal processing circuit.

For conventional television receivers,
The reference voltage generation circuit of the IFAGC (Intermediate Frequency Automatic Gain Control) circuit and the carrier zero level generation circuit of the video detection output amplification circuit were to generate their respective voltage levels independently, so fluctuations in the power supply voltage could cause Output voltage fluctuates. In particular, in the case of portable television receivers that use battery voltage as a power source, there is a problem in that the contrast changes due to fluctuations in the video output voltage, since the voltage decreases significantly due to battery consumption.

The present invention was made in order to provide a video signal processing circuit that can stabilize video output voltage against fluctuations in power supply voltage.

Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

The video signal processing circuit according to this embodiment includes an intermediate frequency amplification circuit 1, a video detection circuit 2 to which the output of the intermediate frequency amplification circuit 1 is applied, and a video detection circuit 2 to which the output of the video detection circuit 2 is applied to the input. an amplifier circuit 3, a load resistor RL to which the output of the amplifier circuit 3 is applied to its first input, and a load resistor RL to which the output of the amplifier circuit 3 is applied to its first input, and to its second input.
AGC circuit 5 to which an AGC reference voltage is applied and controls the gain of intermediate frequency amplifier circuit 1 by its output
and a video output voltage stabilizing circuit composed of transistors Q ₁ , Q ₂ and the like.

Further, this video output voltage stabilizing circuit includes a transistor Q ₁ to which a divided voltage of the power supply voltage proportional to the change in the power supply voltage Vcc is applied to the base, a constant current circuit Q ₂ , and an emitter of the transistor Q ₁ . Level shift means connected between constant current circuit _Q2
A common connection point between the emitter of the transistor _Q1 and one end of the level shift means _R1 is connected to the other end of the load resistor RL _, and the other end of the level shift means _R1 is connected to the constant current circuit _Q2. The voltage at the common connection point with
This voltage is applied to the second input of the AGC circuit 5 as an AGC reference voltage.

In addition, the output of the amplifier circuit 3 is passed through a filter circuit 4 for smoothing and holding the synchronized peak value of the video output voltage.
The signal is applied to the first input of the AGC circuit 5 via.

In this way, a divided voltage proportional to the change in the power supply voltage Vcc is generated with low output impedance from the emitter of the transistor _Q1 , which operates as an emitter follower by being connected to the voltage dividing resistors R ₃ and R ₄ at its base. .

On the other hand, a transistor that operates as a constant current circuit
Since the collector current of Q ₂ is almost constant regardless of fluctuations in the power supply voltage Vcc, the voltage drop across resistor R ₁ as a level shift means is also almost constant, and
The voltage at the common connection point between R ₁ and the collector of transistor Q ₂ is the voltage at the emitter of transistor Q ₁ minus the voltage drop across resistor R ₁ .

Therefore, the DC level (carrier zero level) Ko of the video output signal applied from one end of the load resistor RL driven by the output current of the amplifier circuit 3 to the input of the next stage video amplifier circuit (not shown) is the power supply voltage
Since the voltage is proportional to Vcc, this video output signal can be applied directly to the input of the next stage video amplification circuit.

On the other hand, a voltage obtained by subtracting the base peak value of the video output voltage of the load resistor RL from the carrier zero level Ko is applied to the first input of the AGC circuit 5, and the carrier zero level Ko is applied to the second input of the AGC circuit 5. The voltage obtained by subtracting the constant voltage drop of the resistor _R1 as a level shift means is applied as the AGC reference voltage, and the output of this AGC circuit 5 controls the gain of the intermediate frequency amplifier circuit 1, so the carrier zero level Ko
AGC so that the amplitude of the synchronized peak value of the video output voltage with reference to _the
Since this is controlled, the amplitude of the video output voltage generated across the load resistor RL is constant regardless of fluctuations in the power supply voltage Vcc, and a screen with stable contrast can be obtained.

The video output voltage stabilizing circuit constituted by transistors Q ₁ , Q _{2 ,} etc. will be described in detail below.

The Zener diode Z and the diodes D ₁ and D ₂ connected in series are for forming a constant voltage, and this constant voltage is applied to the base of the series resistor R ₅ provided at the emitter of the transistor Q ₃ . R ₆ and diode D ₃ are for forming a constant current.

That is, this constant current I ₁ is obtained by the following equation (1).

I ₁ =V _F +V _D1 +V _D2 -V _BEQ3 -V _D3 /R ₅
+R ₆ ......(1) Here, V _F is the Zener voltage, and V _D is the forward voltage of the diode. The above diodes D ₁ , D ₂
is for temperature compensation for the transistor Q ₃ and diode D ₃ , and the diode D ₃ is
This is for temperature compensation of constant current transistor _Q2 , which will be described later. Therefore, the above current I ₁ is approximately V
It is determined by _F /R ₅ + R ₆ .

A current mirror circuit consisting of a diode-connected pnp transistor _Q4 and a pnp transistor _Q5 having a common emitter and base with this transistor _Q4 is provided at the collector of the transistor _{Q3 .} It is used as a constant current load for the Zener diode Z mentioned above.

Note that the resistor _R7 provided between the emitter and collector of the transistor _Q5 is a starting resistor when the power is turned on, and when the power is turned on, voltage is first supplied through this resistor _R7 , so that The Zener diode Z operates to form the constant voltage, and the constant voltage is used as the operating current of the Zener diode Z, which forms a constant current, so an extremely stable constant voltage can be formed.
This provides a stable constant current.

The series resistors R ₃ and R ₄ constitute a voltage dividing circuit for the power supply voltage, and a carrier zero level is formed from the emitter of the transistor Q ₁ to which this divided voltage is applied to the base. The emitter of this transistor _Q1 has
A resistor R ₁ is provided, and the other end is connected to the collector of a constant current transistor Q ₂ .

At the base of this transistor _Q2 , there is a resistor with the above constant voltage (V _Z +V _D1 +V _D2 -V _BEQ3 -V _D3 ).
A constant current I ₂ is obtained by applying a divided voltage by R ₅ and R ₆ and providing a resistor R ₂ at the emitter.

That is, this current I ₂ is obtained by the following equation (2).

I ₂ =R ₆ /R ₂ (R ₅ +R ₆ ) [(V _Z +V _D1 +V _D2 −
V _BEQ3 - V _D3 ) + V _D3 - V _BEQ2 ] ...... (3) Here, since V _D1 = V _D2 = V _BEQ3 = V _D3 = V _BEQ2 , the current I ₂ is R ₆ /R ₂ ( R ₅ +R ₆ ) The constant current is determined by V _Z.

The emitter voltage of the transistor Q ₁ is used as the carrier zero level, and the collector voltage of the transistor Q ₂ is used as the IFAGC reference voltage, and the carrier zero level is R ₄ /R ₃ +R ₄ Vcc - V _B
EQ1 , which changes according to fluctuations in the power supply voltage _Vcc . On the other hand, the IFAGC reference voltage is the voltage obtained by subtracting the constant voltage drop R ₁ I ₂ across the resistor R ₁ from the carrier zero level.

Therefore, a divided voltage proportional to the change in the power supply voltage Vcc is applied as a carrier zero level Ko from the emitter of the transistor _Q1 to the input of the next stage video amplifier circuit via the other end and one end of the load resistor RL. Therefore, the video output signal of the amplifier circuit 3 can be directly applied to the input of the video amplifier circuit at the next stage.

Furthermore, the amplitude of the video output voltage across the load resistor RL is a constant voltage drop R ₁ I 2 which is the difference voltage between the carrier zero level Ko at one end of the resistor R ₁ as a level means and the IFAGC voltage at the _other end. to match
Since it is AGC controlled, the amplitude of the video output voltage generated across the load resistor RL remains constant regardless of fluctuations in the power supply voltage Vcc, making it possible to obtain a screen with stable contrast.

The present invention is not limited to the above embodiments, and the present invention is not limited to the above embodiments.
The constant current circuit for passing a constant current through _R1 can be modified in various ways.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram of a video output signal. 1...Intermediate frequency amplification circuit, 2...Video detection circuit, 3...Amplification circuit, 4...Filter circuit, 5
...AGC circuit.

Claims (1)

[Claims] 1. An intermediate frequency amplification circuit, a video detection circuit to which the output of the intermediate frequency amplification circuit is applied to its input, an amplifier circuit to which the output of the video detection circuit is applied to its input, a load resistor to which the output of the amplifier circuit is applied to one end; the output of the amplifier circuit is applied to its first input; and the AGC reference voltage is applied to its second input; The video signal processing circuit includes an AGC circuit that controls the gain of the circuit and a video output voltage stabilization circuit, and the video output voltage stabilization circuit has a base that controls the power supply voltage that is proportional to the change in the power supply voltage. A transistor to which a divided voltage is applied, a constant current circuit, and a level shift means connected between an emitter of the transistor and the constant current circuit, the emitter of the transistor and one end of the level shift means. The common connection point between the level shift means and the constant current circuit is connected to the other end of the load resistor, and the voltage at the common connection point between the other end of the level shift means and the constant current circuit is applied as the AGC reference voltage to the second input of the AGC circuit. A video signal processing circuit characterized in that a voltage is applied to the video signal. 2. The video signal processing circuit according to claim 1, wherein the output of the amplifier circuit is applied to the first input of the AGC circuit via a filter circuit.