JPS6223272B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a stopwatch device that outputs audio, and more particularly to an improved stopwatch device for measuring lap times.

The method of outputting lap time in conventional stopwatch devices is as follows: (i) The display section that normally displays the counted elapsed time is also used, and when output of lap time is instructed, the display section is switched to display the lap time. (ii) When the output of lap time is instructed, there is a method of displaying it on a display section dedicated to lap time, which is separate from the display section that displays the elapsed time being counted. However, (i)
In this case, the lap time is switched and displayed on the same display, so if you want to see the elapsed time count again, you have to perform another external operation to switch and display it, which is a hassle from an operational standpoint. Additionally, there was a problem in that the lap time and the elapsed time currently being counted could not be checked at the same time. Also, (ii)
In this case, although it has the advantage of being able to check the lap time and the elapsed time currently being counted,
At least two display sections are required, which impedes miniaturization of the device itself, and similar time data is displayed adjacently, so there is a risk of transcribing the lap time by mistake when recording it on a sheet. It was hot.

In order to eliminate these conventional drawbacks, the present invention is characterized in that when measuring the lap time, for example, the lap time is announced by outputting audio.

An embodiment of the present invention will be described below with reference to the drawings.

The block diagram of FIG. 1 shows a stopwatch device according to an embodiment of the present invention incorporated into an ordinary timepiece device.

CG is a standard time signal generator, DV is a frequency divider, e.g. emitted from a standard time signal generator CG
A standard time signal of 32768KHz is divided by a frequency divider DV to obtain a 1Hz 1 second signal, etc. C ₁ is 1 above
A counting counter that counts the time and date by inputting a second signal. Usually, the contents of these counts are input to the display buffer B and displayed on the display device DSP via the decoder DC, and functions as a general clock device. do.

_C2 is an elapsed time counter, R and _R0 are registers for storing lap time, VCC is an audio output control circuit, SP is a speaker, TK is a stopwatch key, LK is a lap time key,
These constitute the main parts of the stopwatch device according to one embodiment of the present invention. This will be explained in more detail below.

When the stopwatch key TK is operated, a T-type flip-flop TF is set via the one-shot signal generator _A1 . When TF is set, the 1-second signal obtained from the frequency divider DV is input to the elapsed time counter _C2 via the AND gate _G1 , and the elapsed time from the time the stopwatch key TK was operated is sequentially counted. Ru. Furthermore, at this time,
Due to mode switching to stopwatch operation, the display buffer register B is switched to the elapsed time counter _C2 side, and the count contents of the elapsed time counter _C2 are displayed on the display device DSP via the decoder DC. Is displayed. When the stopwatch key TK is operated again in this state, the T-type flip-flop TF is reset, the AND gate _G1 is turned off, and the counting operation of the elapsed time counter _C2 is stopped. While this counting operation is stopped, the count contents of the elapsed time counter _C2 are held as they are, and when the stopwatch key TK is further operated to set the T-type flip-flop TF, the counting operation is continued.

In this way, the operation of the stopwatch key TK has the function of instructing execution of start and stop of the stopwatch.

If you operate the lap time key LK while the T-type flip-flop TF is reset,
The one shot signal from the one shot signal generator _A2 is inputted to the reset terminal of the elapsed time counter _C2 via the AND gate _G2 , so that the contents of this count can be reset to the initial state. In other words, here the key for lap time is
Also serves as LK to issue a stopwatch reset instruction.

Now, when the lap time key LK is operated while the elapsed time counter _C2 is counting one-second signals (while the T-type flip-flop TF is being set), the one-shot signal generated from the one-shot signal generator _A2 generates an AND signal. The count contents of the elapsed time counter _C2 are transferred to the storage register P and buffer register _R0 via the gate _G3 . S is storage register R and buffer register
It generates a shift signal of _R0 , which is supplied via AND gate _G4 during this transfer. Furthermore, by operating the lap time key LK, the RS flip-flop F is simultaneously set via the one-shot signal generator _A2 .

After that, while the elapsed time being counted is displayed as it is on the display device DSP, the wrap time, that is, the count contents transferred to the storage register R and buffer register _R0 are sequentially displayed in the audio output control circuit.
It is supplied to VCC and output as audio via speaker SP. The outline of the audio output control circuit VCC is shown in Fig. 2.

VR is a memory unit consisting of read-only memory that stores audio quantized data.
VAC is an address counter and VAD is an address decoder. CLA is a reset circuit that resets the address counter VAC when no audio is output, so that it does not specify any address in the memory unit VR. FA is address counter
This is an adder for incrementing the VAC address one step at a time, and the initial address of any audio area P is added to the address counter in order to output audio.
If set to VAC, it will automatically perform VAC + 1 → VAC at a constant sampling frequency from then on.
The quantized data of the corresponding area P is read out sequentially.

CC is code conversion circuit, audio output control circuit
The audio area designation signal _S1 supplied to VCC is input and converted into a code for setting the initial address of the audio area P to be output in the address counter VAC. S ₀ is a trigger signal required for transmission to address counter VAC. JE is each area P
The END code detection circuit detects the END (end) code formed at the final step of the process, and this output operates the reset circuit CLA to reset the address counter VAC. This output is also led out as a signal _S2 and operates to set the next initial address.

DAC is a digital-to-analog (DA) conversion circuit, LPF is a low-pass filter, DD is a speaker drive circuit, and SP is the aforementioned speaker.

In Figure 1, first, buffer register R ₀
The content transferred to is supplied to the audio output control circuit VCC as the first audio area designation signal _S1 . Then, when the one-shot signal is input as the trigger signal _S0 to the audio output control circuit VCC via the delay circuit _D1 and the OR gate _O1 , the audio is output from the speaker SP according to its contents. When the audio output based on the contents of the buffer register _R0 is completed, the audio output control circuit VCC outputs the signal _S2 , which causes _the counter _C3 to count up by one and also A shift pulse is applied to storage register R and buffer register _R0 . Then, by the shift pulse, the storage register R and buffer register R ₀
The contents of buffer register R ₀ are shifted by one digit.
The shifted contents are supplied to the audio output control circuit VCC as the next audio area designation signal _S1 . Trigger signal S ₀ delays the shift pulse taken out from AND gate G ₅ in delay circuit D ₂ and outputs it to OR gate O ₁
It is input by way of .

The contents transferred to the storage register R and buffer register _R0 in this manner are sequentially output as audio. For example, if the contents of elapsed time counter _C2 are
If the lap time key LK was operated at 36 minutes and 40 seconds, the speaker SP would say "Sanji Yuu".
The voice output says "Lotupun Yongjiyuubiyo".

The set value of counter _C3 is the elapsed time counter.
The counter is set to the number of digits of C ₂ or the number of digits within that required for the lap time.
When the value of _C3 reaches a preset value, an output signal is generated and the RS type flip-flop F is reset. This completes the lap time audio output operation.

The lap time key LK can be operated at any time during the counting operation of the elapsed time counter _C2 , and each time the lap time is operated, the lap time at that point in time can be outputted as a sound.

In the above embodiment, when measuring the lap time, the elapsed time is displayed as is and the lap time is outputted as audio. It may also be output. FIG. 3 is a block diagram showing the latter embodiment. Components having the same functions as those in FIG. 1 are designated with the same reference numerals.

In normal stopwatch mode, the contents counted by the elapsed time counter _C2 are supplied to the display buffer register B via the AND gate _G6 , and displayed on the display device DSP via the decoder DC. Ru. When the lap time key LK is operated, a one-shot signal generated from the one-shot signal generator _A2 causes the count contents of the elapsed time counter _C2 at that point to be stored in a separate storage register via the gate _G3 .
This memory content is stored in R′ and the AND gate G ₇
The signal is supplied to the display buffer register B via the display device DSP, and a so-called lap time display is performed on the display device DSP. The AND gate _G7 is turned on by the output of the T-type flip-flop _TF2 set by the above-mentioned one-shot signal, and is controlled by switching with the AND gate _G6 on the elapsed time counter _C2 side. At the same time, the T-type flip-flop TF ₂ is set by inputting the count contents of the elapsed time counter C ₂ to the sequential storage register R and the buffer register R ₀ via the AND gate G ₈ to the audio output control circuit. Audio is output from speaker SP via VCC.

In FIG. 2, since it is impossible in terms of time to output audio almost simultaneously with the elapsed time of the elapsed time counter _C2 , a timer circuit Ti is provided and the counted contents are stored in the storage register R and the buffer register at predetermined intervals. I am trying to transfer it to R ₀ .
In order to output audio for each elapsed time, it is possible to output audio only the second data without audio outputting the hour and minute data, and this method can also be easily implemented.

When the lap time key LK is operated again, the T-type flip-flop _TF2 is reset and the elapsed time display returns to the normal stopwatch mode.

As explained above, according to the stopwatch device of the present invention, when the lap time is measured, the user is notified by outputting one of the elapsed time or the lap time by voice and outputting the other by displaying, and one display section informs the user of the two values. You can check different types of information at the same time, and
The device can be made more compact. In this way, it is convenient to be able to check both pieces of information at the same time, and since the output methods are different for both pieces of information, it is possible to ensure that there are no errors in transcription of lap times. In addition, the device that outputs the lap time audibly is especially useful for athletes such as runners who can use the device to confirm their lap time through audible output during competition practice, allowing them to conduct effective competition practice. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a block diagram showing the essential parts of FIG. 1 in more detail, and FIG. 3 is a block diagram showing another embodiment of the present invention. CG...Standard time signal generator, DV...Frequency divider, C ₂ ...
Elapsed time counter, B...Display buffer register, DC...Decoder, DSP...Display device, R...Storage register, _R0 ...Buffer register, VCC...Audio output control circuit, SP...Speaker, TK...Key for stopwatch , LK...Lap time key, TF
...T type flip-flop, F...RS type flip-flop, TF ₁ /TF ₂ ...T type flip-flop,
R′...memory register, Ti...timer circuit.

Claims (1)

[Scope of Claims] 1. A stopwatch device that counts elapsed time from a start point, comprising: a time signal generating device that outputs a standard time signal; a time counting device that counts the time signal; and a counting operation of the time counting device. an operating switch that is operated to measure the lap time; a storage device that stores the time counted by the time counting device as the lap time when the operating switch is operated; and an elapsed time of the time counting device or a sound generating means for outputting the contents of the lap time in the storage device; a display device for displaying the elapsed time of the time counting device or the contents of the lap time in the storage device; and when the lap time is measured by the operation switch. control means for transmitting the contents of the lap time in the storage device or the elapsed time in the time counting device to the sound generating means or the display device; 1. A stopwatch device characterized in that the stopwatch device is configured to display one signal and output the other signal on a display.