JPS622350B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control circuit that sends data onto a data bus in response to a specific address output onto an address bus.

Conventionally, there has been a control circuit of this type as shown in FIG. In Figure 1, 1 is the address
The receiver 2 receives the address signal ADS from the bus 1a, and the receiver 2 receives the upper address signal ADSU from the receiver 1 via the address bus 1b, compares it with a preset self-address, and when a match is found, the address A collation circuit that energizes the match signal ADIN; 3 a register that receives the lower address signal ADSL from the receiver 1 via the address bus 1c and reads data; 4 a register that receives the address match signal ADIN and the strobe signal STR; AND gate that generates the enable signal DEN by ANDing, 5 is the enable signal
This is a driver that sends data DATA from register 3 to data bus 5a in response to DEN.

The operation of the control circuit shown in FIG. 1 will be explained. The address signal ADS is input to the verification circuit 2 via the receiver 1, and is verified against its own address. As a result, when the self address is detected, the address match signal ADIN goes high and the strobe signal
AND gate 4 opens by STR, and
Gate 4 makes enable signal DEN of driver 5 high.

On the other hand, the address of the register 3 is specified by the address signal ADSL, and the data DATA is outputted, ie, read, by the strobe signal STR. This data DATA is sent to the data bus 5a via the driver 5.

By the way, the driver 5 receives the enable signal
When enabled by DEN, the data DATA
Switching is performed according to the content of data bus 5.
Since a considerable amount of current flows through the address bus 1a through a power supply circuit (not shown) or by electrical floating coupling, switching noise is induced in the address bus 1a, which disturbs the verification in the verification circuit 2 and causes a mismatch. Make it into something. When this switching noise disappears, the matching circuit 2 detects address matching again and sets the enable signal DEN high. As a result, switching noise occurs again, and the above-mentioned process is repeated, and the data DATA on the data bus 5a is affected by the switching noise.

FIG. 2 shows another conventional control circuit designed to eliminate the above drawbacks. In Figure 2, the same parts as in Figure 1 are given the same symbols.
6 is a so-called latch circuit, which outputs an address match signal.
ADIN is introduced into the data input D, the clock signal CLK is introduced into the clock input T, and the enable signal DEN is provided from the set output Q.

FIG. 3 is a time chart explaining the operation of the control circuit shown in FIG. address bus 1a
When the address signal ADS is input to the receiver 1 via the address signal ADSU, the address signal ADSU is sent to the verification circuit 2. Address signal at time t ₁
When the content of ADSU is the address of the circuit concerned, that is, the self address, the address match signal ADIN
is output from the matching circuit 2. Thereafter, at time _t2 , the strobe signal STR is generated, and the register 3 outputs data at the address position specified by the contents of the address signal ADSL. At time _t3 of the next clock timing, latch circuit 6
is set and the enable signal DEN is output, the driver 5 sends out the data DATA of the register 3 to the data bus 5a. Due to the operation of driver 5, switching noise becomes an address signal.
Although it is superimposed on the ADS and address match signal ADIN, the latch circuit 6 is not affected by it. Therefore, the data DATA on the data bus 5a becomes stable. Moreover, if the register 3 quickly responds to the address signal on which switching noise is superimposed, the data DATA from the register 3 will also be disturbed due to the disturbance in the address signal ADS, as shown in FIG.

Conventional data output control circuits have the above-described configuration, but have the disadvantage that data on the data bus is affected by switching noise, making it impossible to send stable data onto the data bus. Ta.

This invention was made in order to eliminate the drawbacks of the conventional devices as described above. After the address match signal is latched, an enable signal for driving the driver is output, and during this enable period, the address match signal is output. It is an object of the present invention to provide a data output control circuit that does not respond to bus signals, thereby making data on a data bus stable and unaffected by switching noise.

The block diagram of FIG. 4 showing one embodiment of the present invention will be described above. In Figure 4, the second
The same parts as in the figure are given the same reference numerals, and 7 is a latch circuit. When the enable signal DEN input to the enable input is low, the latch circuit 7 uses the output of the receiver 1 as an address signal.
Output to address buses 1b and 1c as ADSU and ADSL. When the enable signal DEN changes from low to high, the output of receiver 1 is latched,
When the enable signal DEN is high, the latch contents are sent to the address signal regardless of the output of receiver 1.
Address bus 1b, 1c as ADSU, ADSL
Output to.

Next, the operation will be explained with reference to FIG. An address signal ADS is input to the latch circuit 7 via the receiver 1 via the address bus 1a and is latched therein. The latch circuit 7 inputs the latched address signal ADSU to the verification circuit 2 and checks whether it matches its own address. Once this match is obtained,
Verification circuit 2 outputs address match signal ADIN (time t ₁ ). At time _t2 , the strobe signal STR
is input, and the register 3 outputs data DATA according to the address signal ADSL. At time _t3 , the clock signal CLK causes the latch circuit 6 to set the address match signal ADIN and make the enable signal DEN high. As a result, driver 5
is the data of register 3 on data bus 5a.
DATA is sent, and the latch circuit 7 is prohibited from updating the latch contents. Driver 5 is an enable signal
When switching by DEN, the switching noise is caused by the address signal ADS as shown in the figure.
However, the address signals ADSU and ADSL on the output side of the latch circuit 7 are not affected. Therefore,
Even if the register 3 responds quickly, the data DATA on the data bus 5a will be stable.

As described above, according to the present invention, the address match signal is once latched in the latch circuit, and the output of the address match signal is used to switch the driver that drives the data bus to send out the data. This circuit latches the circuit so that it does not take in changes in the address signal, so even if noise is induced from the data bus to the address bus, it does not affect the output of the latch circuit, and therefore the data on the data bus is It can be made stable.

[Brief explanation of the drawing]

1 and 2 are circuit diagrams of a conventional data output control circuit, FIG. 3 is a time chart explaining the operation of the circuit of FIG. 2, and FIG. 4 is a data output control circuit according to an embodiment of the present invention. FIG. 5 is a time chart explaining the operation of the circuit shown in FIG. 1...Receiver, 2...Verification circuit, 3...Register, 5...Driver, 6, 7...Latch circuit.
In addition, in the figures, the same reference numerals indicate the same parts.

Claims (1)

[Claims] 1 A verification circuit that compares an address signal input via an address bus with a preset self-address and generates an address match signal indicating address match when a match is detected, and the address match signal a latch circuit that latches the clock signal using a clock signal; a driver that sends data onto a data bus using the output of the latch circuit; A data output control circuit comprising an address latch circuit that latches and supplies the data to the verification circuit.