JPS622464B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention provides an insulated gate (MIS) type integrated circuit device.
MISIC) input/output protection circuit.

Generally, MISICs are equipped with input protection to prevent damage to the gate insulating film that occurs when abnormal voltages due to noise or noise are applied to the input terminals.

Conventionally, input/output protection circuits have been designed to break junction _D1 using an impurity diffusion layer as shown in Figure 1.
Commonly used transistors are ones that utilize a down transistor, and ones that use MIS type transistors Q ₂₂ and Q ₃₂ as shown in FIGS. 2 and 3. However, whereas Figure 2 utilizes the punch-through phenomenon between the source and drain of the MIS transistor _Q22 , Figure 3 utilizes the conductive phenomenon due to the inversion layer under the gate electrode. It is. Therefore, in the case of Figure 3, for protection
The threshold voltage V _TH of the MIS transistor Q ₃₂ must be set higher than the maximum value V _IH of the normal signal voltage handled by the input terminal N ₃ and lower than the dielectric strength voltage of the gate insulating film of the first stage transistor Q ₃₁ . . This is because if V _TH is lower than V _IH , leakage current will occur at the input terminal, impairing the MISIC function.
In this case, a thick silicon oxide film for element isolation, which is often used inside MISIC, is often used as the gate insulating film of _Q32 .

However, since the input protection circuits shown in Figures 1 and 2 basically utilize the reverse bias characteristics of the P-N junction, the league current is extremely small under normal conditions. When the actual voltage is applied to the input terminal, the resistance becomes very small and the threshold voltage is relatively high, around 30V, so an excessive current flows rapidly, and as a result, the input protection element This may cause thermal breakdown of the diffused resistor or P-N junction of the MIS type transistor, or melting of the aluminum layer used for wiring.

Also, regarding the input protection circuit shown in Figure 3, when the above transistor is used as Q ₃₂ , the threshold voltage is still relatively high, around 40V, and the resistance of the channel section is large, so it also generates heat. However, the P-N junction may deteriorate, or the aluminum wiring layer near the P-N junction may melt and flow out, causing a short circuit with other adjacent aluminum wiring layers.

For this purpose, thinning the gate insulating film of Q ₃₂ and lowering the threshold voltage is effective, but other
It is necessary to form the input protection MIS type transistor _Q32 by forming a gate insulating film different from that of the MIS type transistor or by implanting ions into the channel region, which is undesirable because the process becomes long.

The purpose of the present invention is to provide MISIC input terminals or
An object of the present invention is to provide an effective input protection circuit for preventing damage caused by abnormal voltage to an output terminal.

FIG. 4 shows a circuit diagram as an embodiment of the input terminal of the N-channel MISIC of the present invention. However, the MIS type transistor used here is an enhancement type.

In the input protection device according to the present invention, the source of an input protection MIS type transistor Q 42 having a gate electrode connected to the input terminal N ₄₁ or the output terminal of the MISIC via a capacitor C is grounded, and the drain is connected to the input terminal N ₄₁ of the MISIC to be protected. It is connected to the gate electrode of the first stage transistor Q ₄₁ or to the source or drain of the output transistor, and further between the input terminal N ₄₁ and the gate electrode of the first stage transistor Q ₄₁ or between the output terminal and the source of the output transistor. Alternatively, a resistance element is inserted between the drain and the drain.

In other words, as can be seen from the equivalent circuit shown in FIG.
The abnormal voltage applied to N ₅₁ is connected to capacitance C ₁ as shown in Fig. 4.
It is divided by the stray capacitance attached to _N44 and the combined capacitance _C0 such as the gate capacitance of _Q42 , and the voltage generated across _C0 is used as the gate input voltage of the input protection transistor _Q52 . Features. Therefore, the threshold voltage V _TH of input/output protection transistors Q ₄₂ and Q ₅₂
does not need to be restricted as in the case of the input protection circuit shown in Figure 3; it can be the same as the other transistors inside the MISIC to be protected, and the size of the capacitance C can be selected appropriately using the mask pattern. The input voltage V at which the input/output protection circuit starts operating is
It is possible to determine _{the ON} state, and there is no need to add a special process to fabricate input/output protection transistors.

Moreover, instead of using the reverse characteristics of the P-N junction shown in Figures 1 and 2, a channel with an inversion layer is used as a bypass circuit for current caused by abnormal voltage, as in Figure 3. Compared to the one in Fig. 3, as mentioned above, there is no limit to the V _TH of the input protection transistor Q ₄₂ ;
The gate insulating film can be made as thin as the other transistors inside the protected MISIC, and V _TH can be set low, so if an abnormal voltage is applied to the input or output terminal, the voltage will be relatively low. Since the response is very fast, the input terminal or output terminal can be clamped to a relatively low voltage, and the P-
Deterioration of the N junction and melting of the aluminum wiring layer can be prevented.

Furthermore, according to the present invention, since the gate electrode of the input protection transistor Q ₄₂ is insulated from the input terminal in terms of direct current, the drain of the enhancement type transistor Q ₄₃ is used for input protection as shown in FIG. If the source N 43 is connected to the gate electrode of the transistor Q ₄₂ and the source N ₄₃ is grounded or set to a negative substrate voltage, when Q ₄₃ is turned on, N ₄₄ is connected to the ground potential regardless of the change in the potential of the input terminal N ₄₁ . or,
By fixing the substrate to a negative potential, _Q42 can be maintained in the OFF state. Also, when _Q43 is turned OFF, _N44 becomes a floating state, and changes in the potential of input terminal _N41 cause _N44 to change. The potential begins to change,
It can perform the functions described above.

The input terminal of an N-channel MISIC will be taken as an example below.

If _N44 is always in a floating state and the potential of _N44 rises due to capacitive coupling with surrounding circuit elements, the input protection circuit will be activated by mistake if a signal voltage is applied to the input terminal, and the protected MISIC Since there is a possibility that the function of the V _ON
It is necessary to set Q 43, but when Q ₄₃ is added, even if the potential of N ₄₄ rises as described above, Q ₄₃ can be turned on.
By doing this, it is possible to return the potential of N ₄₄ to the ground potential or the negative potential of the substrate, and then
By keeping _Q43 in the OFF state, V _ON can be lowered even further without causing the input protection circuit to operate erroneously.

Furthermore, when a signal voltage is applied to the input terminal, Q ₄₃
By keeping V ON in the ON state, V _ON becomes V _IH
It is also possible to make it lower.

By adding Q ₄₃ in this way, it is possible to set V _ON even lower, thereby further increasing the effects of the present invention. However, in this case, if it is in the ON state, it will perform the same function as the protection circuit shown in FIG. 2.

For example, if _N42 is connected to the ground potential and _N43 is connected to the negative substrate potential, the gate electrode of _Q43 will be higher than the source, so if the substrate potential is lower than -V _TH ,
Q ₄₃ becomes ON state. Therefore, when the power supply voltage is not supplied to the MISIC to be protected, the input protection circuit according to the present invention is implemented. Also, N ₄₃ is ground potential, N ₄₂
If you connect a positive power supply to , the same operation will occur.

In addition, if there is a clock that becomes high potential when a signal voltage is applied to input terminal _N41 inside the MISIC to be protected, if _N43 is connected to the ground potential and the above clock is applied to _N42 , the The input protection circuit according to the present invention also functions except when a signal voltage is applied to the input terminal. In the above example, V _ON may be set below V _IN , but if V _ON is set higher than V _IN , N ₄₃ should be connected to ground potential, and N ₄₂ should be connected to the input signal voltage. It is also possible to provide a clock that is at a high potential during part or all of the time when the device is not in use (standby). In this case, the input protection circuit according to the present invention operates while the input signal voltage is applied and while the power supply voltage is not supplied, that is, except during standby. In this case, as shown in FIG. 6, if an enhancement type transistor _Q64 is added, its drain is connected to the input terminal _N61 , its source is connected to the ground potential, and the aforementioned clock is applied to the gate electrode, _Q64 remains active even during standby. It functions as input protection, and becomes an input/output protection circuit that always includes a bypass circuit using the channel area.

FIG. 7 shows an example of a pattern when the example of FIG. 4 of the present invention is implemented in MISIC. The broken line shows the N-type diffusion layer, the dashed line shows the polycrystalline silicon layer, and the solid line shows the contact opening and the aluminum wiring layer. Aluminum 71 is a pad for external input terminal N ₄₁ , 72 is a diffusion layer resistance R ₄ , and polysilicon layer 73 forms a gate electrode of an input protection transistor Q ₄₂ , and at the same time forms a capacitance C in the portion overlapping with aluminum 71 . is forming. Polycrystalline silicon layer 75 forms the gate electrode of Q ₄₃ , and aluminum 77 is connected to first stage transistor Q ₄₁ (not shown in FIG. 7). Note that this example shows an example in which N ₄₂ (aluminum 74) is the ground potential and N ₄₃ (aluminum 76) is the substrate potential.

Although the above description has mainly focused on the input terminal of the N-channel MISIC, the output terminal coupled to the drain or source can also be explained in detail.
The same can be said about the input/output terminals of channel type MISIC and complementary type MISIC.

[Brief explanation of the drawing]

FIGS. 1, 2, and 3 are diagrams showing conventional input protection circuits, respectively. FIGS. 4 and 6 are circuit diagrams showing an embodiment of the present invention, and FIG. 5 is a circuit diagram showing an embodiment of the present invention. FIG. 7, an equivalent circuit diagram for explaining the principle, is a diagram showing a pattern when the embodiment shown in FIG. 4 is implemented in an MIS type semiconductor integrated circuit. Q ₁ , Q ₂₁ , Q ₃₁ , Q ₄₁ , Q ₆₁ are the first stage transistors of the protected MIS type semiconductor integrated circuit, Q ₂₂ , Q ₃₂ ,
Q ₄₂ , Q ₅₂ , Q ₆₂ are protection transistors, Q ₄₃ , Q ₆₃
is a gate control transistor, Q ₆₄ is a second protection transistor, R ₁ , R ₂ , R ₃ , R ₄ ,
R ₅ , R ₆ are resistance elements, C, C ₀ , C ₁ , C ₂ are capacitive elements, N ₁ , N ₂ , N ₃ , N ₄₁ , N ₅₁ , N ₆₁ are external input terminals, N ₄₂ , N ₄₃ indicates a gate control terminal, and φ indicates a clock. Further, in FIG. 7, the solid line shows the aluminum wiring layer and the contact opening, the broken line shows the diffusion layer, and the one-dot chain line shows the polycrystalline silicon layer.

Claims (1)

[Claims] 1. A protective insulated gate field effect transistor having a gate electrode connected to an input terminal or an output terminal via a capacitive element has its source grounded, and its drain connected to a protected insulated gate field effect transistor. or between the input terminal and the gate electrode of the protected transistor, or between the output terminal and the source or drain of the output transistor. An integrated circuit characterized by having a resistive element inserted between the integrated circuits. 2. The gate electrode of the protection transistor is connected to the drain of the gate control enhancement transistor, so that the gate electrode of the protection transistor can be controlled to be in a floating state or in a state where it is maintained at a constant potential. An integrated circuit according to claim 1, characterized in that: 3. The drain of a second protection transistor whose source is grounded is connected to the gate electrode of the protected transistor or the source or drain of the output transistor, and the gate electrode of the second protection transistor and the gate - A control voltage that is at a high potential during at least a part of the period when no signal voltage is applied to the input terminal or output terminal is applied to the gate electrode of the control transistor, and the source of the gate control transistor is grounded. An integrated circuit according to claim 2, characterized in that: