JPS6224751B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock that announces the time by voice at a fixed time and at an arbitrary time, and in particular, when the time is announced by voice at an arbitrary time, a fixed time has come when the time should be forcibly announced by voice. When this occurs, the start of the scheduled audio notification is delayed until the audio notification at that time ends, so that the accurate time is audio announced.

2. Description of the Related Art In recent years, clocks have been proposed that notify by voice the time indicated by the clock or the alarm setting time as an additional function. This type of clock allows you to tell the time only by hearing when it is difficult to read the indicated time or alarm setting time, such as at night or while working in a factory, etc., and can also be widely used as a clock for the blind. . The methods for starting the audio notification operation of these watches include a method in which the time is forcibly announced audibly at fixed intervals, for example, every hour on the hour, and a method in which the time is audibly announced at any arbitrary time by operating an external switch. Since it is best to notify the designated time when necessary and at regular intervals,
Both of the above methods are used, and the latter method is used because it is not necessary to notify at regular intervals in the case of an alarm setting time.

However, if the method of audibly announcing the time at regular intervals and the method of audibly announcing the time at any time using an external switch are used together, it is possible to make an audible announcement by operating the external switch when the scheduled time for the audible announcement arrives. In some cases, the notification may be in progress, and this often results in situations in which scheduled audio notifications are not made. Furthermore, the time at which the voice notification is made at any time is often detected when an external switch is operated, and if the time notification is made over a period of time as described above, the time when the notification ends It was different from the time, so it could not be said to be an accurate time signal.

Furthermore, in a watch that notifies the alarm setting time by voice, if the set time to notify the specified time arrives while the alarm setting time is being notified by voice, the specified time will not be notified, so the user cannot This means that you will not be able to know the exact time of the instruction.

In this way, in the conventional audio time clock,
If the user operates an external switch at any time in order to know the specified time or alarm setting time, depending on the timing of the operation, the specified specified time will not be notified at the scheduled time, and this will prevent the user from receiving the specified time. Sometimes it was impossible to know the time, or sometimes a voice announcement was made at a time different from the instructed time.

The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to prevent accurate scheduled voice notification by causing an external switch to notify an arbitrary time or an alarm setting time by voice. The goal is to make sure that nothing happens.

In order to achieve the above-mentioned object, the present invention has the following features: When the scheduled time for time notification arrives while audio notification of the time is being made by operating an external switch, the audio notification of the time at the scheduled time is started. The feature is that the audio notification by the external switch is delayed until it is finished.

Embodiments of the present invention will be explained below based on the drawings.
FIG. 1 is a circuit diagram showing one embodiment of the present invention. In this embodiment, the designated time is announced audibly on the hour and when an external switch is operated, and when it is on the hour, a "pitsu" sound is generated on the hour, followed by "Tadaimajikokuha〇〇ji〇〇fun." is announced. And when you operate the external switch, you are immediately notified that ``Tadaimajikokuha〇〇ji〇〇fun.'' Furthermore, the clock of this embodiment has an alarm function added, and is configured so that when the above-mentioned external switch is operated after switching to the alarm mode, a voice notification will be issued saying "Alarm is coming at 00:00". .

In FIG. 1, a high frequency signal from a reference signal generator 2 including a crystal oscillator etc. is converted into a desired frequency-divided pulse train by a frequency dividing circuit 4, and the pulse train with a period of 1 second is supplied to a second counter 6. seconds counter 6
consists of a sexagesimal counter and supplies minute pulses with a period of 60 seconds to the minute counter 8. The minute counter 8 also consists of a sexagesimal counter and supplies its output, the hour pulse, to an hour counter 10 consisting of a decimal counter.

On the other hand, the preset alarm time is stored in the set time/minute memory 12 and the set time/hour memory 14, and the set time signals in both memories 12, 14 match the current time signals of the minute counter 8 and hour counter 10 described above. A comparison is made by circuit 16. Then, at the set time when both coincide, the coincidence circuit 16
The output signal 16a changes from "L" to "H" and is supplied to the AND gate 18. The 1024 Hz signal 4a from the frequency dividing circuit 4 and the output signal 20a from the alarm set/non-set switch 20 are input to the AND gate 18, and the output signal 18a of the AND gate 18 is supplied to the sound generation circuit 22 via the OR gate 21. be done. The sound generation circuit 22 is a mixer 2
4, an amplifier 26 and a speaker 28, the output signal 18a is supplied from the mixer 24 via the amplifier 26 to the speaker 28, and the speaker 28 generates an alarm notification sound.

Further, the minute time of the minute counter 8 and the contents of the set time/minute memory 12 are supplied to the multiplexer 30, and similarly, the hour/time of the hour counter 10 and the contents of the set time/hour memory 14 are supplied to the multiplexer 30.
2. Both multiplexers 30, 32
selects the designated time or the set time and supplies the selected time to the digital multiplexer 34. This selection is
via an externally operable mode selection switch 36 and a chattering prevention circuit 38.
This is done by a mode selection circuit 40 connected to. The mode selection circuit 40 is a circuit that forcibly switches to the specified time mode when the audio notification of the specified time on the hour is made, and is a flip-flop (hereinafter referred to as
(referred to as FF) 42 and an AND gate 44.
The output signal 36a of the mode selection switch 36 via the chattering prevention circuit 38 is input to the clock input φ of the FF 42, and the Q output signal 42a of the FF 42 is supplied to one input of the AND gate 44. Output signal 44a of AND gate 44
is supplied to multiplexers 30 and 32.
The output signal 44a of this AND gate 44 is also input to a multiplexer 50, which is connected to a "Tadaimaji Kokuha" code ROM 52 for reading out the "Tadaimaji Kokuha" sound and a "Alarm Jikokuha" sound. Select one of the code signals from the "alarm alarm" code ROM 54 for reading. The code signal selected by multiplexer 50 is then supplied to digital multiplexer 34. The digital multiplexer 34 includes a "Hun" code ROM 56 and a "Ji" code ROM 5 that output code signals for reading other "Hun" or "Ji" sounds.
8 are connected.

A signal for audio selection as described above outputted from the digital multiplexer 34 is supplied to an audio signal generation circuit 60, and an audio signal corresponding to the designated time or alarm time is supplied to the sound generation circuit 22. The audio signal generation circuit 60 has a storage section consisting of an audio ROM 62 that stores audio as digital values, and the audio ROM 62 contains time numerals, ie, numeric sounds from "zero" to "kiyu", "tadai magic kokuha", and "alarm jikoku". The sounds ``Ha'', ``J'', and ``Hun'' are stored, and the audio signal corresponding to the desired set time is selected based on the signal from the digital multiplexer 34. In the embodiment, the audio signal generation circuit 60
includes a start address designation ROM 64, an end address designation ROM 66, an address counter 68, and a digital comparator 70 in order to sequentially read out the audio ROM 62 based on the signal from the digital multiplexer 34. Then, the start address and end address, which are the selection signals from the digital multiplexer 34, are both specified.
It is stored in the ROMs 64 and 66. The selection signals are stored in the order of the output signals from the digital multiplexer 34. For example, in the case of the designated time "12:35", the selection signals are stored from the digital multiplexer 34.
First, the code signal of the "Tadaimaji Kokuha" code ROM 52 via the multiplexer 50 is stored in the start address and end address designating ROMs 64 and 66 as a selection signal. The start address of the specified ROM 64 is selected from the audio ROM 62 via the address counter 68 as the start address of the audio signal "Tadaimaji Kokuha", and this audio signal is accessed and converted into an analog signal by the DA converter 72. Further, unnecessary harmonic components are removed by a low-pass filter 74 and output to the sound generation circuit 22. The audio ROM 62 is accessed until the current address matches, and therefore the current address is sequentially accessed to the end address designation ROM 6.
6 end address and digital comparator 70
compared by. Then, the current address and the end address match, ie, the reading process of the audio signal "Tadaimaji Kokuha" is completed.

In order to sequentially update and supply the selection signal from the digital multiplexer 34 to the audio signal generation circuit 34,
Octal counter 7 to digital multiplexer 34
A count signal from 6 is supplied. When the octal counter 76 is reset, the signal from the counter 76 causes the digital multiplexer 34 to select the signal from the multiplexer 50. When the output of the audio signal of "Tadaimaji Kokuha" is completed and the comparison output of the digital comparator 70 is output, the octal counter 76 is counted +1 via the one shot circuit 78, and as a result, the digital multiplexer 34 outputs the comparison output at the designated time. The 10th place signal, that is, the selection signal of "JIU" is supplied to the audio signal generation circuit 60. Similarly, "ni", "ji"
The audio signals ``san'', ``jiyu'', ``go'', and ``hun'' are sequentially read out.

The above-mentioned instructed time or alarm setting time is read out by turning on the external switch 80. Output signal 8 of external switch 80
0a is supplied to the reset input R of the octal counter 76 via the OR gate 82 and the one-shot circuit 84, and is also supplied to the FF8 in the operation signal generation circuit 86 for operating the aforementioned audio signal generation circuit 60.
input to the set input S of 8. The operation signal generating circuit 86 also includes an AND gate 90 and a one-shot circuit 92, and the Q output signal 88a of the FF 88 is inputted to one of the AND gates 90, and the other input of the AND gate 90 is inputted from the frequency dividing circuit 4. A constant periodic signal 4b is input. The output signal 90a of the AND gate 90 is output from the audio signal generation circuit 60.
It is input to the address counter 68 inside. Also
The final output signal 9 of the octal counter 76 via the one-shot circuit 92 is connected to the reset input R of the FF88.
2a is inputting. Therefore, external switch 8
0 is turned on, a positive single pulse is generated in the output signal 84a of the one-shot circuit 84, which clears the octal counter 76 and causes the digital multiplexer 34 to output the code selected by the multiplexer 50. The signal is supplied to the audio signal generation circuit 60 as a selection signal. At the same time, the Q output signal 88a of FF88 is set to "H".
Then, the AND gate 90 is opened and the constant period signal 4b from the frequency dividing circuit 4 is supplied to the Andre counter 68. As a result, the audio signal generation circuit 60 starts operating and provides audio notification of the designated time or alarm time. When the voice notification ends, 8
A positive single pulse is generated in the output signal 92a of the one-shot circuit 92 connected to the final output of the advance counter 76, thereby inverting the Q output signal 88a of the FF 88 to "L" and closing the AND gate 90. The operation of the audio signal generation circuit 60 is stopped.

In the present invention, the time is further announced at regular intervals (in this embodiment, every hour on the hour) after a notification sound of "pitsu", and this regular announcement is synchronized with the time indicated by the external switch 80 or when the alarm time is announced. If these overlap, the start of the scheduled notification is delayed until the audio notification by the external switch 80 is finished. For this reason, in the embodiment of the present invention, a fixed time detection circuit 94 that detects whether or not the fixed time has arrived when the audio notification of the time is being made by operating the external switch 80, and When this is detected, the operation delay circuit 96 delays the start of scheduled voice notification until the voice notification ends.

FIG. 2 shows a detailed circuit diagram of the fixed time detection circuit 94 and the operation delay circuit 96 in FIG. 1.

As shown in FIG. 2, the fixed time detection circuit diagram 94 is as follows:
In this embodiment, the hour is detected,
Consists of FF98. This FF98 clock input 0
60 from minute counter 8 as shown in Figure 1.
A minute-by-minute carry signal is input via a one-shot circuit 100 and an inverter 102. Further, the output signal 100a of the one-shot circuit 100 is input to the AND gate 104 together with the 1024Hz signal 4a from the frequency divider circuit 4.
The output signal 104a is input to the sound generation circuit 22 via the OR gate 21.

On the other hand, the Q of the FF98 constituting the fixed time detection circuit 94
The output signal 98a is input to the clock input 0 of the FF 106, and the output signal 8 of the FF 88 in the operation signal generation circuit 86 is input to the reset input R of the FF 98.
8b is inputting. FF106 output signal 1
06a is input to the AND gate 112, and the output signal 106b is input to the AND gate 114, the NAND gate 110, and the reset input R of the FF108. The output signal 92a of the one-shot circuit 92 is also input to the AND gate 112.
The output signal 112a of the AND gate 112 is FF
It is input to clock input 0 of 116 and 118. Q output signal 116a of FF116 is FF118
input to the D input of FF118, and the Q output signal 11 of FF118
8a is input to clock input 0 of FF108.
The Q output signal 108a of the FF108 is the FF106,
116 and 118 and to the OR gate 120. The output signal 114a of the AND gate 114 is also input to the OR gate 120, and the output signal 120a of the OR gate 120 is input to the OR gate 120.
is input to the reset input R of the FF122.
The output signal 102a of the inverter 102 shown in FIG. Output signal 110a of NAND gate 110
is input to the AND gate 124. The AND gate 124 also contains the output signal 116b of the FF116.
The output signal 124a of the AND gate 124 is input to one of the AND gates 44 in the mode selection circuit 40. The output signal 122b of the FF 122 is also input to a timer 128 via an OR gate 126. A Q output signal 130a of the FF 130 is also input to this OR gate 126. The Q output signal 88a of the FF 88 in the operation signal generating circuit 86 is input to the clock input 0 of the FF 130, and the aforementioned output signal 92a is input to the reset input R. This output signal 92a is also input to an AND gate 114.

On the other hand, the constant period signal 4c from the frequency divider circuit 4 is input to the clock input 0 of the timer 128, and the timer 128's Q
The output signal 132a is input to the OR gate 82 together with the output signal 80a of the external switch 80.

The operation of this circuit will be explained below using time charts shown in FIGS. 3 to 5.

FIG. 3 is a time chart when the external switch 80 is operated in the designated time display mode. In this case, the mode selection circuit 40
The Q output signal 42a of the FF 42 is "L", and the output signal 44a of the AND gate 44 is also "L". Therefore, the multiplexers 30 and 32 output the minute counter 8 and the hour counter 10, and the multiplexer 50 outputs the "Tadaimaji Kokuha" code ROM.
52 outputs are selected respectively.

Here, when the external switch 80 is turned on, the output signal 80a and the output signal 82a of the OR gate 82 change from "L" to "H", and this rise activates the one shot circuit 84, and the output signal 82a changes from "L" to "H".
A positive single pulse is generated at 4a. As a result, the count contents of the octal counter 76 become the initial state, and the digital multiplexer 34 selects the signal of the "Tadaimaji Kokuha" code ROM 52 and supplies it to the start address specification ROM 64 and end address specification ROM 66 in the audio signal generation circuit 60. do. At the same time, the one shot circuit 84
Due to the positive single pulse obtained in the output signal 84a of the FF88, the Q output signal 88a of the FF88 becomes "H",
The output signal 88b becomes "L". As a result, the AND gate 90 opens and supplies the constant periodic signal 4b from the frequency divider circuit 4 to the address counter 68, thereby causing the audio signal generating circuit 6
0 produces the audio signal of "Tadaimaji Kokuha". When the sound of "Tadaimaji Kokuha" ends, a positive single pulse is generated from the signal 78a of the digital comparator 70 via the one-shot circuit 78, which causes the octal counter 76
The output signal 76a becomes "L" and the output signal 76b becomes "H". As a result, the digital multiplexer 34 selects the 10th signal of the time and sends it to the audio signal generation circuit 60.
supply to. Thereafter, a positive single pulse is generated in the output signal 78a of the one-shot circuit 78 every time the generation of the selected voice ends, whereby the output signals 76a to 76h of the octal counter 76 sequentially rise to "H".

When the output signal 76h of the octal counter 76 rises to "H" after the end of the voice notification of "Hun", a positive single pulse is obtained in the output signal 92a of the one shot circuit 92. Due to this single pulse, the Q output signal of FF88 becomes "L",
Since the output signal becomes "H", the AND gate 90 is closed and the address counter 68 is stopped. Further, the output signal 88b of the FF 88 is input to the AND gates 18 and 104, and when the output signal 88b is "L", that is, when the audio notification is being made, the alarm notification sound is generated by closing the AND gate 18. This prevents the occurrence of overlapping sound notification sounds.

FIG. 4 is a time chart of audio notification when the hour has arrived.

When the hour arrives, a positive single pulse is generated in the output signal 100a of the one-shot circuit 100, and the AND gate 104 is opened only while this pulse is rising. Therefore, 1024Hz of frequency divider circuit 4
The signal 4a is input to the sound generation circuit 22 via the AND gate 104 and the OR gate 21 for a certain period of time. As a result, a "pitsu" sound is generated at the same time that the hour has arrived.

In addition, the output signal 100 of the one-shot circuit 100
The positive single pulse on a causes inverter 102
The signal is inverted by FF 98, 122 and input to the clock input φ of FF 98, 122. However, at this time, the signal 88b input to the reset input R of the FF98 is "H", whereas the output signal 120a of the OR gate 120 input to the reset input R of the FF122 is "L". , inverter 10
FF1 by the rising edge of the output signal 102a of
The Q output signal 122a of No. 22 changes to "H", the output signal 122b changes to "L", and FF98 does not change. Therefore, the output signal 110a of the NAND gate 110 becomes "L", and thereby the output signal 124a of the AND gate 124 also becomes "L".
Therefore, the output signal 44a of the AND gate 44 in the mode selection circuit 40 becomes "L" regardless of the output state of the FF 42, thereby causing the multiplexers 30 and 32 to switch between the minute counter 8 and the hour counter 10.
The multiplexer 50 selects the signal of the "Tadaimaji Kokuha" mode ROM 52.

Also, the output signal 122b of FF122 is “L”
Therefore, the output signal 12 of the OR gate 126
6a becomes "L", and the timer 128 is released from reset and starts counting the constant period signal 4c.

Then, after a certain period of time has passed, timer 1
One-shot circuit 13 connected to the Q output of 28
A positive single pulse is obtained as the second output signal 132a. The single pulse is input to the one-shot circuit 84 via the OR gate 82, and
Activate 4. As a result, the octal counter 76 is cleared in the same manner as when the external switch 80 is operated, and the operation signal generation circuit 86 operates the audio signal generation circuit 60. As a result, the sound generating circuit 22 notifies the time counted by the hour counter 10 and the minute counter 8 by sound following the sound of "Tadaimaji Kokuha".

In this way, in this example, when it is on the hour,
A notification sound "Pitsu" is generated, and after a certain period of time, the time is announced by voice.

FIG. 5 shows a time chart when the hour arrives while the alarm time is being announced by voice.

When the alarm time is audibly announced, the Q output signal 42a of the FF 42 in the mode selection circuit 40 is "H", and accordingly, the output signal 44a of the AND gate 44 is also "H". ing. Therefore, the multiplexers 30 and 32 select the output of the set time memory 12 and the set time memory 14, and the multiplexer 50 selects the output of the "alarm alarm" code ROM 54. The Q output signal 88a of the FF 88 in the operation signal generation circuit 86 is at "H", and the constant period signal 4b from the frequency dividing circuit 4 is generated in the output signal 90a of the AND gate 90. Furthermore, the Q output signal 130 of the FF 130 in the operation delay circuit 96
a is set to "H", and the timer 128 is reset.

In this situation, when the hour arrives,
As previously mentioned, one shot circuit 100 generates a single positive pulse that is input to AND gate 104. However, in this state, the output signal 88b of the FF 88 is "L", so the AND gate 104 is in a closed state.
There was no ``pitsu'' sound like when the hour had simply arrived.

On the other hand, the positive single pulse obtained in the output signal 100a is inverted by the inverter 102 and FF
Input to clock input 0 of 98,122. By this, as explained in Fig. 4, the Q of FF122 is
The output signal 122a becomes "H", and the output signal 122a becomes "H".
b becomes "L". Also in this state FF8
Since the output signal 88b of 8 is "L", FF
The Q output signal 98a of 98 also becomes "H", and the output signal 98b also becomes "L". In this way, FF98's Q
By changing the output signal from "L" to "H"
The Q output signal 106a of the FF106 becomes "H" and the output signal 106b becomes "L". This causes AND gate 112 to open and AND gate 114 to close. In addition, the output signal of the FF 106 changes from "H" to "L" and the Q output signal of the FF 122 changes from "L" to "H", so that the output signal 110a of the NAND gate 110 maintains the "H" state, and the Output signal 124a of gate 124
In this state, since the output signal 116b of the FF 116 is also "H", it becomes "H", and the output signal 44a of the AND gate 44 in the mode selection circuit 40 maintains the "H" state. Therefore, the multiplexers 30, 32, and 50 continue to select the outputs of the set time memory 12, the set time memory 14, and the "alarm alarm" code ROM 54. Therefore, even if the hour is detected, the audio notification of the alarm time continues. Furthermore, when the audio notification of the alarm time ends in this state, the output signal 76h of the octal counter 76 rises to "H", and a positive single pulse is output to the output signal 92a of the one shot circuit 92. With this, FF88
The Q output signal 88a of the output signal 88 is "L".
b becomes "H", and the AND gate 90 is closed to stop the operation of the audio signal generation circuit 60, and the FF98
Reset.

Further, the output signal 92a is applied to the reset input R of the FF130, and the output signal 130a of the FF130 is applied to the reset input R of the FF130.
is set to "L", thereby the output signal 126a of the OR gate 126 becomes "L", and the timer 12
8 is released from reset and starts counting the constant period signal 4c.

Furthermore, the output signal 92a is inputted to the clock input 0 of FF116, 118 via AND gate 112, and the Q output signal 116a of FF116 is set to "H".
Then, the output signal 116b is set to "L". As a result, the output signal 124a of the AND gate 124 becomes "L", and the output signal 44a of the AND gate 44 in the mode selection circuit 40 becomes "L". As a result, the multiplexers 30, 32, and 50 select the outputs of the minute counter 8, hour counter 10, and "Tadaimaji Kokuha" code ROM 52, respectively.

After this, when a certain period of time has elapsed, the Q output signal 13 of the timer 128 via the one-shot circuit 132
A single positive pulse is generated at 2a, which is passed through an OR gate 82 to a one-shot circuit 84.
and operates the operation signal generation circuit 86. As a result, the audio notification of the designated time is performed in the same manner as described above.

When this voice notification of the designated time is completed, a positive single pulse is generated again in the output signal 92a of the one shot circuit 92. With the single pulse
The output signal of the FF88 is inverted to stop the operation of the audio signal generation circuit 60, and the Q output signal 118a of the FF118 is set to "H", and the output signal 11 is
Invert 8b to "L". This output signal 118a
FF1 by rising from "L" to "H"
The Q output signal 108a of 08 becomes "H", thereby causing the FFs 106, 116, 118 and 1
22. Then, the Q output signal 106a of the FF 106 becomes "L", thereby closing the AND gate 112, and the output signal 106a becomes "H".
As a result, the AND gate 114 is opened. Also, since the output signal 116b of the FF 116 becomes "H", the output signal 12 of the AND gate 124
4a becomes "H", and the output signal 44a of the AND gate 44 also becomes "H", and the multiplexer 3
0, 32 and 50 select the output for alarm time audio notification. Further, as the output signal 122b of the FF 122 becomes "H", the output signal 126a of the OR gate 126 becomes "H", thereby resetting the timer 128.

In this way, when the hour comes on the hour while the external switch 80 is turned on and the voice notification of "alarm ji koku ha 〇〇 ji Then, a voice announcement that it is on the hour is made, ``Tadaimajikokuha〇〇ji〇〇fun.'' The same operation is performed even if the hour arrives while the external switch 80 is giving voice notification of the designated time. Therefore, even if the alarm time is audibly announced over a set time, the audible announcement of the hour will always be made, and the user may not know that it is the hour because the alarm setting time is audibly announced. There will be no need to worry. Furthermore, even if the external switch 80 is operated just before the hour and the hour is reached during the audio notification of the designated time, and the notification time and the designated time are different, the audio notification that it is on the hour will not be made afterwards. The user can hear the exact time on the hour.

In the present embodiment, a watch has been described in which the designated time and alarm time are notified audibly by operating the external switch 80. It is also possible to apply the present invention to.

As described above, according to the present invention, when the fixed time for which the time should be forcibly announced while the audio notification of the time is being performed by operating the external switch, the audio notification of the time at the scheduled time is started. of,
By delaying the voice notification by the external switch until it is finished, the scheduled voice notification is prevented from being blocked by the operation of the external switch, and the user can accurately hear the scheduled voice notification.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. FIG. 2 is a circuit diagram showing a fixed time detection circuit and an operation delay circuit in FIG. 1. FIG. 3 is a time chart showing the operation when the external switch is operated in FIGS. 1 and 2. FIG. 4 is a time chart showing the operation when the scheduled time arrives in FIGS. 1 and 2. Figure 5 shows that in Figures 1 and 2,
FIG. 7 is a time chart diagram showing operations when the scheduled time arrives during audio notification. 22... Sound generation circuit, 60... Audio signal generation circuit,
80...External switch, 94...Periodical detection circuit, 96
...Operation delay circuit.

Claims (1)

[Claims] 1. A reference signal generator that generates a reference signal, a frequency dividing circuit that divides the frequency of this reference signal, a counter that counts a designated time using the frequency divided signal from this frequency dividing circuit, and an alarm time. a matching circuit that detects a match between the contents of the counter and the setting time memory, and an alarm signal generating circuit that generates an alarm notification sound signal based on the output signals from the matching circuit and the frequency dividing circuit. an external switch for mode selection; a first multiplexer into which count signals from the counter and the set time memory are input, and which selects and outputs one of the count signals by operating the mode selection switch; and an audio start. an OR gate that receives an operation signal from the audio start switch and a constant periodic signal generated from a counter at regular intervals and outputs a notification start signal; and an OR gate that receives a count signal from the first multiplexer and outputs a notification start signal. an audio selection circuit that sequentially selects and outputs a count signal one digit from the beginning for each time digit in response to the operation, and outputs a termination signal when all the time digits have been selected and output; an audio signal generation circuit that converts a time digit signal into an audio signal; a sound generation circuit that generates a sound in response to an alarm notification signal from the audio signal generation circuit and the alarm signal formation circuit; an audio operation circuit that operates the audio signal generation circuit until a termination signal is generated from the audio selection circuit; and an audio operation circuit that is connected to the audio operation circuit and the counter and operates the audio signal generation circuit while the audio signal generation circuit is operating. a periodic detection circuit that detects the generation of a constant periodic signal from the counter; and a periodic detection circuit that stores the output signal from this periodic detection circuit, and then selects a mode in response to the generation of the first termination signal from the audio selection circuit. outputting a fixed signal and, after a certain period of time has elapsed, causing the OR gate to output a signal for outputting a notification start signal in place of the fixed periodic signal from the counter; an operation delay circuit that releases the memory of the output signal from the operation delay circuit and stops outputting the mode-fixed signal; and an operation delay circuit that is connected between the mode selection switch and the first multiplexer and that generates the mode-fixed signal from the operation delay circuit. An audio timepiece comprising: a mode selection circuit that sometimes supplies a signal to the first multiplexer to selectively output the count signal of the counter regardless of the operation of the mode selection switch.