JPH0346791B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timepiece equipped with a sound generating device, and particularly to a timepiece that notifies the time and other information during timekeeping.

In general, when timing a watch, especially an all-electronic watch that uses an optical display, there is a problem in that if the timing is set at high speed, the display cannot follow the timing, making it impossible to confirm the timing details. Also, as a matter of course, one must visually concentrate on the display while adjusting the timing. If one is distracted by surrounding circumstances or has to set the time in a dimly lit place, the desired time setting time may end up being missed.

SUMMARY OF THE INVENTION Therefore, the present invention provides a timepiece equipped with a sound generating device that notifies the contents of the counter during time adjustment by voice, and allows the user to directly hear and confirm the contents of the time adjustment being changed.

An embodiment of the present invention will be described below based on the drawings. 1 is a crystal oscillator, 2 is a frequency divider, and 3 is a pulse generation circuit that generates pulses in response to manual rotation operation. 4 is a timer, which generates a pulse output when counting, for example, 5 seconds. 5 to 8 are each 1/1
This is a counter that measures digits, two digits, hours, and morning and afternoon. Numerals 9 to 12 are latch circuits that temporarily store the outputs of the respective counters, and 13 is a speech synthesizer, which generates the contents as an audio signal when a predetermined data is input, and is mainly a read-only memory ( It consists of integrated circuits such as ROM). The speech synthesizer is a known one, and its details will be omitted. A code converter 14 converts the outputs of the counters 5 to 8 into codes suitable for the input of the speech synthesizer 13. Reference numeral 15 denotes a speaker, which emits the content of input data according to the audio signal from the audio synthesizer 13. For the purpose of the following explanation, the terminal 13a of the speech synthesizer 13 has a logic value of "0" while the speech signal is being generated (hereinafter, the logic values will be simply referred to as "0" and "1"), and is stopped. "1" shall be generated during the interval. Also, terminal 1
When 3b is held at "1", input data is converted into an audio signal. 16 is a timing pulse generation circuit, 17 to 20 are delay type flip-flop circuits, 21 is a detection circuit consisting of a counter, etc.
The period of the pulse generated from the pulse generation circuit 3 is set to 3.
Detection is performed in stages, and time t ₁ < time
t ₂ , when the pulse period t is t≦t ₁ , it is applied to terminal a, when t ₁ < t≦t _2, it is applied to terminal b, and when t ₂ < t
When , "1" is generated at terminal c. 22-25 are S
-R flip-flop circuit; 26 to 28 are differentiating circuits; 29 to 55 are gate circuits; 56 is an inverter;
57 is a manual switch, and 58 to 61 are gate circuits.

Next, the operation will be explained. When the switch 57 is closed, the gate circuits 38, 58 and 60 are open, and the 1 minute signal from the frequency divider 2 is passed through the gate circuits 38 and 39 to the counter 5.
is supplied to the clock, and one-digit minute timekeeping is performed. Thereafter, the counter 6 measures the two digits of the minutes, the counter 7 measures the hour digits, and the counter 8 measures the morning and afternoon times.
In this way, normal time is measured.

If the switch 57 is opened in this state, timing can be adjusted. That is, gate circuits 38 and 60 are closed, and since terminal 13a is held at "1", gate circuit 36 is opened. On the other hand, as the switch opens, a single pulse is generated from the differentiating circuit 28, and is passed through the gate circuit 31 and each gate circuit 45 to 48 to the flip-flop circuit 28.
Set 2 to 25. Further, the output pulse of gate circuit 31 becomes a clock input of flip-flop circuit 20 via gate circuits 37 and 32.
Here, the gate circuit 33 assumes that the output terminal Q of the flip-flop circuit 18 is "0" and that the voice synthesizer 13
Since the terminal 13a of is "1", an output "1" is generated. Therefore, when the above clock is input, the output terminal Q of the flip-flop circuit 20 becomes "1", and the input to the gate circuit 32 is prohibited. Further, the output of the gate circuit 34 also becomes "1", which becomes the clock input of the timing pulse generation circuit 16, and generates a pulse at the output terminal _Q1 . On the other hand, since the high frequency pulse φ ₁ is applied to the clock input of the flip-flop circuit 18, after the input D becomes "1", the output terminal Q is inverted to "1". Since the flip-flop circuit 19 also receives the pulse _φ1 as a clock input, after the output terminal Q of the flip-flop circuit 18 is inverted to "1", the output terminal Q of the flip-flop circuit 19 is inverted to "0". Now, when the output terminal Q of the flip-flop circuit 18 becomes "1", the output of the gate circuit 33 becomes "0", and therefore the gate circuit 34
When the output of the flip-flop circuit 18 becomes "0" and the pulse φ ₁ is supplied, the output terminal Q of the flip-flop circuit 18 becomes "0". As a result, the output of the gate circuit 33 becomes "1" again, and therefore the output of the gate circuit 34 becomes "1", and the timing pulse generation circuit 16
At the same time as the pulse at output terminal Q ₁ stops, a pulse is generated at output terminal Q ₂ . On the other hand, the output terminal Q of the flip-flop circuit 18 is again inverted to "1", and the output terminal of the flip-flop circuit 19 is inverted to "0". By repeating such operations, a pulse is generated at the output terminal of the gate circuit 34 in synchronization with the pulse φ ₁ , and timing pulses are sequentially generated at the output terminals Q ₃ and Q ₄ of the timing pulse generation circuit 16. When a pulse is generated from output terminal _Q5 , flip-flop circuit 20, timing pulse generation circuit 16, and flip-flop circuits 22-25 are reset.
As described above, each time a pulse is applied to the clock input of the flip-flop circuit 20, the timing pulse generating circuit 16 generates one cycle of timing pulses.

Now, the switch 57 is opened, the flip-flop circuits 22 to 25 are set as described above, and the pulse generated at the output terminal _Q1 from the timing pulse generation circuit 16 causes the gate circuits 54 and 55 to be set.
When the output of the gate circuit 35 becomes "1" and the output terminals Q and of the flip-flop circuits 18 and 19 become "1", the output of the gate circuit 35 becomes "1".
become. Therefore, "1" is input to the terminal 13b of the speech synthesizer 13, and the input data being input to the speech synthesizer 13 is converted into an audio signal. The input data is the contents of counters 5-8 at the time the switch 57 was opened. That is, the pulse generated at the output terminal _Q1 of the timing pulse generating circuit 16 writes the time measurement data from the counters 5-8 into the latch circuits 9-12. In addition, the above output terminal Q ₁
When a pulse occurs, morning or afternoon clock data is passed through gate circuits 43 and 44 and converted by code converter 14 into a code suitable for speech synthesizer 13. The converted clock data is converted into an audio signal by the audio synthesizer 13, and the content thereof is outputted by the speaker 15.

Next, the output terminal of the timing pulse generation circuit 16
When a pulse is generated at Q ₂ , the gate circuit 42 is opened and the clock data of the hour digit is sent to the gate circuits 42 and 44.
and a speech synthesizer 13 via a code converter 14
is input. The content is converted into an audio signal,
The content is voiced from the speaker 15. Thereafter, as pulses are sequentially generated at the output terminals Q ₃ and Q ₄ of the timing pulse generation circuit 16, the gate circuits 41 and 40 are opened, and data of two digits and one digit of minutes are sequentially sent to the speech synthesizer 13. entered,
The content is voiced from the speaker 15.

Output terminal Q ₅ of timing pulse generation circuit 16
When a pulse is generated, flip-flop circuits 20, 22-25 and timing pulse generating circuit 16 are reset as described above. Therefore, the outputs of gate circuits 51 to 54 are held at "0". Furthermore, when the audio signal from the audio synthesizer 13 stops, the output of the terminal 13a becomes "1", so one input of the gate circuit 33 is also held at that value.

The operations during timing are as follows. When the pulse generating circuit 3 generates a pulse in the open state of the switch 57 described above, a pulse corresponding to one period of the above pulse is generated at the output terminal Q of the flip-flop circuit 17, and during this period, the output terminal of the frequency divider 2 The pulse supplied from φ ₂ passes through the gate circuit 30 and is input to the detection circuit 21 . Now, if the pulse generating circuit 3 generates a short-period pulse, "1" is generated at the terminal a of the detecting circuit 21,
The contents of counter 7 are incremented by 1 and counters 5 and 6 are reset. Further, the output "1" of the terminal a sets the flip-flop circuit 23 via the gate circuit 46, and also sets the flip-flop circuit 23 through the gate circuit 46.
9 and 50, respectively, to reset flip-flop circuits 24 and 25. Gate circuits 51 and 52 are therefore closed and gate circuit 53 is opened. Here, the gate circuit 54 is closed by the output of the output terminal Q of the flip-flop circuit 22, which has been reset by the pulse generated at the output terminal _Q5 of the timing pulse generating circuit 16. When a pulse is generated at the output terminal _Q1 of the timing pulse generation circuit 16, the counters 5 to
The clock data of No. 8 is transferred to latch circuits 9-12. When a pulse is generated at the output terminal _Q2 of the timing pulse generation circuit 16, the gate circuit 42 is opened, and the timing data stored in the latch circuit 11 passes through it, and the gate circuit 44 and the code The signal is input to the speech synthesizer 13 via the converter 14. On the other hand, the above pulse generated at the output terminal _Q2 of the timing pulse generation circuit 16 generates a pulse at the output terminal 13b via the gate circuits 53, 55 and 35. Therefore, the content of the previous time is converted into an audio signal by the audio synthesizer 13,
The content is voiced from the speaker 15.

Next, when the period of the pulse generated in the pulse generation circuit 3 becomes longer than in the previous example and the output of the terminal b of the detection circuit 21 becomes "1", the counter 5 is reset and the contents of the counter 6 are It can be advanced by “1”. Also, flip-flop circuit 24 is set and flip-flop circuit 25 is reset. Therefore, only the gate circuit 52 is opened, and when a pulse is generated at the output terminal _Q3 of the timing pulse generating circuit 16, the two-digit content of the latch circuit 10 is sounded from the speaker 15.

If the period of the pulse generated in the pulse generation circuit 3 is longer, "1" is generated at the output terminal c of the detection circuit 21, the contents of the counter 5 are incremented by 1, and the flip-flop circuit 25 is set.
Therefore, when a pulse is generated at the output terminal _Q1 of the timing pulse generating circuit 16, the one-digit content stored in the latch circuit 9 is output from the speaker 15.

By the way, when a carry signal is generated in the counter 7, the contents of the counter 8 for morning and afternoon are also uttered. If a carry signal now occurs, it sets the flip-flop circuit 22 through the gate circuit 45. Therefore, the gate circuit 54 is opened and the contents of AM or PM are uttered from the speaker 15.

In this example, while sound is being generated from the speaker 15, that is, the output terminal 13a of the speech synthesizer 13
While is "0", the gate circuit 36 is closed and generation of pulses at its output terminal is prohibited.

When the pulses from the pulse generation circuit 3 are stopped for a certain period of time due to the end of time adjustment, etc., the following operation is performed. When the generation of pulses stops, the reset of the timer 4 is released, and the counting of the pulse φ ₃ supplied from the frequency divider 2 is continued. After a certain period of time, for example, 5 seconds, an output is generated from the timer 4, and the gate is activated. Flip-flop circuits 22-25 are set via circuits 31 and 45-48. Therefore, the gate circuits 51 to 54 are opened, and the operating state is the same as that when the switch 57 is opened, as described above, and the contents of the counters 5 to 8 are sequentially uttered from the speaker 15.

As described in detail above, according to the present invention, one of the plurality of counters is selectively timed according to the period of the timing pulse, and the contents of the counter are audibly notified and the counters of the previous stage are Since the timing digit can be selected according to the speed of the timing pulse, and only that digit is audibly announced, it is possible to check the timing contents in a short time regardless of the surrounding brightness. This can be done quickly and reliably to set the time.

Furthermore, with the timing of the counter of the desired stage,
In order to reset the counters before the timed counter, when the time is set in order from the high-order digits,
Since the digit to be timed has been reset in advance, it will always be incremented from the reset value, and you will have a rough idea of how long it will take to reach the desired value, and you will be able to see if it passes the desired value. The risk of leakage can be minimized.

In addition, after the timing pulse has stopped for a certain period of time, the contents of the counters at each stage are sequentially announced by voice, so the end of timing is automatically detected and the time after timing is read back. This allows you to reconfirm the timing details.

[Brief explanation of drawings]

The drawings are electrical circuit diagrams including block diagrams illustrating one embodiment of the present invention. 2...Frequency divider, 3...Pulse generation circuit, 5-8
...Counter, 9-12...Latch circuit, 13...
...Speech synthesizer, 14...Code converter, 15...
Speaker, 16...timing pulse generation circuit.

Claims (1)

[Claims] 1. A multi-stage counter that measures time based on a time signal, a timing pulse generating means that generates a timing pulse with a variable generation cycle, and a plurality of counters that measure time based on a time signal; a timing means for selectively timing one of the stages of counters; a reset means for resetting a counter in a lower stage than the counter timed by the timing means; What is claimed is: 1. A timepiece equipped with a sound generating device, characterized in that it comprises a sound synthesizing means for audibly reporting the contents of a timed counter. 2. A multi-stage counter that measures time based on a time signal, a timing pulse generation means that generates a timing pulse with a variable generation cycle, and one of the multiple-stage counters according to the cycle of the timing pulse. a timing means for selectively timing the stages; a reset means for resetting counters in stages lower than the counter timed by the timing means; comprising a timer circuit that generates an output when the timer has stopped for a certain period of time or more, and a control means that uses the output of the timer circuit to sequentially supply the contents of the counters in each stage to the voice synthesizing means to generate a voice alarm. A watch equipped with a sound generating device characterized by: