JPS6224969B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an alarm circuit in a PLL (phase locked loop) circuit that detects an abnormal state in the PLL circuit and generates an alarm.

In an AFC (automatic frequency control) circuit using a PLL circuit, it is common to detect an abnormal state, generate an alarm, and switch between working and standby circuits.
In this case, abnormal conditions are detected by comparing the DC component obtained by integrating the output pulses of the phase comparator of the PLL circuit with a reference voltage.

For example, if the reference frequency signal is as shown in Figure 1a, the output pulse of the phase comparator in the case of a lagging phase is as shown in Figure 1b, and the output pulse of the phase comparator in the case of an advanced phase is as shown in Figure 1c. Become. This type of output pulse with a delayed phase or an output pulse with an advanced phase is integrated by an active filter, etc.
As shown in the figure, the reference frequency signal and the output signal of the voltage controlled oscillator VCO are applied to the phase comparator PC, their phases are compared, and the comparison output is sent to the voltage controlled oscillator VCO via the low frequency filter LPF. The voltage controlled oscillator VCO generates an output signal synchronized with the phase of the reference frequency signal. The output pulse of the phase comparator PC is integrated by the active filter AF, amplified by the amplifier AMP, and then applied to the comparators COMP1 and COMP2, and compared with the reference voltages Vr ₁ and Vr ₂ , respectively. OR circuit OR when the other reference voltage is lower than the other reference voltage.
An alarm signal arm will be output via.

As mentioned above, in the conventional alarm circuit, an amplifier AMP is used to increase sensitivity, and a comparator is used to detect overly advanced phase and overly delayed phase.
Since COMP 1 and COMP 2 must be provided and each of them must be configured with an analog circuit, the configuration becomes complicated in order to solve problems such as drift, and there is also the disadvantage that there are many adjustment points.

The present invention improves the above-mentioned conventional drawbacks by digitally processing the output pulses of the phase comparator, detecting when the phase is out of a predetermined range, and generating an alarm. The purpose of this is to provide a configuration that operates stably. Examples will be described in detail below.

FIG. 3 is a block diagram of an embodiment of the present invention, in which the phase of the reference frequency signal and the phase of the controlled frequency signal are compared by the phase comparator PC, and the output pulses are sent to the reference pulse generating circuits PG1, PG2 and It is added to the phase determination circuit P, and the phase determination circuit P determines whether the phase is an advanced phase or a delayed phase, and in the case of an advanced phase, the standard from the reference pulse generation circuit PG1 is added to the advanced phase determination circuit P1. Based on the pulse, it is determined whether the phase is advanced within a predetermined range or not, and if the phase is delayed, the delayed phase determination circuit P2
At this point, it is determined whether the delayed phase is within a predetermined range based on the reference pulse from the reference pulse generating circuit PG2, and if it is not within the predetermined range, an alarm signal arm is outputted via the OR circuit OR.

FIG. 4 is a block diagram of an embodiment of the present invention constructed using D flip-flops.
FF3 is a D flip-flop, INV1 to INV4 are inverters, N1 to N3 are NAND gates, C1,
C2 is a capacitor, and R1 to R3 are resistors. The phase comparator PC compares the reference frequency signal a and the controlled frequency signal A, outputs a pulse output signal with a pulse width corresponding to the phase difference, which is inverted by the inverter INV2, and the inverted signal c is sent to the flip-flops FF1 to FF1. Added to FF3. These flip-flops FF1 to FF3 are all reset as initial conditions.

Further, the reference frequency signal a is differentiated and waveform-shaped by a circuit consisting of a capacitor C1, resistors R1 and R2, and an inverter INV3, and is applied as a reference pulse signal d to the D terminal of the flip-flop FF2. Further, the reference frequency signal a is a NAND gate N1,
N2, resistor R3, capacitor C2 and inverter
The circuit consisting of INV4 integrates and shapes the waveform and outputs it to the flip-flop FF as a reference pulse signal e.
It is added to the C terminal of 3.

The D terminal of the flip-flop FF1 receives a signal b obtained by inverting the reference frequency signal a by the inverter INV1.
is applied, and when the signal b is "1" at the rising edge of the signal c applied to the C terminal, the flip-flop FF1 is in the set state and the output from the Q terminal becomes "1".

Fig. 5 shows an example of the waveforms of signals a to e in each part of Fig. 4, corresponding to a to e, where c in Fig. 5 shows the case of a delayed phase, and c' shows the case of an advanced phase. . Therefore, in the case of delayed phase, flip-flop FF1
is not set, and the terminal output becomes "1", and this terminal output is applied to the R terminal of flip-flop FF3, so that flip-flop FF3 becomes in a reset state. In addition, in the case of an advanced phase, flip-flop FF1 is set, the Q terminal output becomes "1", and this Q terminal output is output to flip-flop FF2.
The flip-flop FF2 is put into a reset state. That is, flip-flop FF
By setting and resetting 1, the phase is determined as to whether it is an advanced phase or a delayed phase. In the case of an advanced phase, the flip-flop FF2 continues to be in a reset state by the Q terminal output, and the terminal output is always "1". In the case of a delayed phase, the flip-flop FF3 continues to be in the reset state, and its terminal output is always "1".

If flip-flops FF2 and FF3 are in the reset state, the alarm signal arm output from the NAND gate N3 is "0", indicating a normal state. Furthermore, when either flip-flop FF2 or FF3 is set, the alarm signal arm becomes "1", which can indicate the occurrence of an abnormality. In that case, when flip-flop FF2 is set, the lagging phase signal LG becomes "1", and when flip-flop FF3 is set, the leading phase signal LD becomes "1", and the alarm signal arm is set as the leading phase or as the lagging phase. It turns out that this is what happened.

For example, in the case of the delayed phase signal c shown in FIG. 5c, since the signal b is "0" at the time of its rise, the flip-flop FF1 is not set. Since the reference pulse signal d is "0" at the rising edge of the signal c, the flip-flop FF2 is also not set. Therefore, the alarm signal arm is "0".
If the delayed phase is large and the signal c becomes as shown by the dotted line, the reference pulse signal d is "1" at the time of the rise of the signal c, so the flip-flop FF
2 is set, the delayed phase signal LG and the alarm signal
arm becomes “1”, and due to an abnormality in the PLL circuit,
This indicates that the phase delay of the controlled frequency signal A with respect to the reference frequency signal a has become larger than a predetermined range.

Furthermore, in the case of the leading phase shown in c' in FIG. 5, since the signal b is "1" at the time of its rise, the flip-flop FF1 is set, and the reference pulse signal e
Since the signal c' is "0" at the rising edge of the signal c', the flip-flop FF3 is not set. However, when the leading phase becomes large and a signal c' as shown by the dotted line is obtained, since the signal c' is "1" at the rising edge of the reference pulse signal e, the flip-flop FF3 is set, and the leading phase signal LD and the alarm signal arm becomes "1", indicating an abnormal state in which the phase lead has exceeded a predetermined range.

As mentioned above, the pulse width of the reference pulse signals d, e is compared with the pulse width of the phase comparison output pulse signal from the phase comparator PC as a pulse width in a predetermined delay or advance phase range, and the pulse width of the reference pulse signals d, e is compared with the pulse width of the phase comparison output pulse signal from the phase comparator PC. If it is within the pulse width, it is determined to be normal, and the flip-flop FF2 corresponds to the delayed phase determination circuit P2 in FIG.
3 corresponds to the leading phase determining circuit P1 in FIG.

As explained above, the present invention provides a phase comparator
Means consisting of reference pulse generation circuits PG1, PG2, etc. that generate a reference pulse signal of a constant pulse width from a reference frequency signal used as a reference for the phase comparator in the PC, and a means in which the output pulse signal of the phase comparator PC advances in phase. and a phase comparator based on the determination result of this phase determination circuit P.
Comprising an advanced phase determination circuit P1 and a delayed phase determination circuit P2 that compare and determine the output pulse signal of the PC and the reference pulse signal, the phase difference of the controlled frequency signal A with respect to the reference frequency signal a is greater than or equal to a predetermined range. In this case, it determines that the phase is out of synchronization or an abnormal state close to it and generates an alarm signal arm.Since the processing is done digitally, the circuit configuration is simple and stable operation is possible. There are advantages that can be achieved.

Regarding the output pulse signal of the phase comparator PC,
It is determined whether the phase is a leading phase or a lagging phase, and if the phase is leading, the leading phase determining circuit P1 determines, and if the phase is lagging, the determining circuit P2 is used to determine the delayed phase, so there is less possibility of a determination error occurring. , reliability can be improved.

[Brief explanation of the drawing]

Figure 1 is a waveform diagram for explaining the operation of the phase comparator, Figure 2 is a waveform diagram for explaining the operation of the phase comparator.
3 is a block diagram of a conventional alarm circuit, FIG. 3 is a block diagram of an embodiment of the present invention, FIG. 4 is a block diagram of an embodiment of the present invention using a D flip-flop, and FIG. FIG. 3 is a waveform diagram of an example of signals of each part in the figure. PC is a phase comparator, FF1 to FF3 are flip-flops, INV1 to INV4 are inverters, N1 to N
3 is Nand Gate.

Claims (1)

[Claims] 1 In an alarm circuit that generates an alarm when the phase difference output in the phase comparator of the PLL circuit is above or below a predetermined value, means for creating a reference pulse signal of pulse width; a phase determination circuit for determining whether the output pulse signal of the phase comparator is an advanced phase or a delayed phase; and a phase determination circuit that operates based on the determination result of the phase determination circuit to 1. An alarm circuit in a PLL circuit, comprising an advanced phase determination circuit and a delayed phase determination circuit for comparing an output pulse signal of a comparator and the reference pulse signal.