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JPH0459809B2 - - Google Patents
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JPH0459809B2 - - Google Patents

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Publication number
JPH0459809B2
JPH0459809B2 JP57177207A JP17720782A JPH0459809B2 JP H0459809 B2 JPH0459809 B2 JP H0459809B2 JP 57177207 A JP57177207 A JP 57177207A JP 17720782 A JP17720782 A JP 17720782A JP H0459809 B2 JPH0459809 B2 JP H0459809B2
Authority
JP
Japan
Prior art keywords
frequency
output
phase comparator
input signal
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57177207A
Other languages
Japanese (ja)
Other versions
JPS5966229A (en
Inventor
Tsuneo Hirose
Shinichi Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57177207A priority Critical patent/JPS5966229A/en
Publication of JPS5966229A publication Critical patent/JPS5966229A/en
Publication of JPH0459809B2 publication Critical patent/JPH0459809B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/14Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は入力信号に異常が生じた時にも正確に
出力信号を出すようにした位相ロツクループ回路
(以下、PLL回路と称す)に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a phase lock loop circuit (hereinafter referred to as a PLL circuit) that accurately outputs an output signal even when an abnormality occurs in an input signal.

従来例の構成とその問題点 従来から位相ロツクループ(PLL)技術が広
く用いられている。位相ロツクループは、本来入
力周波数の高周波のジツタ成分を除去するもので
ある。従つて、多少の入力信号の異常に対しても
出力信号は急激に変化しない特性を有する。
Conventional configuration and its problems Phase lock loop (PLL) technology has been widely used in the past. The phase lock loop originally removes high frequency jitter components of the input frequency. Therefore, the output signal has a characteristic that the output signal does not change suddenly even if there is some abnormality in the input signal.

近年、記録媒体から信号を抽出する時に信号か
らクロツクを抽出し、このクロツクでもつて情報
信号を読み取る、いわゆるセルフクロツク抽出に
PLL技術が用いられている。このような場合に
は、非常に正確なクロツク抽出が行なわれなけれ
ば情報に大きなバーストエラーを付加してしま
う。
In recent years, when extracting a signal from a recording medium, a clock is extracted from the signal, and this clock is used to read the information signal, so-called self-clock extraction.
PLL technology is used. In such a case, a large burst error will be added to the information unless very accurate clock extraction is performed.

このように、近年、PLL回路も高性能なもの
が要求されている。
In this way, in recent years, high performance PLL circuits have been required.

第1図に基本的なPLL回路の一例を示す。第
1図において、1は入力信号iと出力信号pの位
相を比較する位相比較器であり、その出力は増幅
器2に接続され、増幅器2の出力は電圧−周波数
変換器である電圧制御型発振器3を制御する。こ
の電圧制御型発振器の出力がPLL回路の出力で
あり、この出力はまた位相比較器1にフイードバ
ツクされている。
Figure 1 shows an example of a basic PLL circuit. In Figure 1, 1 is a phase comparator that compares the phases of input signal i and output signal p , the output of which is connected to amplifier 2, and the output of amplifier 2 is a voltage-controlled oscillator that is a voltage-frequency converter. Control 3. The output of this voltage controlled oscillator is the output of the PLL circuit, and this output is also fed back to the phase comparator 1.

第2図は増幅器2の周波数特性図である。 FIG. 2 is a frequency characteristic diagram of the amplifier 2.

増幅器2は第2図に示すように、一般にローパ
スフイルタとなつている。系の開ループ利得をG
とすると、oがゲイン交点周波数である。oは系
の応答速度を決定する。これは、入力信号のジツ
タを除去するために入力周波数よりも十分低く選
ばれる。しかし、あまり低くすると、系の応答速
度が低くなつてしまう。例えば、高密度記録媒体
では入力信号の周波数は1MHz程度であり、一方、
高速アドレスサーチ等の必要からoは1KHz以上
に選ばれる。即ち、oには上述のような制限が加
えられ、自由に決定できない。o=1KHzとした
時、第1図において、入力信号iに異常が起こつ
た場合を考える。なお、入力信号のiの変動周波
数は5〜30Hz程度の場合が多い。例えば、この変
動周波数を10Hzとする。
As shown in FIG. 2, the amplifier 2 is generally a low-pass filter. The open loop gain of the system is G
Then, o is the gain intersection frequency. o determines the response speed of the system. This is chosen sufficiently lower than the input frequency to remove jitter in the input signal. However, if it is too low, the response speed of the system will become low. For example, in high-density recording media, the frequency of the input signal is about 1MHz;
Due to the need for high-speed address search, etc., o is selected to be 1KHz or higher. In other words, o is subject to the above-mentioned restrictions and cannot be freely determined. Let us consider the case where an abnormality occurs in the input signal i in Fig. 1 when o = 1KHz. Note that the fluctuation frequency of the input signal i is often about 5 to 30 Hz. For example, let this fluctuating frequency be 10Hz.

第3図は、入力信号iに雑音等の異常がない場
合の位相比較器1の出力である。入力信号iの変
動周波数が10Hzであるから、この位相比較器の出
力の基本周波数は10Hzである。
FIG. 3 shows the output of the phase comparator 1 when there is no abnormality such as noise in the input signal i . Since the fluctuation frequency of the input signal i is 10 Hz, the fundamental frequency of the output of this phase comparator is 10 Hz.

しかし、入力信号に異常が発生すると、位相比
較器の出力は第4図の42のように大きく乱れ
る。系のゲイン交点周波数は1KHzであり、変動
周波数10Hzより十分大きいから、この間に電圧制
御型発振器3の出力周波数は大きくずれてしま
う。このような異常を検出して、第4図の破線4
4のように補間できればよい。もし、oを変動周
波数10Hzに合わすことができれば、このような補
間が可能である。しかし、oは前述したように系
の応答から、そのような低い値に設定できない。
However, if an abnormality occurs in the input signal, the output of the phase comparator will be greatly disturbed as shown at 42 in FIG. Since the gain intersection frequency of the system is 1 KHz, which is sufficiently higher than the fluctuation frequency of 10 Hz, the output frequency of the voltage-controlled oscillator 3 deviates significantly during this period. By detecting such an abnormality, the dashed line 4 in Fig.
It is sufficient if interpolation can be performed as in 4. If o can be made to match the fluctuating frequency of 10Hz, such interpolation is possible. However, as mentioned above, due to the response of the system, o cannot be set to such a low value.

発明の目的 本発明は、上述のように入力信号に異常が起こ
つた時も出力信号に異常が現われないようにした
PLL回路を提供することを目的とする。
Purpose of the Invention The present invention prevents abnormalities from appearing in the output signal even when an abnormality occurs in the input signal as described above.
The purpose is to provide a PLL circuit.

発明の構成 本発明は、入力信号と出力信号の位相を比較す
る位相比較器と、共振周波数が入力周波数の変動
成分とほぼ一致した共振をもち、かつローパスフ
イルタの特性を有する共振回路と、前記共振回路
の出力に応じて発振周波数が制御される発振器と
を具備して構成したものである。なお、発振器に
は一般に電圧制御型発振器が用いられる。
Structure of the Invention The present invention provides a phase comparator that compares the phases of an input signal and an output signal, a resonant circuit having a resonance whose resonant frequency almost matches a fluctuation component of the input frequency, and having characteristics of a low-pass filter; The oscillator has an oscillator whose oscillation frequency is controlled according to the output of the resonant circuit. Note that a voltage controlled oscillator is generally used as the oscillator.

実施例の説明 以下、本発明の実施例を図面に基いて説明す
る。第5図は本発明の一実施例のブロツク図を示
し、第1図で説明したものと同様の部分は同一の
符号を付している。この第5図において、位相比
較器1はループスイツチ51の入力側に接続さ
れ、かつ、その出力端は位相異常検出器52に接
続されている。ループスイツチ51の出力端は共
振回路53に接続され、その出力は電圧制御型発
振器3を制御する。
DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described based on the drawings. FIG. 5 shows a block diagram of an embodiment of the present invention, and parts similar to those described in FIG. 1 are designated by the same reference numerals. In FIG. 5, the phase comparator 1 is connected to the input side of a loop switch 51, and its output end is connected to a phase abnormality detector 52. The output end of the loop switch 51 is connected to a resonant circuit 53, and its output controls the voltage controlled oscillator 3.

共振回路53は第6図に示すような2次系のロ
ーパスフイルタとする。この共振周波数pを入力
信号の変動成分周波数にほぼ一致させる。ループ
が閉じている時の系の応答周波数はゲイン交点周
波数oで決まる。今、第4図aのような異常が位
相比較器1の出力に現われると、位相異常検出器
52で異常を検出し、この出力で異常区間、ルー
プスイツチ51を開とし、ループを切断する。開
ループ時の系の共振は、共振回路53のpになる
から、共進回路53の出力は入力信号の変動成分
周波数と丁度一致して変化する。従つて、共振回
路53の出力は第4図aの曲線44のように変化
するので、電圧制御型発振器3の出力はほとんど
傷がない場合と同じように変化する。
The resonant circuit 53 is a secondary low-pass filter as shown in FIG. This resonant frequency p is made to approximately match the fluctuating component frequency of the input signal. The response frequency of the system when the loop is closed is determined by the gain intersection frequency o . Now, when an abnormality as shown in FIG. 4a appears in the output of the phase comparator 1, the phase abnormality detector 52 detects the abnormality, and this output opens the loop switch 51 during the abnormal section to disconnect the loop. Since the resonance of the system in open loop is p of the resonant circuit 53, the output of the co-progressor circuit 53 changes exactly in accordance with the fluctuating component frequency of the input signal. Therefore, the output of the resonant circuit 53 changes as shown by the curve 44 in FIG.

次に、第4図bに極めて長い時間に渡る異常が
位相比較器1の出力に現れた時の動作を示す。こ
のような場合にも、共振回路53の共振周波数が
入力成分の変動成分周波数に一致しているため電
圧制御発振器3の出力はほとんど傷がない場合と
同様に変化する。
Next, FIG. 4b shows the operation when an abnormality that lasts for an extremely long time appears in the output of the phase comparator 1. Even in such a case, since the resonant frequency of the resonant circuit 53 matches the fluctuating component frequency of the input component, the output of the voltage controlled oscillator 3 changes in the same way as in the case where there is almost no flaw.

これに対し、単なる異常前の状態を保持する場
合は、異常区間を単に直線的に補間するにすぎ
ず、本発明のように変動周波数に対して正弦波状
に補間することが出来ない。
On the other hand, when simply maintaining the state before the abnormality, the abnormal section is simply interpolated linearly, and it is not possible to interpolate sinusoidally with respect to the fluctuating frequency as in the present invention.

第7図は、本発明の他の実施例を示すブロツク
図である。この第7図において、第4図で説明し
たものと同様のものは同一の符号を付している。
第7図においては第6図の共振回路53の代りに
縦続接続した1次のローパスフイルタ61と2次
のバンドパスフイルタ62からなる共振回路5
3′を用いている。第8図の曲線81が1次のロ
ーパスフイルタ61の特性であり、曲線82が2
次の共振回路の特性である。この2次のバンドパ
スフイルタの共振周波数を入力信号の変動成分の
周波数に合わせておくと、ほぼ第6図の場合と同
様の動作をする。
FIG. 7 is a block diagram showing another embodiment of the present invention. In FIG. 7, parts similar to those explained in FIG. 4 are designated by the same reference numerals.
In FIG. 7, a resonant circuit 5 consisting of a first-order low-pass filter 61 and a second-order band-pass filter 62 connected in cascade instead of the resonant circuit 53 of FIG.
3' is used. A curve 81 in FIG. 8 is the characteristic of the first-order low-pass filter 61, and a curve 82 is the characteristic of the second-order low-pass filter 61.
The following are the characteristics of the resonant circuit. If the resonant frequency of this secondary bandpass filter is matched to the frequency of the fluctuating component of the input signal, the operation will be similar to that shown in FIG. 6.

発明の効果 以上のように本発明は非常に簡単な構成で、極
めて長時間の異常時にも、入力成分の変動に極め
て正確に発振周波数を入力信号の変動周波数成分
に追随させることができるものである。
Effects of the Invention As described above, the present invention has a very simple configuration, and is capable of making the oscillation frequency follow the fluctuating frequency components of the input signal extremely accurately even during an extremely long-term abnormality. be.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のPLL回路の一側を示すブロツ
ク図、第2図はその増幅度対周波数特性図、第3
図および第4図は第1図のPLL回路の動作を説
明するための波形図、第5図は本発明の一実施例
を示すブロツク図、第6図は第5図の実施例の利
得対周波数特性図、第7図は本発明の他の実施例
のブロツク図、第8図は第7図の実施例の利得対
周波数特性図である。 1……位相比較器、3……電圧制御型発振器、
51……ループスイツチ、52……位相異常検出
器、53,53′……共振回路。
Figure 1 is a block diagram showing one side of a conventional PLL circuit, Figure 2 is its amplification versus frequency characteristic diagram, and Figure 3 is a diagram showing one side of a conventional PLL circuit.
5 and 4 are waveform diagrams for explaining the operation of the PLL circuit shown in FIG. 1, FIG. 5 is a block diagram showing an embodiment of the present invention, and FIG. FIG. 7 is a block diagram of another embodiment of the present invention, and FIG. 8 is a gain versus frequency characteristic diagram of the embodiment of FIG. 1... Phase comparator, 3... Voltage controlled oscillator,
51...Loop switch, 52...Phase abnormality detector, 53, 53'...Resonance circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 入力信号と出力信号の位相を比較する位相比
較器と、前記位相比較器の出力信号の所定レベル
以上の変化を検出する位相異常検出器と、前記位
相比較器の出力側に接続されたループスイツチ
と、前記ループスイツチの出力側に接続され、か
つ共振周波数が入力周波数の変動成分周波数とほ
ぼ一致した共振をもち、ローパスフイルタの特性
を有する共振回路と、前記共振回路の出力に応じ
て発振周波数が制御される発振器とを具備したこ
とを特徴とする位相ロツクループ回路。
1. A phase comparator that compares the phases of an input signal and an output signal, a phase abnormality detector that detects a change of a predetermined level or more in the output signal of the phase comparator, and a loop connected to the output side of the phase comparator. a resonant circuit connected to the output side of the loop switch, the resonant circuit having resonance whose resonant frequency almost matches the fluctuating component frequency of the input frequency and having the characteristics of a low-pass filter; 1. A phase lock loop circuit comprising: an oscillator whose frequency is controlled.
JP57177207A 1982-10-07 1982-10-07 Phase locked loop circuit Granted JPS5966229A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57177207A JPS5966229A (en) 1982-10-07 1982-10-07 Phase locked loop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57177207A JPS5966229A (en) 1982-10-07 1982-10-07 Phase locked loop circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP4109454A Division JPH0738584B2 (en) 1992-04-28 1992-04-28 Phase locked loop circuit

Publications (2)

Publication Number Publication Date
JPS5966229A JPS5966229A (en) 1984-04-14
JPH0459809B2 true JPH0459809B2 (en) 1992-09-24

Family

ID=16027041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57177207A Granted JPS5966229A (en) 1982-10-07 1982-10-07 Phase locked loop circuit

Country Status (1)

Country Link
JP (1) JPS5966229A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3207016B2 (en) * 1993-07-05 2001-09-10 シャープ株式会社 Resin coating method for semiconductor laser device
JPH0969967A (en) * 1995-08-31 1997-03-11 Sony Corp Imaging device

Also Published As

Publication number Publication date
JPS5966229A (en) 1984-04-14

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