JPS6225302B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an FM stereo demodulation circuit that forms a multiplicand signal to be multiplied by a composite signal by a combination of a resistive voltage divider circuit and an analog multiplexer, and particularly relates to an FM stereo demodulation circuit that forms a multiplicand signal to be multiplied by a composite signal, and particularly improves the vertical symmetry of the multiplicand signal. Regarding improvements. Previously, in Japanese Patent Application No. 55-167744, the applicant proposed a stereo demodulation circuit in which a multiplicand signal to be multiplied by a composite signal is formed by a combination of a resistive voltage divider circuit and an analog multiplexer. is proposed. FIG. 1 shows an example of such an FM stereo demodulation circuit. In the figure, the composite signal C(t) supplied to the input terminal IN is connected to the resistor
It is applied to both ends of a resistive voltage divider circuit 13 consisting of R ₁ to R ₇ . Each divided voltage output of the resistive voltage divider circuit 13 is output to the left output terminal OUT _L via analog switches SW ₁ to SW ₈ , and
It is output to the right output terminal OUT _R via SW' ₁ to SW' ₈ . On the other hand, analog switches SW ₁ to _{SW 8} and analog switches SW' ₁ to SW' ₈ correspond to Q ₀ to Q ₇ of the decoder 5.
On/off is controlled by the output. Decoder 5
is output from BCD/U/D counter 4
Convert the BCD code to correspond to decimal numbers 0 to 7. The BCD/U/D counter 4 receives the output of the RS flip-flop 6 and is controlled to perform a count-up operation at the rising edge of the _Q0 output of the decoder 5, and to perform a count-down operation at the rising edge of the _Q7 output of the decoder 5. . NAND gates 7, 8, and 9 form a 76 KHz clock pulse as shown in FIG. 2 based on the Q output of RS flip-flop 6 and the Q ₃ and Q ₄ outputs of decoder 5. This clock pulse is T
After being frequency-divided by 1/4 through D-type flip-flops 10 and 11, which are configured to operate as type flip-flops, the signal is supplied to one input of a phase detector (hereinafter simply referred to as PD) 1. The other input of the phase detector PD1 is supplied with a 19KHz pilot signal extracted from the composite signal. And phase detector 1
When the phases of both inputs match, the oscillation frequency of the voltage-controlled variable oscillator circuit (hereinafter simply referred to as VCO) 3 is changed by a predetermined output from the phase detector through a low-pass filter. controlled by a so-called phase-locked loop.
The oscillation frequency of VCO3 is locked to 532KHz. According to the above configuration, the VCO3 outputs a 532KHz clock signal as shown in Figure 2,
Further, the decoder 5 supplies and outputs switching pulses as shown in FIG. The switching pulses outputted from the output terminals Q ₀ to _{Q 7} of the decoder 5 are sent to analog switches connected to the divided voltage outputs located vertically symmetrically to each other among the divided voltage outputs in the resistive voltage divider circuit 13. , i.e.
It is simultaneously supplied to SW ₁ and SW′ ₁ , SW ₂ and SW′ ₂ , and SW ₃ and SW′ ₃ . As a result, at both ends of the resistor 13,
If a constant voltage is applied to the output terminals OUT _L and
Assuming that the multiplicand signal is output from OUT _R , as shown in Figure 2, the output terminal OUT _L receives S _L (t) as the multiplicand signal, and the right output terminal also outputs the multiplicand signal.
S _R (t) is output as a multiplicand signal to OUT _R. As is clear from the figure, these multiplicand signals each have a frequency of 38KHz and are mutually exclusive.
This results in a phase difference of 180°. The waveforms of these multiplicand signals S _L (t) and S _R (t) can be set to any desired waveform by appropriately determining the values of the resistors R ₁ to _{R 7} that constitute the resistor voltage divider circuit 13. . In Figure 3, the values of each resistance value R ₁ to _{R 7} are set as shown in Table 1, and the multiplicand signal S _L (t) S _R (t)
This is a case where the waveform is each sinusoidal waveform.

[Table] Figure 4 shows the multiplicand signal as shown in Figure 3.
It is a graph showing each frequency component of demodulated output (sensitivity) when a sine wave is used. As is clear from Figure 4, when ω = 38KHz, the component of the third harmonic 3ω with respect to the component of the fundamental wave ω is:
It is possible to attenuate as much as 40dB. In this way, according to this stereo demodulation circuit,
Unlike conventional methods that use non-linear performance elements as multiplication means, signals with arbitrary waveforms can be multiplied accurately with respect to composite signals without distortion, thus further increasing the number of voltage division levels mentioned above. By configuring the waveform of the staircase wave signal to be closer to a sine wave, ideal stereo demodulation operation can be performed. Furthermore, according to this demodulation circuit, as mentioned above, it is possible to significantly reduce low-order harmonic components such as 3rd and 5th harmonics, so a filter or the like is provided before the demodulation circuit to remove these components from the composite signal. This has various advantages such as being able to solve the frequency dependence of stereo separation. However, in this stereo demodulation circuit, as shown in Figure 3, the vertically symmetrical voltages V ₁ , V' ₁ , V ₂
, V′ ₂ , V ₃ and V′ ₃ are generated corresponding to different resistance elements, so for example, in FIG _. Resistors R ₃ and R ₅ , R ₂ and
If the values of R ₆ , R ₁ and R ₇ do not completely match each other, there is a drawback that the waveform of the output multiplicand signal will be vertically asymmetric. Therefore, in order to completely maintain the vertical symmetry of the multiplicand waveforms S _L (t) and S _R (t) in this FM stereo demodulation circuit, a high degree of quality control is required when selecting the resistor elements. There was a problem that it was necessary, leading to an increase in costs. Furthermore, when the multiplicand waveform becomes vertically asymmetrical, the demodulated signal becomes more sensitive to even-order harmonics, leading to problems such as deterioration of the S/N ratio and distortion rate. This invention was devised in view of the above-mentioned problems, and its purpose is to create an FM stereo demodulation circuit that derives the output of this type of resistor voltage divider circuit to left and right output terminals via an analog multiplexer. , the multiplicand waveforms S _L (t) and S _R
The objective is to improve the vertical symmetry of (t) as much as possible. In order to solve the above problem, this invention branches the input composite signal into two signal systems for each right side output and left side output, converts the level of the signal of one system at a fixed ratio P ₀ , and For the other signal, the ratio is set to P ₁ , P ₂ (2P ₀ = P ₁ + P ₂ ), which is a constant ratio that changes alternately every half period of the subcarrier, and the left and right sides are in opposite phase. After converting the level, the potential difference between the obtained reference level signal and the upper and lower level signals is output on the right side.
Each output on the left side is divided into multiple voltages using a resistive voltage divider circuit, and these divided outputs are sequentially reciprocated from the reference level side every half cycle of the subcarrier to be output to the left and right output terminals, respectively. It is characterized by A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 5 is a block circuit diagram showing an example of an FM stereo demodulation circuit according to the present invention, and FIG. 6 is a waveform diagram showing signal states of various parts in the same figure. In Figure 5, the composite signal C(t) (including the main signal (L+R) and sub signal (L-R), etc.) supplied to the input terminal IN is branched into two signal systems: a right output system and a left output system. be done. The left system composite signal is supplied to operational amplifiers 27 and 28 in parallel, and the right system composite signal is supplied to operational amplifiers 29 and 30 in parallel. The operational amplifier 27 and the operational amplifier 29 each work as a buffer circuit, and when the analog switch SW ₀₀ and analog switch SW ₅₅ connected to the input side are on, their output level is always zero volts (that is, the overall gain is 0). ), and when analog switch SW ₀₀ and analog switch SW ₅₅ are off, it is set to operate as a buffer amplifier with a gain of 1. On the other hand, operational amplifier 28 and operational amplifier 30
are respectively input composite signals C(t)
Resistors R ₆₆ , R ₇₇ , R' ₆₆ , and R' ₇₇ are set so as to output a level that is 1/2 of that of . Between the output terminal of the operational amplifier 27 and the output terminal of the operational amplifier 28, a resistive voltage divider circuit 35 consisting of resistors R ₁₁ to R ₄₄ is connected.
are connected, and each divided voltage output of this resistive voltage dividing circuit 35 is led out to the left output terminal OUT _L via analog switches SW ₁₁ to _{SW 44} . Similarly, between the output terminal of the operational amplifier 29 and the output terminal of the operational amplifier 30, there are resistors R' ₁₁ to R' _{44 .}
A resistor voltage divider circuit 36 consisting of
It is led out to the right output terminal OUT _R via SW ₁₁ ′ to SW ₄₄ ′. On the other hand, these analog switches SW ₁₁ ′~
_SW44 ', _SW11 to _SW44 , and _SW00 to _SW55 are on/off controlled by the output of a digital circuit for generating a switching signal, which will be described later. Next, the above digital circuit will be explained. The oscillation output signal of the voltage controlled oscillator circuit (hereinafter referred to as VCO) 16 is sent to the BCD/U/D counter 17, BCD
Decimal decoder 18, NAND gate 20, 2
1, inverters 22 and 23, an RS flip-flop 24, a D-type flip-flop 25, a phase detector 14, and a low-pass filter 15. BCD/U/D counter 17 is this
It counts the clock pulses CP output from the VCO 16 and outputs them as a BCD code. Decoder 1
8 converts the BCD code output from the BCD/U/D counter 17 into decimal numbers 0 to 7 and outputs it. The RS flip-flop 19 is set by the Q ₀ output of the BCD decimal decoder 18 and is set by the Q ₇
Reset on output. The BCD/U/D counter is controlled to be switched up or down by the Q output of this RS flip-flop. As a result,
The BCD/U/D counter 17 alternately repeats up-counting and down-counting every time it counts eight 532KHz clock pulses output from the VCO 16. As a result, each output terminal of the decoder 18
Timing pulses as shown in FIG. 6 are output to Q ₀ to Q ₇ . The respective outputs Q ₀ to _{Q 7} of these decoders 18 are further connected to OR gates 31 to 34.
or gates 31 to 34
A timing pulse as shown in FIG. 6 is output from. The outputs of these four OR gates are output from analog switches SW ₄₄ and SW ₄₄ ', SW ₃₃ and SW ₃₃ ', SW 11 and SW ₁₁ , which are arranged symmetrically.
SW ₁₁ ′ is supplied in parallel. On the other hand, on the output side of the RS flip-flop 24,
As shown in Figure 6, a rectangular wave that becomes “1” or “0” is output every half cycle of the subcarrier, and the RS
^{The Q} output of the flip-flop 24 is connected to the operational amplifier 27.
The Q output of the RS flip-flop ₂₄ is supplied as a switching signal to an analog switch SW ₅₅ inserted to the input side of the operational amplifier 29. The D-type flip-flop 26 is for generating a cancel signal for canceling the pilot signal. According to the above configuration, the composite signal C is always present on the output side of the operational amplifier 28 and the operational amplifier 30.
(t) is stepped down to 1/2 level and output. On the other hand, the composite signal is outputted to the output sides of the operational amplifiers 27 and 29, with the level controlled to be 1 times or 0 times every half period of the subcarrier. When the gain of the operational amplifier 27 is set to 1, the output of the operational amplifier 29 is always set to 0. Conversely, when the gain of the operational amplifier 27 is set to 0, the output of the operational amplifier 29 is always set to 0.
The gain of operational amplifier 29 will be set to 1. That is, the output of the operational amplifier 27 and the output of the operational amplifier 29 are always in opposite phases. On the other hand, analog switches SW ₁₁ to _{SW 44} are turned on sequentially corresponding to the period when the analog switch SW ₀₀ is on and off, respectively.
SW ₄₄ →SW ₃₃ →SW ₂₂ →SW ₁₁ →SW ₂₂ →SW ₃₃ →
Similarly, the analog switches SW ₁₁ to _{SW 44} are turned on in the same way as SW ₄₄ , SW ₄₄ ′ → SW ₃₃ ′ → SW ₂₂ during the period corresponding to when the analog switch SW ₅₅ is on or off. ′→
It turns on as SW ₁₁ ′→SW ₂₂ ′→SW ₃₃ ′→SW ₄₄ ′. Therefore, if a DC voltage is applied to the input terminal IN, the left output terminal OUT _L will receive a step-wave multiplicand signal S _L (t) as shown in FIG.
is outputted, and a staircase wave-like multiplicand signal S _R (t) is similarly outputted to the right output terminal OUT _R. In other words, any composite signal C can be input to the input terminal IN.
(t), the left output terminal OUT _L
The result of multiplying this composite signal C(t) by the left multiplicand signal S _L (t) shown in FIG. 6 is outputted to the right output terminal OUT _R. Multiplicand signal S _R
(t) is output, and thus stereo demodulation operation is achieved. The waveforms of the multiplicand signals S _L (t) and S _R (t) are the resistance values
By appropriately determining R ₁₁ to _{R 44} and resistance values R ₁₁ ′ to _{R 44} ′, it is possible to make the wave infinitely close to a sine wave. By making this waveform as close as possible to a sine wave, the odd-numbered harmonic components of the demodulated output (sensitivity), ie, 3ω, 5ω, 7ω, 9ω, are , 11ω, 13ω, etc., and extremely efficient stereo demodulation can be achieved. Furthermore, according to the present invention, the upper and lower half waves of the multiplicand signals S _L (t) and S _R (t) in FIG. The vertical symmetry of is reliably maintained, and therefore even harmonic components of the demodulated output (sensitivity) can be significantly reduced. Thus, according to the FM stereo demodulation circuit of this embodiment, the composite signal C(t) supplied to the input terminal IN is split into two into the left output system and the right output system, and then further divided into two. The system branches into two systems, and one system steps down to 1/2 level through an operational amplifier 28, and the other system switches the level between 0x and 1x every half period of the subcarrier through an operational amplifier 27. Then, the outputs of the two operational amplifiers 27 and 28 or the operational amplifiers 29 and 30 in the right and left output systems are divided into a plurality of voltages by the resistor voltage divider circuits 35 and 36, respectively, and the voltages of these two resistor voltage divider circuits 35 and 36 are Analog switch that configures each divided voltage output into an analog multiplexer
SW ₁₁ to SW ₄₄ and SW ₁₁ ′ to _{SW 44} ′ perform one reciprocating operation in a period corresponding to a half cycle of the subcarrier, and sequentially take them out and send them to the output terminals OUT _L and
Since the multiplicand signals S _L (t) and S _R (t) have a phase difference of 180° from each _other ,
Since each half period of these multiplicand signals is determined corresponding to the same resistive element, the vertical symmetry of these multiplicand signals is reliably maintained, and this makes it possible to reduce harmonics at odd and even harmonics. Sensitivity can be significantly reduced. In this embodiment, the gain of the buffer circuit constituted by the operational amplifier 28 and the operational amplifier 30 is set to 1/2, and the gain of the operational amplifier 27 and the operational amplifier 2 is set to 1/2.
The gain of the buffer circuit consisting of 9 is 0 and 1, respectively.
Generally, if the gain of the buffer circuit composed of the operational amplifier 28 and the operational amplifier 30 is _P0 , the buffer circuit composed of the operational amplifier 27 and the operational amplifier 29 is switched alternately. It is sufficient that the two gains P ₁ and P ₂ of the circuit have a relationship of 2P ₀ =P ₁ +P ₂ . Furthermore, by increasing the number of resistive elements constituting the resistive voltage divider circuits 35 and 36 and appropriately setting the resistance value of each resistor, the waveforms of the multiplicand signals S _L (t) and S _R (t) can be further improved. Of course, it is possible to approximate a sine wave. As is clear from the above explanation, the FM stereo demodulation circuit according to the present invention controls the level of the composite signal at a fixed ratio _P0 by the left and right reference level setting circuits, and also sets the upper and lower levels of the left and right sides. Depending on the circuit, the level of the composite signal is set at a fixed ratio P ₁ , P ₂ (2P ₀ = P ₁ + P ₂ ) that alternately varies every half period of the subcarrier, and the left and right sides are in opposite phase. The output potential difference between the reference level setting circuit and the upper and lower level setting circuits is divided into a plurality of levels by the left and right resistor voltage divider circuits. Since the pressure output is sequentially scanned back and forth from the output side of the reference level setting circuit by the analog multiplexers on the left and right sides every half period of the subcarrier, the multiplicand signal is surely vertically symmetrical. This solves the problem of increased sensitivity to even harmonics, which was a problem with conventional circuits, and significantly improves the reliability and demodulation performance of this type of FM stereo demodulation circuit.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the electric circuit of the FM stereo demodulation circuit previously proposed by the applicant.
The figure is a waveform diagram showing the signal state of each part in Figure 1, Figure 3 is a waveform diagram showing the state where the multiplicand signal is a sine wave, Figure 4 is a graph showing harmonic components included in the demodulated output, Figure 5 is related to the present invention.
A block diagram showing an example of an FM stereo demodulation circuit,
FIG. 6 is a waveform diagram showing the signal state of each part in FIG. 5. 27...Upper and lower level setting circuit on the left, 28...
Reference level setting circuit on the left, 29... Upper and lower level setting circuit on the right, 30... Reference level setting circuit on the right, 35... Resistor voltage divider circuit on the left, 36... Resistor voltage divider circuit on the right, SW ₁₁ ~ SW ₄₄ ……Analog switch that constitutes the left multiplexer,
SW ₁₁ ′ to SW ₄₄ ′...Analog switch that makes up the right multiplexer, OUT _L ...Left output terminal, OUT _R ...Right output terminal.

Claims (1)

[Claims] 1. FM demodulating a stereo signal from a composite signal including at least a main signal and a sub signal
The stereo demodulation circuit includes left and right reference level setting circuits that convert the level of the composite signal at a constant ratio P0, and a constant level setting circuit that converts the level of the composite signal at a constant ratio _P0 that alternately changes the level of the composite signal every half period of the subcarrier. Ratio P ₁ , P ₂ (2P ₀ = P ₁ +
P ₂ ), and the left side and right side convert the levels so that they are in opposite phase, the upper and lower level setting circuits on the right side, and the left side that divides the output potential difference between the reference level setting circuit and the upper and lower level setting circuits into multiple voltages. , the divided voltage outputs of the right resistor voltage divider circuit and the left and right resistor voltage divider circuits are sequentially scanned back and forth from the output side of the reference level setting circuit every half cycle of the subcarrier and sent to the left and right output terminals, respectively. An FM stereo demodulation circuit comprising a left-hand analog multiplexer and a right-hand analog multiplexer. 2. The FM stereo demodulation circuit according to claim 1, wherein each resistance value of the resistor voltage divider circuit is set to correspond to an upper half wave or a lower half wave of a sine wave. 3. The FM stereo demodulation circuit according to claim 1, wherein the ratio P ₀ is set to 1/2, and the ratios P ₁ and P ₂ are set to 0 and 1, respectively.