JPS634737B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a stereo demodulation circuit that reduces crosstalk components and improves the degree of separation, and in particular multiplies a composite signal by a multiplier signal having subcarrier frequency components. The present invention relates to a stereo demodulation circuit that adds or subtracts the same to a composite signal again.

Conventionally, SW-type MPX stereo demodulation circuits have been configured to switch composite signals using a 38KHz subcarrier, thereby performing synchronous demodulation.

In this case, the composite signal vc(t) (excluding the pilot signal) is expressed as vc(t)=(L+R)+(L-R) sinωct(ωc; subcarrier frequency), and the switching signal s(t)
If we express the rectangular wave used as s(t)=1/2±(2/π) sinωct±(2/3π) sin3ωct±..., these multiplication results vc(t)・s
The audio component contained in (t) is, for example, Lo
In the (left output) component, Lo=(1/2+1/π)L+(1/2−1/π)R, and a crosstalk component of (1/2−1/π)R is generated. As a result, the maximum degree of separation in principle is
The problem was that it was only 13dB.

The present invention was made to solve the above problems, and its purpose is to reduce crosstalk components and provide a stereo demodulation circuit with good separation.

In order to achieve the above object, the present invention multiplies a composite signal including at least a stereo main channel signal and a stereo reverse channel signal by a multiplier signal having a subcarrier frequency component, a first arithmetic circuit that forms an output signal that is the sum of the signal and the composite signal; and a second arithmetic circuit that forms an output signal that is the difference between the signal that is the multiplication result and the composite signal.
The present invention is characterized in that it comprises arithmetic circuits, and each output signal of the first and second arithmetic circuits is extracted as a demodulated signal.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a conceptual diagram for explaining a first method of a stereo demodulation circuit according to the present invention.

As shown in the figure, the stereo demodulation circuit according to the first method generates a multiplier signal having subcarrier frequency components for a composite signal Vc(t) including at least a stereo main channel signal and a stereo subchannel signal. a first arithmetic circuit Z ₁ for multiplying F by a single-output analog multiplier P and forming an output signal that is the sum of this multiplied signal and said composite signal Vc(t); and a second arithmetic circuit Z ₂ that forms an output signal that is the difference between the composite signal Vc(t) and the composite signal Vc(t) _;
The output signals fL(t) and fR(t) of _Z2 are taken out to terminals L and R as demodulated signals.

In this way, the signal fL(t) at the output terminal L
is expressed as fL(t)=vc(t)(1+F), and the signal fR at output terminal R
(t) is expressed as fR(t)=vc(t)(1-F). At this time, if the value of the multiplier signal F is set to F=2sinωct (ωc; subcarrier frequency), the L and R demodulated output signals fL(t),
This makes it possible to significantly reduce the crosstalk component contained in fR(t).

The above principle is proven as follows.

First, we will prove the demodulated output of the L channel. If we assume that the value of the L component included in the composite signal is L, the value of the R component is R, and the frequency of the subcarrier is ωc, then the composite signal vc(t)
can be expressed as vc(t)=L(1+sinωct)+R(1-sinωct) (excluding the pilot signal). Moreover, when the value of the multiplier signal F is set to F=Ksinωct, the demodulated output signal fL of the L channel is
(t) is fL(t)={L(1+sinωct) +R(1-sinωct)}(1+Ksinωct), and rearranging this equation, fL(t)=L{1+K/2+(1+K) sinωct-(K /2) cos2ωct} +R{1-K/2+(K-1) sinωct +(K/2)cos2ωct}. Here, if only the audio signal component fA(t) included in the above equation is extracted, it is expressed as fA(t)=L(1+K/2)+R(1-K/2). In other words, the left demodulated signal fL
(t) audio signal fA(t) has R(1-
K/2) is included.

Therefore, if we set R(1-K/2)=0 and find the value of K for the crosstalk component to be 0, we get:
K=2, and it can be seen that the value of the multiplier signal F mentioned above should be F=2sinωct.

Similarly, when finding the audio signal component fA(t) included in the right demodulated output signal fR(t), fA(t)=L(1-K/2) +R(1+K/2), and in this case also. A crosstalk component of L(1-K/2) is included.

Therefore, in the same way as above, set L(1-K/2)=0 and calculate K for the crosstalk component to be 0.
When the value of is calculated, it becomes K=2.

As a result, if the value of the multiplier signal F is set to F=2sinωct, the crosstalk components included in the left and right audio signals can be completely removed at the same time. 1 is an electric circuit diagram of a specific example of a stereo demodulation circuit (hereinafter referred to as a first embodiment); FIG. In addition, in the figure, each R written in parentheses indicates the resistance value of the resistor r.

As shown in the figure, the composite signal vc(t) supplied to the input terminal IN is inputted to the plus input of the operational amplifier OP01 after being divided into half by resistors r1 and r2. .

On the other hand, when the analog switch S1 is off and the analog switch S2 is on, the negative input of the operational amplifier OP01 has a
The output Vx of the operational amplifier OP1 is fed back via the resistor r3.

On the other hand, when analog switch S1 is on and analog switch S2 is off, at a predetermined ratio determined by resistor r4 and resistor r5,
The composite signal vc(t) and the output Vx of the operational amplifier OP1 are mixed and fed back. Here, when clock φ is “1” and clock φ is “0”,
The value of the output Vx of the operational amplifier OP01 satisfies vc(t)/2 = {Vx・R+vc(t)・2R}/3R, so the value of Vx at this time is Vx=−vc(t)/2 It is expressed as

On the other hand, when the clock φ is "0" and the clock φ is "1", the operational amplifier OP01 becomes a buffer, so the value of Vx is expressed as Vx=vc(t)/2.

Therefore, the operational amplifier OP01 operates as a multiplication circuit having a rectangular wave as shown in FIG. 3 as the multiplier signal f(t). And this multiplier signal f
When (t) is expressed as a Fourier series, it is expressed as f(t)=4/π{sinωct+(1/3)sin3ωct+...}. Therefore, the value of the output Vx is Vx=vc(t)・f(t)=vc(t)・4/π{sinωct+(1/3)sin3ωct+...}.

This output Vx is then connected to level adjustment resistor r8
through the operational amplifier OP0 that constitutes the adder circuit.
2, and is similarly supplied to an operational amplifier OP03 forming a subtraction circuit via a level adjustment resistor r9.

As a result, the value of the signal V(L) output to LOUT is V(L)=-(R10/R6)・vc(t) −(R10/R8)・vc(t)・f(t) =- (R10/R6)・vc(t) {1+(R6/R8)・f(t)} =−(R10/R6)・vc(t) {1+(4・R6/πR8) [sin3ωct+(1/3 ) sinωct＋……〕} Here, the term (1/3)sin3ωct+... has nothing to do with the frequency band of the audio signal, so it can be removed using a high-cut filter. Therefore, by setting 4·R6/πR8=2 and finding the values of R6 and R8, it is possible to completely remove the crosstalk component included in the left demodulated output.

Similarly, for the right side demodulated output, if we set 4・R7/π・R9=2 and find the values of R7 and R9, we can also completely remove the crosstalk component included in the right side demodulated component. This is possible.

Next, FIG. 4 shows another specific example of the FM stereo demodulation circuit related to the first method (hereinafter referred to as the second method).
FIG. 2 is an electrical circuit diagram showing an example.

The stereo composite signal supplied to the input terminal IN passes through an operational amplifier OP6 that is configured to operate as a buffer, and is then branched into a left system and a right system, which are respectively connected to an operational amplifier OP4 that operates as an adder circuit and an operational amplifier OP4 that operates as a subtracter. It is supplied to an operational amplifier OP5 which operates as a circuit. Furthermore, the output Ei of the operational amplifier OP6 is supplied in parallel to the operational amplifier OP1 and the operational amplifier OP2. operational amplifier
The gain of OP1 is when analog switch S3 is on,
In addition, when the analog switch S4 is off, it is set to be "-2", and when the analog switch S3 is off and the analog switch S4 is on, it is set to be "0". ing.

Q38 and Q38 output from a digital circuit DGT, which will be described later, are supplied as switching signals to the analog switch S3 and the analog switch S4.

On the other hand, the operational amplifier OP2 is configured to operate as an adder circuit that adds the output signal Ei of the operational amplifier OP6 and the output of the operational amplifier OP1.

The output of the operational amplifier OP2 is applied to both ends of the resistor ladder LAD, and each divided voltage output of the resistor ladder LAD is selectively taken out via the analog switches S5 to S8 and buffered. Operational amplifier configured as
It is supplied to the aforementioned operational amplifier OP4 and operational amplifier OP5 via OP3.

Next, the configuration of the digital circuit DGT will be explained.

The oscillation output signal of the voltage controlled oscillator 1 is BCD.
U/D counter 2, BCD/DEC datar 3, NAND gate 4 and NAND gate 5, RS flip-flop 6, D-type flip-flop 7, phase
It is locked to 532KHz by a phase-locked loop consisting of a detector 8 and a DC amplifier 9.

The BCD/U/D counter 2 counts the clock pulses output from the voltage controlled oscillator 1,
Output this in BCD code. The BCD-DEC decoder 3 converts the BCD code output from the BCD/U/D counter 2 into decimal numbers 0 to 7 and outputs the converted code.

The RS flip-flop 10 is set by the Q0 output of the BCD-DEC decoder 3 and reset by the Q7 output. The Q output of this RS flip-flop 10 is used to control the BCD/U/D counter 2.
is controlled by up/down switching. As a result,
BCD/U/D counter 2 is voltage controlled oscillator 1
Every time 8 532KHz clock pulses output from the 8 clock pulses are counted, up-counting and down-counting are repeated alternately.

Therefore, timing pulses are output to each output terminal Q0 to Q7 of the BCD-DEC decoder 3 at the timing shown in FIG. And these
Each output Q0 to Q7 of the BCD-DEC decoder 3 is
Furthermore, it is gate-controlled via OR gates 11-14 and is supplied as a switching signal to analog switches S5-S8 connected to each output side of the aforementioned resistance ladder LAD.

On the other hand, on the output side of RS flip-flop 6,
As shown in FIG. 5, a rectangular wave that becomes "1" or "0" is output every half period of the subcarrier, and the Q38 output of this RS flip-flop 6 is connected to the input side of the operational amplifier OP1 as described above. The output of Q38 is supplied as a switching signal to analog switch S3.
4 as a switching signal. The D-type flip-flop 15 is for generating a cancel signal for canceling the pilot signal.

According to the above configuration, the output Ei of the operational amplifier OP6 is outputted to the output side of the operational amplifier OP1 with the level alternately switched to 0 times minus 2 times, as shown in FIG. 5, and the output of the operational amplifier OP2 is output. On the side, a rectangular wave that is inverted around the 0 level is output, corresponding to the addition result of the output of the operational amplifier OP1 and Ei. Furthermore, this square wave is connected to the resistance ladder described above.
The signal is converted into a pseudo sine wave by the LAD and analog switches S5 to S8, and further outputted via the operational amplifier OP3.

As a result, operational amplifier OP1, operational amplifier OP
2. Resistance ladder LAD and operational amplifier OP3 as a whole operate as a multiplier with a multiplier signal containing a component of 2sinωct, and as a result,
A demodulated output of -Ei (1+2 sinωct) is obtained at LOUT, and a demodulated output of -Ei (1-2 sinωct) is obtained at ROUT.As is clear from the demodulation principle described above, each left and right demodulated Crosstalk components included in the output are completely removed.

FIG. 6 is a conceptual diagram for explaining the second method of the stereo demodulation circuit according to the present invention. As shown in the figure, the stereo demodulation circuit according to the second method generates a multiplier signal having subcarrier frequency components for a composite signal Vc(t) including at least a stereo main channel signal and a stereo subchannel signal. F is multiplied by a complementary output type analog multiplier PP to obtain a pair of positive and negative complementary multiplication outputs, of which a composite signal Vc is applied to the positive output.
(t) to form a sum of the composite signal Vc(t) and the multiplier signal F _;
a second arithmetic circuit _Z2 that adds a composite signal Vc(t) to the negative output to form a difference between the composite signal Vc(t) and the multiplier signal F;
and each output signal fL of the second arithmetic circuit Z ₁ and Z ₂
(t) and fR(t) are taken out to terminals L and R as demodulated signals.

In this way, as in the case of the first method described above, the signal fL(t) at the output terminal L is expressed as fL(t)=vc(t)(1+F), and the signal at the output terminal R fR
(t) is expressed as fR(t)=vc(t)(1-F). Then, when the value of the multiplier signal F is set to F=2sinωct (ωc: subcarrier frequency), the L and R demodulated output signals fL(t), fR(t) are obtained using the same principle as the first method. This makes it possible to significantly reduce the crosstalk components contained in the

Next, FIG. 7 is an electrical circuit diagram of a specific example (hereinafter referred to as the third embodiment) of a stereo demodulation circuit according to the second method described above.

In addition, in the figure, each R written in parentheses indicates the resistance value of the resistor r.

In the figure, a composite signal vc(t) containing at least a stereo main channel signal and a stereo subchannel signal is impedance-converted via a buffer 20 and then branched into two systems, one of which is connected to an inverting amplifier. 21.

Next, the non-inverting output that is the output of the buffer 20 and the inverting output that is the output of the inverting amplifier 21 are as follows.
The signals are supplied to the left selector 22 and the right selector 23 in parallel, respectively.

The left and right selectors 22 and 23 are respectively controlled to switch in synchronization with the logic signal A, and are configured to selectively take out either the non-inverted output or the inverted output.

The outputs of these left and right selectors 22 and 23 are then supplied to left and right variable resistance circuits 24 and 25, respectively.

The resistance values of the variable resistance circuits 24 and 25 are controlled in four stages according to the respective logic states of the logic signals B and C, that is, when B="1" and C="0", R ₁ , When C="1" and B="0", R ₂ , B
It is set so that R ₁ R ₂ (here, indicates the parallel combined resistance value) when =C="1", and ∞ when B=C="0".

Further, the arithmetic circuits 26 and 27 constitute a multiplier circuit in conjunction with the switching operation of the variable resistance circuits 24 and 25, respectively, and at the same time, the outputs of the variable resistance circuits 24 and 25 and the buffer supplied via the resistor r3. It is configured to also function as an adder circuit that adds the outputs of 20 and 20.

On the other hand, constructing the composite signal vc(t)
19KHz pilot signal is phase detector 2
8. It is supplied as a reference frequency signal to the PLL consisting of a VCO 29, a BCD/8-bit counter 30, and a 1/2 cycle 31.
The oscillation frequency of VCO 29 is locked to 304KHz.

Further, the count outputs D ₀ to D ₂ of the counter 30 are decoded in a predetermined format via the decoder circuit 32, thereby converting the aforementioned logic signals A,
B, C and their inverted signals are formed.

In addition, the resistors r ₁ and r ₂ constituting the variable resistance circuits 24 and 25 respectively are set at r ₁ /(r ₁ r ₂ )=sin (π/4)≈1.4 in order to approximate the waveform of the multiplier signal to a sine wave. For example, r ₁ = 1KΩ,
r ₂ =2.5KΩ.

A truth table of the decoder circuit 32 is shown in FIG.
As shown in the figure, this decoder circuit converts the 8-bit binary data formed in response to the 304KHz pulse locked by the PLL described above into such a way that only one bit differs between successive adjacent codes. , it is designed to be converted into a special code.

If the above-mentioned first and second selectors 22, 23 and the left and right variable resistance circuits 24, 25 are driven by such a special code, the multiplier signal F of the above-mentioned multiplication circuit will be as shown in FIG. A sine wave like the following can be obtained approximately.

According to the above configuration, the composite signal vc
(t) is impedance-converted via the buffer 20, and then branched into two different signal systems with a phase difference of 180 degrees, and then supplied in parallel to the selectors 22 and 23, and as a result, these selectors 22,
On the output side of 23, the composite signal vc(t) is inverted and output every half period of the subcarrier,
Furthermore, the output of this selector is connected to variable resistance circuits 24, 2.
5, the OP amplifier 26, along with the composite signal vc(t) supplied via resistor _r3
27, where multiplication and addition operations are performed simultaneously.

As a result, output terminals L and R each have vc
A demodulated output including (t) (1+2 sin ωct) and vc(t) (1−2 sin ωct) is obtained. That is,
By extracting audio components from this demodulated output through an appropriate low-pass filter, desired left and right demodulated outputs can be obtained.

Moreover, especially in this third embodiment, since a special code in which only one bit of logic differs between adjacent codes is adopted as the output of the decoder 32, the selectors 22, 23 and the variable resistance circuit 24 , 25, there is also the effect that noise generation during switching is extremely small.

As is clear from the first to third embodiments described above, the stereo demodulation circuit according to the present invention adds subcarrier frequency components to a composite signal including at least a stereo main channel signal and a stereo subchannel signal. a first arithmetic circuit that multiplies a multiplier signal having a multiplier signal and forms an output signal that is the sum of the multiplied signal and the composite signal, and an output signal that is the difference between the multiplied signal and the composite signal; second to form
arithmetic circuits, and each output signal of these first and second arithmetic circuits is taken out as a demodulated signal, so crosstalk components included in each of the left and right demodulated outputs are significantly reduced. This makes it possible to improve the degree of separation as much as possible.

Furthermore, as shown in the second and third embodiments, if a sine wave corresponding to the multiplier signal 2sinωct is formed by a resistor element and a digital switch, the odd harmonics included in the multiplication result can be The components and the even-numbered harmonic components can be significantly reduced, making subsequent filter design easier.

Furthermore, as shown in the third embodiment, the switching of the digital switch is performed once between adjacent codes.
By using special codes that differ only in bits, it is possible to further reduce the generation of noise during switching.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram for explaining the first method of the stereo demodulation circuit according to the present invention, FIG. 2 is an electric circuit diagram showing the configuration of the first embodiment of the present invention, and FIG. 3 is the diagram as shown in FIG. FIG. 4 is an electric circuit diagram showing the second embodiment of the present invention, FIG. 5 is a waveform diagram showing signal states of various parts in FIG. 4, and FIG. 6 is a diagram showing the signal state of each part in FIG. FIG. 7 is an electric circuit diagram showing the configuration of a third embodiment of the present invention;
FIG. 8 is a truth table for explaining the operation of the decoder circuit, and FIG. 9 is a diagram showing the multiplier signal waveform in the third embodiment. OP02, OP4...addition circuit. OP03, OP5
...Subtraction circuit, OP01, OP1 to OP3 ... Multiplication circuit, 21 ... Inverting amplifier, 22, 23 ... Selector, 24, 25 ... Variable resistance circuit, 26, 27
...OP amplifier.

Claims (1)

[Claims] 1 Multiplying a composite signal including at least a stereo main channel signal and a stereo subchannel signal by a multiplier signal having a subcarrier frequency component, and producing an output signal that is the sum of this multiplied signal and the composite signal. and a second arithmetic circuit that forms an output signal that is the difference between the signal resulting from the multiplication and the composite signal, and each output of the first and second arithmetic circuits. A stereo demodulation circuit characterized in that a signal is extracted as a demodulated signal.