JPS6226582B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method in which an electrode film formed on the main surface of a semiconductor substrate is connected to an external electrode by applying pressure.
The present invention relates to a so-called pressure contact type semiconductor device.

The pressure contact type semiconductor device has a structure suitable especially when the current to be handled is large and the amount of heat generated inside the semiconductor substrate is large. The feature of this structure is that the electrode film provided on the main surface of the semiconductor substrate and the external electrode located at the outermost part of the semiconductor device are fixed and electrically connected to each other without using adhesives such as brazing. This is achieved by applying pressure between them. In this way, thermal stress caused by heat generation within the semiconductor substrate during energization can be relieved by sliding between the electrode film and the external electrode. When using a material (e.g. copper) with a thermal expansion coefficient significantly different from that of the semiconductor substrate as the external electrode, an internal buffer made of a material (e.g. tungsten) with a thermal expansion coefficient similar to that of the semiconductor substrate is installed between the external electrode and the electrode film. It is also widely used to alleviate thermal stress using an internal buffer. In this case, the internal buffer, electrode membrane and external electrode are fixed by pressure.

Conventionally, the above-described pressure contact structure has also been applied to semiconductor switching devices such as gate turn-off (hereinafter referred to as GTO) thyristors, field effect thyristors, and transistors that handle relatively large amounts of power. In these semiconductor switching devices, a large number of unit elements are arranged in parallel within a semiconductor substrate so that large currents can be switched without impairing switching characteristics.
A structure is adopted in which the electrode films of these unit elements are connected in parallel by an internal buffer or an external electrode.

Regarding the structure of this conventional example and its drawbacks,
A GTO thyristor with an internal buffer will be explained in detail with reference to FIG. In FIG. 1, a semiconductor substrate 1 includes a p-type emitter (anode-side emitter) layer 11, an n-type base (anode-side base) layer 12, a p-type base (cathode-side base) layer 13, and an n-type emitter (cathode-side emitter) layer 12. ) has a laminated structure of 14 layers. A tungsten anode electrode 5 is brazed to the main surface of the semiconductor substrate 1 on the anode layer 11 side. The main surface on the opposite side has an uneven shape. The cathode layer 14 is exposed in the convex portion, and the p-type base layer 13 is exposed in the concave portion, and a cathode electrode film 2 and a gate electrode film 3 are formed on each exposed surface.

As shown in FIG. 1a, the cathode electrode film 2 is arranged on the main surface of the semiconductor substrate 1 in a radially divided manner. The cathode layer 14 is also divided corresponding to the individual cathode electrode films 2, whereby the semiconductor substrate 1 is divided into a large number of unit elements. Incidentally, in FIG. 1a, the boundary line of the unevenness and the gate electrode film 3 are not shown in order to avoid complication of the drawing.

An annular internal buffer 4 is placed on the cathode electrode film 2, so that the cathode electrode films of a large number of unit elements are connected in parallel. A copper cathode external electrode 6 is placed on the internal buffer 4 . Further, the anode electrode 5 is brazed to an anode external electrode 7 made of copper.
GTO thyristor gate external electrode (not shown)
are a recess 61 connected to the center of the gate electrode film 3 and provided in the internal buffer through-hole 41 and the cathode external electrode 6, and a groove provided in a part of the cathode external electrode 6 and communicating the recess 61 with the outside. (not shown) to the outside.

A flange (not shown) attached to the outer periphery of each cathode and anode external electrode is provided between the cathode and anode external electrodes.
and another flange provided on an insulating cylinder (not shown) that houses the semiconductor substrate therein, and are sealed by welding together. When in use, pressure is applied between the cathode external electrode 6 and the anode external electrode 7, and this pressure causes the cathode external electrode 6 to
and the internal buffer 4, and the internal buffer 4 and the cathode electrode film 2 are well connected electrically and thermally, so that the forward voltage drop value is low and the heat generated during energization is easily transmitted to the external cooler. be made into

For this purpose, the above-mentioned pressing force is required to be a predetermined value or more, and a pressure of about 200 Kg/cm ² is usually used. For example, when using an internal buffer 4 with an outer diameter of 2.5 cm and an inner diameter of 1.2 cm, in order to lower the electrical and thermal resistance between the internal buffer 4 and the cathode external electrode 6, a pair of external electrodes 6 and 7 is used. A total pressure of about 760 kg is applied between them. This pressure is simultaneously transmitted to the internal buffer 4 and the cathode electrode 2, thereby electrically and thermally connecting them.

However, according to the experiments conducted by the present inventors, the pressure that makes good electrical and thermal contact between the external cathode electrode 6 and the internal buffer 4 is too high between the internal buffer 4 and the cathode electrode film 2. It became clear that. For this reason, together with the addition of thermal cycles during use of semiconductor devices,
It became clear that the cathode electrode film 2 caused a creep phenomenon and was deformed. If the deformation is significant, the cathode electrode film 2 may come into contact with the adjacent gate electrode film 3, resulting in a short circuit between the cathode and the gate, or the cathode electrode film 2 may become unevenly deformed, which progresses and causes internal buffer 4. Since the parallelism between the internal buffer 4 and the semiconductor substrate 1 is not maintained, an accident may occur in which the outer periphery of the internal buffer 4 and the semiconductor substrate 1 come into contact with each other. Furthermore, even if such an accident does not occur, the thickness of the cathode electrode film 2 becomes thinner due to deformation due to the creep phenomenon, and the cathode electrode film 2 and the semiconductor substrate 1 become alloyed, causing the switching characteristics of the semiconductor device to deteriorate. There were flaws that worsened.

It has been found that although such defects are noticeable when a metal with relatively low hardness, such as aluminum, is used as the cathode electrode film 2, it also occurs when other metals are used.

In order to avoid the above-mentioned disadvantages, the total pressure applied between the pair of external electrodes is lowered, so that the above-mentioned disadvantages due to the creep phenomenon between the internal buffer 4 and the cathode electrode film 2 do not occur, and the electrical and thermal We considered ways to ensure good contact. However, in that case, the pressing force between the internal buffer 4 and the cathode external electrode 6 was also reduced, and a new problem arose in that sufficient electrical and thermal contact between them was not achieved. As a result, the thermal resistance between the internal buffer 4 and the cathode external electrode 6 increases, resulting in the disadvantage that the semiconductor device cannot be cooled sufficiently. The same applies to the case where the anode electrode 5 and the anode external electrode 7 are brought into pressure contact.

An object of the present invention is to avoid the drawbacks of the above-mentioned conventional examples, improve the disharmony of the pressure contact force between electrode members that are pressure-welded over a wide area, and between electrode members that are pressure-welded over a narrow area,
The object of the present invention is to provide a press-contact type semiconductor device that achieves good electrical and thermal contact in both cases.

Another object of the present invention is to provide a pressure contact type semiconductor device in which the electrode film is not deformed due to creep phenomenon.

In order to achieve the above object, the present invention is characterized by a semiconductor substrate having different types of electrode films formed on one main surface thereof, and a semiconductor substrate having different types of electrode films formed on one main surface of the semiconductor substrate. In a device having an electrode member brought into pressure contact with another electrode member connected to the other main surface of the semiconductor substrate, a means for sharing the pressing force between the above-mentioned pair of electrode members with the above-mentioned kind of electrode film is provided. It is at the point that I have set. That is, it has a surface portion that is brought into pressure contact with the electrode member described above, similar to the above-mentioned type of electrode film, but it has a pressure regulating region that does not itself serve as a current path.

By adopting the above configuration, the contact area between the semiconductor substrate and the electrode member, such as the internal buffer, increases by the pressure adjustment area, so that under the same total pressure, the electrode film of the semiconductor substrate The pressure per unit area applied decreases. Therefore, for example, in a device with an internal buffer, it is possible to maintain good electrical and thermal contact between the internal buffer and the electrode film while reducing the pressure per unit area between the two to prevent deformation of the electrode film. can do.
Furthermore, since the pressure between the internal buffer and the external electrode does not change, good electrical and thermal contact can be maintained between them. Furthermore, since the pressure regulating region according to the present invention does not serve as a current path, it does not deteriorate the electrical characteristics of the semiconductor substrate in any way.

Examples of the present invention will be described below.

FIG. 2 shows the structure of a GTO thyristor with an internal buffer, which is an embodiment of the present invention.

In FIG. 2, the same parts as in FIG. 1 are designated by the same reference numerals as in FIG. Note that the pair of external electrodes are omitted in FIG. 2.

In FIG. 2, the semiconductor substrate 1 includes a thyristor region A as an operating region, an annular pressure regulating region B,
Annular isolation region C interposed between region A and region B
It consists of The junction structure of thyristor region A is the first
This is equivalent to that of the semiconductor substrate 1 in the figure. The pressure regulating region B has a laminated structure between the internal buffer 4 and the anode electrode 5, which includes a metal film 22, an n ⁺ type layer 214, a p type layer 13, an n type layer 12, and an n ⁺ type layer 211. The isolation region C includes a p-type layer 13, an n-type layer 12,
It has a laminated structure consisting of an n ⁺ type layer 211. The p-type base layer in region A and the p-type layers in regions B and C, and the n-type base layer in region A and the n-type layer in regions B and C are each integrally formed.

In FIG. 2a, the internal buffer 4 has its inner and outer peripheries indicated by dash-dotted lines. Although the outline of the gate electrode film 3 is not shown in order to avoid complication of the drawing, its shape roughly follows the outlines of the cathode electrode film 2 and the metal film 22. In Figure a, the outer circumferences of the metal film 22 and the internal buffer 4 do not match, but this is for the sake of ease of illustration, and in reality, as shown in Figure b, they almost match. There is.

The semiconductor substrate 1 of this embodiment has a diameter of 35 mm on the internal buffer 4 side, a combined diameter of regions A and C of 30 mm, and a width of region C of 2.5 mm. The dimensions of each semiconductor layer are as follows. Each n-type emitter layer 14 has a width of 300 μm and a length of 6
mm, and there are 72 pieces in total. Its thickness is 15 μm. The thickness of the p-type base layer 13 is 30μ
The thickness of the m and n type base layer 12 is 180 μm, the thickness of the p type emitter layer 11 is 45 μm, and the thickness of the n ⁺ type layer 211 is 50 μm.

This semiconductor substrate 1 was manufactured in the following steps using a semiconductor substrate made of n-type silicon having a specific resistance of 50 Ω-cm as a starting material. Selectively pre-deposit phosphorus from one main surface of the semiconductor substrate so that the surface sheet resistance is 2Ω/□.
Then, it was stretched and expanded to form an n ⁺ type layer 211. Next, gallium was pre-deposited over the entire surface from the pair of main surfaces so that the surface sheet resistance was 22 Ω/□, and then stretched and diffused to simultaneously form the p-type base layer 13 and the p-type emitter layer 11. The portion of the semiconductor substrate that has not been diffused through the above steps becomes the n-type base layer 12. next,
Boron is applied from the other main surface of the semiconductor substrate (exposed main surface of the p-type base layer) so that the surface sheet resistance is 11Ω/
The n-type emitter layer 14 and the n ⁺ -type layer 214 were simultaneously formed by diffusion to form a □. Subsequently, the other main surface of the semiconductor substrate was selectively etched by 25 μm to form a recess to which the gate electrode film 3 was to be attached. The etching solution used was a mixture of nitric acid, hydrofluoric acid, and acetic acid.

After the semiconductor substrate 1 was manufactured as described above, a tungsten plate anode electrode was brazed to one main surface of the semiconductor substrate 1 using a gold-antimony alloy. next,
A cathode electrode film 2, a gate electrode film 3, and a metal film 22 are formed on the exposed parts of the n-type emitter layer 14, p-type base layer 13, and n ⁺ -type layer 214 on one main surface, respectively, to a thickness of 13 μm by aluminum vapor deposition. formed to a thickness.

Note that the space between the cathode electrode film 2, gate electrode film 3, and metal film 22 on one main surface is covered with a SiO ₂ film formed before these are vapor-deposited, but for the sake of simplification of the drawing, Not shown.

The cathode electrode film 2 and the metal film 22 have a thickness of 1
A tungsten internal buffer 4 having a diameter of 2 mm is mounted, and each cathode electrode film 2 and metal film 22 are electrically connected. Copper external electrodes (not shown) are brought into contact with the internal buffer 4 and anode electrode 5, respectively, and together with an insulating tube (not shown) that airtightly connects the pair of external electrodes, they form an envelope. . A gate electrode lead (not shown) is connected to the gate electrode film 3, and the gate electrode lead is connected to the central hole of the internal buffer, a groove provided in the adjacent external electrode, and a hole penetrating the insulating cylinder. led to the outside. The GTO thyristor fabricated in this way has a rating of 800V and 300A.

In this embodiment, a pressure of approximately 1000 kg is applied between a pair of external electrodes, and this pressure causes electrical and thermal changes between the external cathode electrode and the internal buffer 4, and between the internal buffer 4 and the cathode electrode film 2. Achieving contact. In this embodiment, not only the cathode electrode film 2 but also the metal film 22 having the same height as the cathode electrode film 2 are pressed against the internal buffer 4 at the same time. Therefore, a pressure of about 1000 kg is applied not only to the cathode electrode film 2 but also to the metal film 22, and the pressure per unit area decreases.

In this example, each cathode electrode film 2 has a width of approximately 0.2 mm and a length of approximately 6 mm, and 72 of them are formed, so the total area of the cathode electrode film 2 is approximately
It is ^86.4mm2 . Conventionally, this area alone supported a pressure of approximately 1000 kg, resulting in a pressure of approximately 1160 kg/cm ² being applied to the cathode electrode membrane. Although good electrical and thermal contact can be made at this pressure, the creep phenomenon is likely to occur, and the above-mentioned drawbacks cannot be avoided.

In contrast, in this embodiment, the metal film 22 shares the pressure. The metal film 22 is annular and has an inner diameter of about 30 mm.
mm, and the outer diameter is approximately 35 mm, so its area is approximately 255 mm ²
Therefore, the total area of the cathode electrode film 4 is approximately 341
^mm2 . Therefore, in this example, only about 293 kg/cm ² of pressure is applied to the cathode electrode film 2. This pressure is a value sufficient to achieve good electrical and thermal contact with the internal buffer, and at the same time to a level that does not cause deformation of the aluminum cathode electrode film 2 due to the creep phenomenon to be a practical problem. can be suppressed up to

In fact, when we conducted a comparative experiment with the conventional example shown in Figure 1 and this example at a pressure of 1000 kg, we found that the GTO
The electrical characteristics and heat dissipation properties of the thyristor were both good, but at room temperature -125℃
As a result of a thermal fatigue test in which the gate and cathode were short-circuited after approximately 10,000 cycles in the conventional example, it was noticeable that the GTO thyristor of this example experienced a short circuit between the gate and the cathode after approximately 10,000 cycles. No failures occurred even after 10,000 cycles. Conventional GTO with short circuit between gate and cathode after testing
When the thyristor was disassembled and investigated, it was revealed that the cathode electrode film had been deformed and was in contact with the gate electrode film.

In this embodiment, the metal film 22 and the semiconductor region (pressure adjustment region) immediately below the metal film 22 are designed not to serve as a main current path. Let me explain the reason. Since the purpose of the pressure regulating region is to bear the pressure contact force, it is desirable to have a larger area than the individual cathode electrode films 2. Furthermore, in order to effectively utilize a certain area of the semiconductor substrate 1, it is preferable that the semiconductor substrate 1 is not divided into smaller parts like the cathode electrode film 2, but rather has a rather wide area. However, in semiconductor switching devices such as GTO thyristors, one emitter, which is the main current path, is subdivided in order to perform turn-off operations reliably and at high speed. Therefore, if the pressure regulating region is also used as a current path, that part (especially the adjacent gate electrode film 3
This results in the inconvenience that the turn-off operation may not be performed or may be significantly delayed at the farthest point from the point.

In this embodiment, as a means for this purpose, as shown in FIG. 2, no p-type emitter layer is provided in the pressure regulating region B, and the number of laminated layers is reduced by one layer.
An n ⁺ type layer 211 is provided instead. In this way, even if a forward voltage is applied between the metal film 22 and the anode electrode 5, holes will not be injected from the anode side, so no current path will occur.

In order to ensure this effect, an isolation area C is provided in this embodiment. Region C has the following two effects. In this region C, p is directly connected to region B.
No mold emitter layer is provided. This prevents the main current from passing between the metal film 22 and the anode electrode 5 in an oblique direction of the semiconductor substrate 1. To do this, the width of the region C must be set to the width of the n-type base layer 1
It is preferable that the thickness be 2 or more. Further, it is more preferable that the diffusion length of minority carriers in the n-type base layer 12 is longer than that. In the case of this example, good results were obtained by setting the width of region C to about 1 mm or more.
Next, a gate electrode film 3 is formed on the exposed portion of one main surface of region C. Thereby, even if a small amount of main current flows in region B, this main current can be completely turned off by the gate electrode film 3 in this portion.

The pressure regulating region B of this embodiment is provided along the outer periphery of the semiconductor substrate 1, and the internal buffer 4
contact all parts of the outer periphery of the Therefore, there is no accident where the parallelism between the internal buffer and the semiconductor substrate 1 is not maintained and they come into contact, which was a drawback of the conventional example described above.

FIG. 3 shows another embodiment of the invention.

In the figure, parts equivalent to those in FIG. 2 are designated by the same reference numerals as in FIG.

In this embodiment, four pressure regulating regions B are arranged at equal intervals in the circumferential direction so that the metal films 22 formed on their surfaces are approximately concentric with the cathode electrode film group. In this embodiment, since the pressure regulating region B is arranged in parallel with the cathode electrode film 2, the semiconductor substrate 1
The pressure regulating region B can be introduced without increasing the outer diameter of the pressure regulating region B. In addition, in FIG. 3, the cathode electrode film 2 is arranged concentrically and radially for convenience, but the shape of the cathode electrode film 2 may vary depending on how the gate external electrode is taken out or the electrical characteristics of the GTO thyristor are designed. For example, it may be modified into a spiral shape, a non-concentric radial shape, etc. In such cases,
According to the concept of this embodiment, the pressure regulating region B can be formed by dividing the cathode electrode film 2 as appropriate.

FIG. 3b shows an enlarged view of the main part of the - section in FIG. 3a.

Each symbol corresponds to FIG. 2a.

The functions and effects of the pressure regulating region B and the isolation region C are the same as in FIG.

This embodiment employs a structure in which a part of the p-type emitter layer 11 of the thyristor region A is replaced with an n ⁺ -type region 111. The n ⁺ -type region 111 short-circuits the pn junction between the p-type emitter layer 11 and the n-type base layer 12 to the anode electrode 5, and has the effect of shortening the turn-off time of the GTO thyristor. This n ⁺ type region 111 is formed only in a part of the p type emitter layer 11 that corresponds directly below the n type emitter layer 14, and in this point it is essentially the same as the n ⁺ type layer 211 in the pressure regulating region B. different. It goes without saying that this n ⁺ type region 111 can also be applied to the embodiment shown in FIG.

The above two embodiments do not require any special means to form the pressure regulating region B and the isolation region C, and can be formed at the same time as the thyristor region A by only making some modifications to the manufacturing process of the thyristor region A. The cathode electrode film 2 and the metal film 2
This is a preferred embodiment of the present invention because the heights of 2 can be matched without any special consideration. However, the present invention can take various forms other than the above-described embodiments. Specific examples thereof will be explained below.

First, in order to ensure that the pressure regulating region B is a non-operating region, crystal defects are introduced into the region B by heavy metal atoms such as gold or platinum, and by radiation irradiation such as electron beams or gamma rays, and these defects are removed as lifetime killers. Therefore, it is effective to significantly shorten the carrier lifetime in region B. This measure can also be applied to isolated area C. Further, it is also possible to sufficiently introduce the lifetime killer into the region B and make the region C unnecessary.

Next, the parts of the pressure regulating region B and the isolation region C adjacent to the anode electrode 5 are shown in FIGS. 2b and 3b.
Instead of using the n ⁺ type layer 211 shown in Figure 2, a type with an impurity concentration close to the extreme (general term for n ^- type and p ^- type) is used.
It is possible to provide a semiconductor layer so that substantially no carrier injection from this layer occurs.

FIG. 4 shows still another embodiment of the present invention.

In this embodiment, the p-type base layer 13 of the thyristor region A is not included in the pressure regulating region B, and the semiconductor region adjacent to the metal film 22 of the pressure regulating region B is set as the p-type region 61, and the p-type base layer 13 is Layer 13 and p-type region 61 are separated by n-type base layer 12. By doing this, the pressure regulating region B does not become a path for the main current, and even when a turn-on or turn-off voltage is applied between the gate and cathode electrodes, the p-type region 61 and the n-type base layer 12
between the n-type base layer 12 and the p-type base layer 1
Since the pn junction between the metal film 22 and the gate electrode film 3 is reverse biased, no current flows between the metal film 22 and the gate electrode film 3.
It does not change the electrical characteristics of the GTO thyristor. Note that the planar shape of this embodiment is the same as that shown in FIG. 3, so a description thereof will be omitted. It is of course possible to apply the structure of this embodiment to the structure shown in FIG.

In each of the embodiments described so far, the cathode electrode film is provided to protrude more than the gate electrode film, and a flat internal buffer is applied. The electrode film and the gate electrode film are arranged side by side on the same plane,
The effects of the present invention can also be obtained by using an internal buffer in which the portion that contacts the cathode electrode film and the surface of the pressure regulating region is made more protruding than the other portions.

Further, in each of the above embodiments, an internal buffer is provided between the cathode external electrode and the cathode electrode film. However, even if an internal buffer does not exist, when a large-area anode electrode and an anode external electrode are pressure-welded without brazing, A disharmony occurs in the pressure welding forces, resulting in the same problems. For example, if the pair of external electrodes is made of a copper-carbon fiber composite material or a material with a low thermal expansion coefficient such as tungsten or molybdenum, the internal buffer can be omitted. The present invention can therefore be applied even in such cases.

Furthermore, the conductivity types of each semiconductor layer of the semiconductor substrate are n and p.
Needless to say, it is also applicable to semiconductor substrates of opposite polarity obtained by reversing the polarity.

As described in detail above, according to the present invention, good electrical and thermal contact can be achieved between the electrode parts,
Moreover, it is effective in providing a highly reliable pressure contact type semiconductor device.

[Brief explanation of the drawing]

Fig. 1 shows a conventional GTO thyristor, a is a plan view, b is a vertical sectional view along the - cutting line of a, Fig. 2 shows a GTO thyristor according to an embodiment of the present invention, a is a plan view, b is a vertical cross-sectional view taken along the -cutting line in a, FIG. 3 shows a GTO thyristor according to still another embodiment of the present invention, where a is a plan view, and b is an enlarged cross-sectional view of the main part along the -cutting line in a. 4 are enlarged sectional views of essential parts of a GTO thyristor according to still another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor base, 2... Cathode electrode film, 3... Gate electrode film, 4... Internal buffer, 5... Anode electrode, 6, 7... External electrode, 22... Metal film.

Claims (1)

[Claims] 1. Three pn junctions are formed by sequentially stacking an anode emitter layer, an anode base layer, a cathode base layer, and a cathode emitter layer with different conductivity types between a pair of main surfaces. , a semiconductor substrate in which a cathode-side base layer and a cathode-side emitter layer are exposed on the cathode-side main surface, and a gate electrode film and a cathode electrode film formed on the cathode-side base layer and the cathode-side emitter layer, respectively;
In a pressure contact type semiconductor device having a plate-shaped electrode member that contacts the cathode electrode film under pressure and another electrode member that contacts the anode side main surface of the semiconductor substrate, the semiconductor substrate is connected to the cathode side electrode. an operating region consisting of a four-layer laminated structure of both the emitters and both bases between the membrane and the other electrode member; and an operating region consisting of a four-layer laminated structure of the emitters and the bases, and the emitter on the cathode side between the metal film provided on the main surface of the cathode side and the other electrode member. The electrode member is characterized in that it has a pressure regulating region that cannot become a current path due to the three-layer laminated structure of the base layer and both base layers, and the plate-shaped electrode member is brought into pressure contact with the metal film. Semiconductor equipment. 2 Between a pair of main surfaces, an anode side emitter layer, an anode side base layer, a cathode side base layer, and a cathode side emitter layer having mutually different conductivity types are sequentially laminated to form three p-n junctions, and three pn junctions are formed on the cathode side main surface. a semiconductor substrate in which a cathode-side base layer and a cathode-side emitter layer are exposed; a gate electrode film and a cathode electrode film formed on the cathode-side base layer and the cathode-side emitter layer, respectively;
In a pressure contact type semiconductor device having a plate-shaped electrode member that contacts the cathode electrode film under pressure and another electrode member that contacts the anode side main surface of the semiconductor substrate, the semiconductor substrate is connected to the cathode side electrode. an operating region consisting of a four-layer laminated structure of both the emitters and both bases between the membrane and the other electrode member; and an operating area on the cathode side between the metal film provided on the main surface on the cathode side and the other electrode member. It has a laminate structure of three layers: a semiconductor layer of the same conductivity type as the base layer and separated from the cathode base layer via the anode base layer, the anode base layer, and the anode emitter layer. Therefore, it has a pressure regulation area that cannot become a current path,
A semiconductor device characterized in that the plate-shaped electrode member is brought into pressure contact with the metal film.