JPS6226612B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a receiver switching circuit that switches between a plurality of receivers and one signal demodulator.

For some types of satellite command receivers, the reception status changes depending on the satellite's attitude.
Requires multiple antennas and receivers connected to them. On the other hand, due to limitations on the weight and power consumption that can be mounted on an artificial satellite, it is not possible to carry multiple command demodulators. Therefore, means is required to switch the outputs of a plurality of receivers and connect them to one command demodulator.

As a means of this connection, if each receiver has a squelch circuit that turns off the receiver output when there is no reception input, it is possible to add the outputs of multiple receivers and connect them to one command demodulator. Conceivable.

However, if the squelch circuit of one receiver malfunctions and there is no signal received by this receiver,
Since this receiver only transmits noise, it has the disadvantage of deteriorating the signal-to-noise ratio (SN ratio) of the output signal of other normal receivers.

The present invention solves the above-mentioned drawbacks, and automatically disconnects a receiver that does not transmit a received signal or a malfunctioning receiver from a demodulator among a plurality of receivers, and replaces the output signal of other normal receivers. The purpose of the present invention is to provide a receiver switching circuit that does not degrade the signal-to-noise ratio of the receiver.

The present invention includes a switch provided for each receiver to disconnect or disconnect the received signal of the receiver, an adder for adding up the outputs of the respective switches, and a demodulator to which the output of the adder is applied. The receiver switching circuit is characterized by comprising means for controlling the switch based on a lock status signal indicating the synchronization state of the demodulator.

This will be explained below with reference to the drawings.

The figure is a configuration diagram of a circuit according to an embodiment of the present invention. In the figure, 1 and 2 are receivers, and 3 is a demodulator.
The output of the receiver 1 is connected to an analog switch 6 via a received signal input terminal 5. Further, the output of the receiver 2 is connected to an analog switch 8 via a received signal input terminal 7. Both analog switches 6
and 8 are each connected to the input of analog adder 10. The output of this analog adder 10 is
It is connected to the input of the demodulator 3 via the signal output terminal 11.

A lock status signal indicating the synchronization state of the demodulator 3 is applied from the demodulator 3 to an input of an up-down counter 14 via a lock status input terminal 12. This up/down counter 1
The most significant bit (hereinafter referred to as "MSB") output of 4 is connected to the control input of the analog switch 6 and the inverter 15. This inverter 15
The output of is connected to the control input of the analog switch 8. In addition, from the least significant bit (hereinafter referred to as "LSB") of the up-down counter 14 to the MSB 1
The outputs of the lower bits are connected to the input of the NOR circuit 16.

The output of this NOR circuit 16 is connected to one input of a NAND circuit 18. Also, this NAND circuit 18
The terminal 12 is connected to the other input.
The output of this NAND circuit 18 is connected to one input of an AND circuit 19. The other input of the AND circuit 19 is connected to a terminal 20 to which an external clock signal is input. The output of this AND circuit 19 is connected to the clock input CL of the up-down counter 14.

With this configuration, the up-down counter 14
When the MSB of is high level, the analog switch 6 is closed and the analog switch 8 is opened, so the output signal of the receiver 1 input to the terminal 5 is
The signal is supplied to the demodulator 3 via the adder 10 and the signal output terminal 11. When the receiver 1 receives a radio wave, the received signal subjected to phase shift keying (PSK) is supplied to the demodulator 3, and the demodulator 3 is subjected to phase synchronization. At this time, the lock status signal is output from the demodulator 3, the signal input from the lock status input terminal 12 changes from low level to high level, and the up/down counter 14 changes from the up count mode to the down count mode. Furthermore, when the up-down counter 14 continues to count down and all bits from the LSB to the next lower bit of the MSB become low level, the output of the NOR circuit 16 becomes high level, so the output of the NAND circuit 18 becomes low level. Therefore, the clock signal from the terminal 20 is inhibited by the AND circuit 19, and the output of the up-down counter 14 is input to the lock status input terminal 12.
This state does not change until the lock status signal goes low.

Next, when the receiver 1 no longer receives radio waves, the signal supplied to the demodulator 3 disappears, and the lock status signal of the demodulator 3 becomes low level, so the signal sent from the lock status input terminal 12 becomes low level. Become. When the signal from the lock status input terminal 12 goes low, the output of the NAND circuit 18 goes high, and the clock signal from the terminal 20 causes the up-down counter 1 to
4 starts the up count and the output of the NOR circuit 16 changes to low level. As the up-count continues, the MSB of the output of the up-down counter 14 changes from high level to low level, analog switch 6 opens, analog switch 8 closes, and the output of receiver 2 changes to adder 10 and signal It is supplied to the demodulator 3 via the output terminal 11.

If receiver 2 is also not receiving radio waves,
The up-down counter 14 continues to count up and returns to the MSB of the output of the up-down counter 14.
goes from low level to high level. Furthermore, if the receiver 2 is receiving radio waves, the demodulator 3 outputs a lock status signal and the up/down counter 14
is in down count mode. At this time, if all bits from the LSB to the next lower bit of the MSB become low level, the output of the NAND circuit 18 becomes low level, the clock signal from the terminal 20 is prohibited, and the output signal of the receiver 2 is transmitted to the demodulator 3. remains supplied.

In such a configuration, if a receiver fails, a normal signal is not output from the receiver output, so the failed receiver will not continue to be selected.

In the above embodiment, an example is shown in which there are two receivers, but the number of receivers is not limited to two, but may be three or more.

Further, logic circuits other than the up-down counter can also perform similar operations using the lock status signal as a reference.

As explained above, if multiple receivers and demodulators are connected using the means of the present invention, even if one of the multiple receivers fails, the output of the failed receiver will be will not continue to be selected, and will not degrade normal received signals output from other receivers.

Since this receiver switching operation is performed automatically, there is an advantage that a malfunctioning receiver can be automatically disconnected when used in an unmanned receiving device, especially a receiving device for a space rocket or an artificial satellite.

[Brief explanation of the drawing]

The figure is a configuration diagram of a circuit according to an embodiment of the present invention. 1, 2... Receiver, 3... Demodulator, 5... Received signal input terminal, 6... Analog switch, 7...
Received signal input terminal, 8...Analog switch, 1
0...Analog adder, 11...Signal output terminal,
12...Lock status input terminal, 14...Up-down counter, 15...Inverter, 16
...NOR circuit, 18...NAND circuit, 19...AND circuit, 20...terminal.

Claims (1)

[Claims] 1. Receiver switching, which is provided for each receiver and includes a switch that connects or disconnects the received signal of this receiver, an adder that adds the outputs of each switch, and a demodulator that receives the output of this adder. A receiver switching circuit comprising means for controlling said switch based on a lock status signal indicating a synchronization state of said demodulator.