JPS6228584B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device with extremely high reliability.

Generally, a semiconductor substrate on which a transistor or the like is formed is usually sealed with a sealing body such as a ceramic package (including a method of sealing a ceramic package with glass), a ceramic package using a metal cap, or a plastic package. . Among these packages, there are a number of ceramic materials used in ceramic packages.
Contains uranium, thorium, etc. at ppm level.

On the other hand, plastic packaging materials use fine particles such as alumina called filler, and the filler also contains the above-mentioned impurities.

These impurities, for example, 16th proceedings
of reliability physics (1978), p. 33, it is known to emit alpha rays and cause malfunctions (called soft errors) in dynamic memory circuits constructed within semiconductor pellets. .

By the way, it has been found that soft errors caused by α rays also occur in various memory circuits described below.

First, there is a case of a static type MOS memory cell circuit as shown in FIG. This cell circuit is constituted by a diffusion region (dotted line) formed in the semiconductor substrate 1 and a wiring layer formed on the surface of the semiconductor substrate 1, as shown in the plan view of FIG. Note that FIG. 2 only shows the wiring layer of the power supply line VL and word line WL, which are made of a diffusion region (dotted line) formed in the semiconductor substrate 1 and a polycrystalline silicon layer formed on the surface thereof. . The bit line b and the ground line G in FIG. 1, which are omitted to complicate the drawing, are made of an aluminum layer and are connected to the surface of the semiconductor substrate 1 through an insulating layer so as to cross the power supply line VL and word line WL. is formed.

Therefore, in the semiconductor memory device shown in FIG. 2 that constitutes one cell circuit as shown in FIG.
Assume that MOS transistor Q ₁ is turned off, while MOS transistor Q ₂ is turned on and holds information of "1". If the α rays emitted from the package in such a state hit the drain diffusion region D ₁ of the transistor Q ₁ (connection point A in Figure 1),
A pair of holes and electrons is generated within the semiconductor substrate directly under this drain diffusion region _D1 . On the other hand, in this semiconductor memory device, a positive power supply voltage _VDD is applied to the power supply line VL, and since the MOS transistor _Q1 is off, the drain diffusion region D is applied with a potential level approximately equal to the power supply voltage _VDD . It will be done. Therefore, negative electrons are induced into this drain diffusion region _D1 . Therefore, the potential of the gate of MOS transistor Q ₂ (connection point A in FIG. 1) connected to this drain diffusion region D ₁ decreases, and the potential of the gate of MOS transistor Q ₁ (connection point A in FIG.
The potential will be lower than the potential at connection point B) in the figure.

As a result, MOS transistor _Q1 turns on,
The MOS transistor _Q2 is turned off, and the information of "1" is inverted to the information of "0".

Similarly, even if this semiconductor memory device holds "0" information, it will be inverted to "1" information by being hit by α rays. In other words, when MOS transistor Q ₁ is on and MOS transistor Q ₂ is off, when α rays emitted from the package hit the drain diffusion region D ₂ of transistor Q ₂ (connection point B in Figure 1). , for the same reason as above, this time the drain diffusion region
The potential at the gate of the MOS transistor Q ₁ (connection point B in FIG. 1) connected to D ₂ decreases and becomes lower than the potential at the gate of the MOS transistor Q ₂ (connection point A in FIG. 1).

As a result, MOS transistor _Q1 turns off,
The MOS transistor _Q2 turns on, and the information of "0" is inverted to the information of "1".

Next is the case of a dynamic 16K-bit NMOS memory circuit.

FIG. 3 shows part of the circuit. In the figure,
Dummy cell DMC ₁ is used to compare the voltage levels of memory cells MC ₃ and MC ₅ with sense amplifier AMP ₁ , while dummy cell DMC ₃ is used to compare the voltage levels of memory cell MC ₁ with sense amplifier AMP ₁ . used. Similarly, dummy cell
DMC ₂ is used to compare the voltage levels of memory cells MC ₄ and MC ₆ with sense amplifier AMP ₂ .
On the other hand, dummy cell DMC ₄ is used to compare the voltage level of MC ₂ with sense amplifier AMP ₂ . Note that AD ₁ and AD ₂ indicate address circuits.

In a semiconductor memory device constituting such a memory circuit, it goes without saying that alpha rays emitted from the package may hit the memory cells _or dummy cells, causing malfunctions _. It also occurs where. Especially this sense amplifier AMP ₁ , AMP ₂
It was observed that the soft errors occurring in the memory cell and dummy cell portions were extremely high compared to the soft errors occurring in the memory cell and dummy cell portions. The reason for this is that the area of one sense amplifier is considerably larger than that of one cell, and the data lines DL ₁ ,
This is thought to be because DL ₂ is a diffusion layer and has a high probability of being hit by alpha rays.

Next, a soft error that occurs when the sense amplifier of this memory circuit is hit by alpha rays emitted from the package will be explained using the voltage fluctuation characteristic diagram shown in FIG.

Suppose that information "0" in the memory cell MC3 in FIG. ₃ is read out.

First, by the signal of clock pulse _φ1 ,
Turn on MOS transistors Q ₅ and Q ₆ . As a result, the data lines DL ₁ and DL ₂ are precharged to the V _DD level, that is, the "1" level. t ₁ in FIG. 4 is the precharge start time. After precharging is completed, information is read. At the start of reading (t ₂ ), the word line WD ₁ of the dummy cell and the word line W ₂ of the memory cell are selected, and the MOS transistor Q ₇ of the dummy cell DMC ₁ and the MOS transistor Q ₈ of the memory cell MC ₃ are turned on. At this time, the voltage levels of the data lines DL ₁ and DL ₂ fall as shown in FIG. The capacitance value of capacitor C ₁ of dummy cell DMC ₁ is the capacitance value of capacitor C 1 of cell MC ₃ .
The capacitance value is approximately 1/2 that of C ₂ . Therefore, immediately after _t2 , the voltage level of data line _DL1 falls as shown by the solid line. On the other hand, the voltage level of the data line _DL2 decreases as shown by the dashed line. When MOS transistor _Q9 is turned on by the clock pulse _φ3 to amplify the voltage level difference between data lines _DL1 and _DL2 ,
In other words, if the α rays emitted from the package do not hit the data line DL ₁ before the amplification start time t ₃ , the data lines DL ₁ and DL ₂ after the amplification start time t ₃ elapse.
The voltage level becomes as shown by dotted lines DL ₁ ′ and DL ₂ ′ in FIG. Then, amplification is completed at time _t4 .

However, when the α rays hit the data line DL ₁ at time t _x shown in _FIG . Voltage level drops. Then, at time t _y , the voltage levels of data lines DL ₁ and DL ₂ are reversed.

Therefore, the voltage levels of data lines DL ₁ and DL ₂ after the start of amplification (t ₃ ) are as shown in DL ₁ and DL ₂ in FIG. 4. Then, at the time _t4 when amplification is completed, the voltage levels of data lines _DL1 and _DL2 are completely inverted.

Therefore, originally, the potential of the data line _DL1 is approximately at the _VDD level, turning on the MOS transistor _Q10 , and the potential of the data line _DL2 is at the ground level, turning on the MOS transistor Q10.
This turns off transistor _Q11 , but α
Due to the influence of the line, the potential of data line DL ₁ becomes ground level and the potential of data line DL ₂ becomes V _DD level.
MOS transistor _Q10 is turned off and MOS transistor _Q11 is turned on.

As a result, the information in the memory cell _MC3 is read out as if it were "1".

Such a problem also occurred when reading out information "1" in the memory cell _MC3 . In this case, information inversion occurred when the α rays hit the data line DL ₂ .

The above-mentioned sense amplifier is constructed in and on the semiconductor substrate 1 as shown in FIG.
In the figure, a gate electrode made of polycrystalline silicon
G ₁₁ , source diffusion region S ₁₁ and drain diffusion region
_D11 constitutes a MOS transistor _Q11 . and a gate electrode made of polycrystalline silicon.
G ₁₂ , source diffusion region S ₁₂ and drain diffusion region
_D12 constitutes a MOS transistor _Q12 . Gate electrode G ₁₁ is connected to drain diffusion region D ₁₂ at connection point J ₁ . On the other hand, the gate electrode _G12 has a drain diffusion region at the connection point _J2 .
Connected to D ₁₁ . The second aluminum wiring layer 2 connected to the drain diffusion region (not shown) of the MOS transistor Q ₉ is connected to the source diffusion regions S ₁₁ and S ₁₂ at connection points J ₃ and J ₄ . has been done. Note that drain diffusion regions _D11 and _D12 are connected to data lines DL1 and _D12 , respectively.
Extends laterally for use as DL ₂ .

Furthermore, this applies to static type bipolar memory cell circuits.

The bipolar memory cell circuit, as shown in FIG. 6, consists of resistors R ₁ , R ₂ , diodes D ₁ , D ₂ and multi-emitter transistors Q ₁₂ , Q ₁₅ . The common connection line of the diodes D ₁ and D ₂ and the resistors R ₁ and R ₂ is connected to the word line W ⁺ , and one emitter of each of the transistors Q ₁₂ and Q ₁₃ is connected to the bit line.
B ₀ and B ₁ , and the other emitter is connected to an information holding constant current source I _ST .

The above-mentioned bipolar memory cell circuit is known, and the retention of information is performed by the stable state of a bistable circuit, that is, a flip-flop circuit. In other words, if a potential difference occurs between the bases of transistors Q ₁₂ and Q ₁₃ , positive feedback occurs due to collector-base cross-coupling, and among transistors Q ₁₂ and Q ₁₃ ,
The transistor with the higher base potential is turned on, and the other transistor is turned off, resulting in a stable state.

In DC terms, this information retention ability is determined by the potential difference between the bases of transistors Q ₁₂ and Q ₁₃ in a stable state. In terms of AC, the ease of reversing a flip-flop circuit depends on the transistor's current amplification factor, high frequency gain bandwidth, base resistance, parasitic capacitance, etc., and the resistance R connected to the collector of the transistor as a load. ₁ , _R2 or diode
Determined by the high frequency characteristics of D ₁ and D ₂ .

In order to improve the information retention ability, it is sufficient to deteriorate the high frequency characteristics caused by these. However, in order to increase the speed of bipolar memory, it is necessary to improve these characteristics, and in ultra-high-speed bipolar memory, the information retention ability inevitably decreases as the speed increases.

In such a bipolar memory, information inversion can be explained as follows.

In a semiconductor substrate that constitutes a bipolar memory circuit, when alpha rays emitted from a package that seals the substrate enter the substrate, pairs of holes and electrons are generated due to the energy loss of the alpha rays during the incident path. These hole-electron pairs are collected through the collector-base region depletion layer and collector region-substrate depletion layer of the transistor, and generate a noise current. In FIG. 6, when transistor Q ₁₂ is on and transistor Q ₁₃ is off, in normal operation, the collector potential V _C1 of transistor Q ₁₃ is equal to the collector potential of transistor Q ₁₂ , as shown by the solid line in FIG. V _C
It has a potential relationship higher than ₀ . However, holes generated when α rays enter the substrate
Among the electron pairs, those collected by the depletion layer between the collector and base regions are the noise current I _o
occurs. This noise current I _o is a transistor
Flows through the parasitic capacitance C _TC2 between the collector and base regions of Q ₁₃ , and the collector potential V _C1 of the transistor Q ₁₃
to bring down. As a result, the flip-flop memory cell begins to perform an inversion operation, as shown by the dotted line and the dashed-dotted line in FIG. 7, and shifts to one stable state.
Then, a complete information reversal occurs.

In this way, memory circuits that use charges to retain information malfunction due to alpha rays.

Therefore, it is an object of the present invention to eliminate the occurrence of malfunctions in memory circuits due to the above-mentioned alpha rays, and in particular, to prevent malfunctions in static type memory circuits.

In order to achieve the above object, the basic technical idea of the present invention is to prevent alpha rays emitted by the package from penetrating into the semiconductor substrate. The reason is that resin is coated on the area that forms part of the memory circuit.

The semiconductor memory device of the present invention uses a polyimide resin such as polyimide resin or polyimide isoindolo quinazolinedione resin (hereinafter referred to as PII resin) to attenuate and absorb α particles flying from impurities contained in the package material.
Therefore, the resin coating film serving as the damping material and absorbing material is required to be thick enough to prevent α particles from passing through. This thickness should be at least 10 μm in order to prevent variations in device characteristics.
It is preferably 30 μm or more, and more preferably 30 μm or more. The ability to prevent the transmission of alpha rays is not limited to the resin coating film, but is an ability generally possessed by insulating films. However, it is extremely difficult to deposit insulating films such as silicon dioxide, phosphorous glass, silicon nitride, and aluminum oxide, which have been conventionally used in semiconductor devices, on a semiconductor substrate to a thickness of 10 μm or more. That is, these insulating films formed by vapor phase growth have extremely high film stress, and if the film is deposited to a thickness of several micrometers or more, cracks will occur. Furthermore, with the sputtering method, it is possible to deposit with a relatively low incidence of cracks, but the deposition rate is extremely low at several hundred Å/min, and it is practically impossible to deposit more than 10 μm. On the other hand, with polyimide resin and PII resin, the film stress is extremely small at approximately 4 kgf/mm ² , and the breaking strain is approximately 30 kgf/mm2.
%, which is about an order of magnitude larger than the inorganic insulating film.
A thick film of several tens of μm can be formed without generating any cracks. On the other hand, some polymer resins have film-forming properties similar to those of the above-mentioned polyimide resin and PII resin films. Generally, the sealing process for ceramic packages is performed at a high temperature of around 450°C, so heat resistance that can withstand this temperature is required. Examples of resins that satisfy this property include the above resins.

In other words, as shown in Fig. 8, when thermogravimetric loss analysis was performed on various polymer resins, silicone resin 13, epoxy resin 14, etc.
Weight loss begins at 250°C, but polyimide resin 12 starts to lose weight at 500°C. PII resin 11
It also has excellent heat resistance, with a weight retention rate of approximately 70% at 600°C. Thus, polyimide resin or PII resin has heat resistance to the above-mentioned high temperature process.

In addition, in PII resin or polyimide resin, the content of impurities such as uranium and thorium, which are sources of alpha rays, is extremely low at about 0.1 to several ppb (analysis of these impurities was based on activation analysis). Therefore, PII resin or polyimide resin is
At the same time, the resin itself can be easily obtained with extremely high purity, and therefore the amount of alpha rays it generates is extremely small. On the other hand, it can be said that organic polymer materials generally have a lower content of impurities than inorganic materials. However, as an example of organic polymer materials,
In the case of polyethylene resin, the uranium content is
It is relatively high at 40 to 50 ppb, and organic polymer materials are not necessarily suitable. Both PII resin and polyimide resin can be said to be excellent materials in terms of the content of impurities such as uranium and thorium.
However, as mentioned above, from the point of view of heat resistance, PII
Resin is even more preferred.

In addition, polyimide resin here refers to a polymer obtained by reacting aromatic diamine and aromatic tetracarboxylic dianhydride, and PII resin refers to a polymer obtained by reacting aromatic diamine, aromatic tetracarboxylic acid, and aromatic diamino dianhydride. It refers to a polymer obtained by reacting with carbonamide, and all of them are well known. PII resin is described in detail, for example, in Japanese Patent Publication No. 48-2956, including its manufacturing method.

Since the area forming part of the memory circuit formed within the semiconductor substrate is affected by alpha rays, the resin coating film provided to prevent alpha rays from entering is present at least on that area. Must.

Note that, if the semiconductor substrate has an insulating layer, an electrode, a wiring layer, etc., these are also included. The semiconductor device of the present invention is mainly constructed from a monolithic integrated circuit.

Ceramic encapsulation is a well-known technology in the semiconductor technology field.
All can be used. These ceramic packages include, for example, those called corfired dips and ceramic dips. These ceramics usually have alumina ceramics as their main component, and glass, whose main component is lead glass, is used for adhesion between ceramics in the ceramic type.

Polyimide resins and PII resins may contain a small amount (about several ppm) of alkaline impurities such as Na. In this case, if a resin film such as polyimide resin is formed on the semiconductor substrate and subjected to high-temperature heat treatment, pinholes etc. will be present in the insulating film provided on the surface of the semiconductor thin plate forming the semiconductor substrate.
The alkali impurities may enter from this portion and change the device characteristics. In order to prevent this, it is effective to form a phosphorous glass film or a silicon nitride film having a high ability to block alkali ions on the semiconductor substrate and to interpose it between the film and the polyimide resin.

The semiconductor memory device of the present invention described above includes (1) a step of coating a semiconductor substrate with polyimide resin or PII resin to a thickness of 10 μm or more, and (2) sealing the semiconductor substrate coated with the resin with a sealing body such as a ceramic material. It can be easily manufactured by a manufacturing method including a step of stopping.

Hereinafter, the effects of the present invention will be explained in more detail with reference to Examples.

Example 1 This will be explained with reference to FIG. P-type silicon semiconductor substrate 21 constituting a memory circuit as described above
A PII resin 23 having a film thickness of 4 to 37 μm was formed on top.

The PII resin is applied onto the wafer using the spion method, heat-treated at 200℃ for 1 hour to semi-cure it, and
The bonding pad portion 22 was opened by photoetching with an aqueous hydrazine solution. Then 350℃
It was heat treated at 450°C for 10 minutes for 1 hour to completely cure it. The heat treatment is preferably carried out in nitrogen or an inert gas. PIQ (registered trademark of Hitachi Chemical Co., Ltd.) was used as the PII resin. PIQ is also used as the PII resin in each of the following examples. Further, this substrate was sealed in a ceramic package (ceramic package) as shown in FIG.

In addition, in FIG. 9, 20 is an N-type diffusion region constituting a part of the memory circuit, 21' is an insulating film,
For example, the SiO ₂ film 21'' is a wiring conductor layer, and 24 is a bonding wire connected to an external connection lead.
Further, in FIG. 10, reference numeral 25 indicates an external connection lead, and reference numeral 26 indicates molten glass to which the ceramic 27 is bonded in a sealed manner.

Example 2 PII resin is formed on a semiconductor substrate by another method as follows.

As shown in FIG. 11, a P-type silicon semiconductor substrate 61 is die-bonded to a predetermined position of the package, bonding wires 62 are bonded by wire bonding for external connection, and then a PII resin 63 is potted. ,200℃
Heat treatment was performed at 350°C for 1 hour, and at 450°C for 10 minutes. The PII resin film thickness is approximately 40 to 70 μm. It is desirable to extend the insulating film 61' over the scribe region 64.

Example 3 As mentioned above, polyimide resin has some
It may contain alkaline impurities such as Na (approximately ppm). At this time, if a polyimide resin film is formed on the semiconductor substrate and a high temperature heat treatment is applied,
Particularly, as shown in FIG. 7, a portion 7 is formed due to the presence of pinholes in the insulating film 71' or misalignment of the mask between the opening of the insulating film 71' and the metal wiring 71''.
6 or the like, impurity ions may enter from these parts and change the device characteristics. Therefore, it is effective to form a phosphorous glass or silicon nitride film with high alkali ion blocking ability on the semiconductor substrate and interpose it between the film and the polyimide resin. That is, as shown in FIG. 12, a phosphorus glass 73 is formed on a silicon semiconductor substrate 71 by vapor phase growth, and a polyimide film 74 is further formed thereon. Ringarasu is
Phosphorus concentration of 30mol% to 12mol%, film thickness 0.3μm
The thickness is preferably about 1.5 μm. That is, the ability of the phosphorus glass membrane to block alkali ions depends on the phosphorus concentration, and becomes effective at 3 mol% or more. On the other hand, as the phosphorus concentration increases, the hygroscopicity increases, so
If it exceeds 12 mol%, defects such as Al wiring corrosion will begin to occur. The thickness of the phosphor glass should be at least 0.3 μm in order to almost completely cover the semiconductor substrate.
The above is necessary, and 1.5 μm is the range that does not cause cracks due to the tensile stress of the phosphor glass itself.
The following are desirable. The polyimide resin film 74 was formed by the same method as in Example 1. If there is no such phosphor glass and there are pinholes or mask misalignment 76 in the insulating film 71' as described above, a polyimide resin film 74 is formed and heat treatment is performed at a high temperature of 400°C or higher. A yield drop of about 40% was observed. However, in this example, it was confirmed that the yield did not decrease due to the formation of the polyimide resin film, and furthermore, it was confirmed that malfunctions due to α-ray irradiation did not occur.

A similar effect is confirmed when a silicon nitride film is used instead of the phosphorus glass 73. Silicon nitride film is made by sputtering method, plasma CVD
(Plasma Enhanced Chemical Vapor
Although it can be formed by a known method, it is preferable to use a plasma CVD method. Film thickness is 0.2~
A range of 3 μm is desirable. The thickness of the silicon nitride film is still required to be 0.2 μm or more in order to almost completely cover the semiconductor substrate, and the upper limit is preferably about 3 μm so that plasma etching of the silicon nitride film described below can be easily performed. .
This silicon nitride film can be opened, for example, by plasma etching using CF ₄ . 12th
In the figure, 75 indicates a bonding wire.

In this example, it is clear that the same effect as this one can be achieved even if PII resin is used instead of polyimide resin, and if these resins are formed by the potting method.

Example 4 In this example, a polyimide resin or PII resin film 8 having openings 82 shown in FIG.
1 was pressure-bonded onto a silicon semiconductor wafer. Openings 82 correspond to bond pad areas and scribe areas of the semiconductor body. This film is 50-500 μm thick. Also in this example, soft errors caused by α-ray irradiation did not occur. The effect of the present invention on ceramic sealing is also clear. Note that this semiconductor wafer is film 8
1 and then diced into pellets.

Example 5 The area of the silicon wafer other than the element area (area where soft errors occur due to α-ray irradiation) was covered with a printing mesh screen, and a prepolymer solution of PIQ (concentration 19.5%, viscosity Approximately 10,000 cp) and then at 200℃
Bake for 60 minutes, then bake for another 60 minutes at 350°C until the thickness
A 50 μm PIQ film was formed only on the element region. In this example as well, no soft errors occurred due to α-ray irradiation. Furthermore, the effect on the soft error occurrence rate after ceramic sealing is clear.

Example 6 After a pellet (semiconductor package) was mounted on a base of a package, the pellet was covered with an uncured or semi-cured film of polyimide resin or PII resin, and then baked at 350° C. for 30 minutes. An uncured film was obtained as follows. In other words, a polyimide prepolymer solution (e.g., Toray's Trenice #3000) or PIQ prepolymer is applied onto a flat substrate (e.g., a glass plate), and then baked at 100°C to substantially volatilize the solvent and reduce the thickness. An uncured film of 30-50 μm was formed. Next, use a sharp cutter to cut the pellet into a size that matches the size of the pellet, and peel it off the substrate.
This was placed over the pellets that make up the memory circuit. Similarly, if you bake at 200℃,
Again, a semi-cured film with a thickness of 30 to 50 μm is obtained. When uncured and semi-cured films are placed over the pellets and baked at 350°C for 30 minutes, these films adhere well to the pellets.
It fully functions as a protective film. Furthermore, the semiconductor memory device manufactured in this manner did not suffer from any soft errors due to alpha ray irradiation.

As a variation of this method, polyimide resin or
This effect is not lost even if instead of a PII resin film piece, a Si piece of the same shape is adhered onto the active element region with a polyimide resin or a PII resin prepolymer and cured with heat. At this time, it is desirable to oxidize the surface of the Si piece using a thermal oxidation method.
Furthermore, before bonding with polyimide or PII resin prepolymer, for example, Al is applied to the surface of the thermal oxide film.
Forming a heat-treated product of the chelate compound improves adhesion.

According to the present invention, the following specific effects were obtained.

Figure 14 shows a _16K -bit NMOS dynamic RAM (Random Access
Memory) In the semiconductor substrate that constitutes the circuit,
It is a graph showing the number of soft errors caused by α rays when a PII resin film is coated on this substrate and when it is not coated with a PII resin film.

In this figure, the vertical axis shows the number of soft errors per minute, and the horizontal axis shows the intensity of the α-ray source (Americium) with an energy of 5 MeV. The unit of α-ray source intensity is microcurie (μ
Ci).

Semiconductor substrate E not coated with PII resin film at all
As shown in the figure, a considerable amount of soft errors occur. On the other hand, in semiconductor substrate F coated with a 20μ PII resin film, the number of soft errors was reduced to about 1/10 ⁴ when the α-ray source intensity was only 10 ² μCi compared to semiconductor substrate E. Furthermore, in the case of semiconductor substrate G coated with a PII resin film of 50μ, the deterioration was approximately 1/10 ⁶ or less compared to semiconductor substrate E.

By the way, the maximum energy of alpha rays is 8.8 MeV, and the energy to create hole-electron pairs within a silicon semiconductor substrate is 3.7 eV. Therefore, the number of electrons created by one α ray is approximately 2.4×10 ⁶ . Therefore, regardless of whether it is a MOS, bipolar, dynamic type, or static type, a semiconductor memory device that forms information "1" or "0" in a memory circuit with a charge smaller than this will always be affected.

Therefore, it is extremely effective to apply the present invention to such a semiconductor memory device.

The present invention is a CCD (Charge-Coupled-Device)
The present invention can also be applied to semiconductor memory devices constituting memory circuits such as. In the case of a CCD, a diffusion region is not provided, and a portion of the semiconductor substrate surface itself forms part of the memory circuit.

It should be noted that the sealing body applied to the present invention is not limited to the one made of the above-mentioned ceramic material,
It also includes those made of metal materials or insulating materials such as glass.

Furthermore, a ladder polymer, such as Phenyl Ladder Silicon, is used as a heat-resistant resin.

[Brief explanation of the drawing]

Figure 1 is a static MOS memory cell circuit diagram, Figure 2 is a plan view of a semiconductor substrate that forms part of the cell circuit in Figure 1, and Figure 3 is a partial circuit diagram of a 16K-bit dynamic NMOS memory circuit. , 4th
The figure is a voltage level change characteristic diagram in the memory circuit of Figure 3, Figure 5 is a plan view of a semiconductor substrate that constitutes the sense amplifier part of Figure 3, Figure 6 is a bipolar memory cell circuit diagram, and Figure 7 is a diagram of the semiconductor substrate that constitutes the sense amplifier part of Figure 3. Fig. 8 is a graph showing the thermogravimetric reduction curves of various polymer resins; Fig. 9 is a semiconductor formed with a polymer resin film according to an embodiment of the present invention. FIG. 10 is a cross-sectional view of a semiconductor memory device in which the semiconductor substrate is sealed in ceramic, and FIG. 11 is a cross-sectional view of a semiconductor substrate in which a resin film is formed on the semiconductor substrate by a potting method in an embodiment of the present invention. 12 is a sectional view of a semiconductor substrate in which a phosphorous glass or silicon nitride film and a resin film are formed on a semiconductor substrate in an embodiment of the present invention, and FIG. 13 is a sectional view of a semiconductor substrate in an embodiment of the present invention. FIG. 14 is a plan view of the semiconductor substrate with a resin film crimped onto it, and is a graph showing the number of soft errors caused by alpha rays when the semiconductor substrate is coated with a PII resin film and when it is not coated with a PII resin film. 1, 21, 61, 71... Semiconductor substrate constituting a memory circuit, 11, 23, 63... PII resin, 1
2,74...Polyimide resin film, 20...Diffusion region,
27... Ceramic, 73... Phosphorus glass film, 76...
Mask misalignment portion, 81...Resin film, 82...
Open hole.

Claims (1)

[Claims] 1. A region constituting a static type memory circuit is formed in a semiconductor region, and the region constituting the static type memory circuit is coated with a resin material selected from the group consisting of polyimide resin and polyimide-isoindolo-quinazolinedione resin. A semiconductor memory device characterized in that the semiconductor region is covered with a film and the semiconductor region covered with the coating film is sealed with an insulator.