JPH0544189B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor memory device with extremely high reliability.

Generally, a semiconductor substrate on which a transistor or the like is formed is usually sealed with a sealing body such as a ceramic package (including a method of sealing a ceramic package with glass), a ceramic package using a metal cap, or a plastic package. . Among these packages, there are a number of ceramic materials used in ceramic packages.
Contains uranium, thorium, etc. at ppm level.

On the other hand, plastic packaging materials use fine particles such as alumina called filler, and the filler also contains the above-mentioned impurities.

These impurities, for example, 16th proceedings
of reliability physics (1978), p. 33, it is known to emit alpha rays and cause malfunctions (called soft errors) in dynamic memory circuits constructed within semiconductor pellets. .

By the way, it has been found that soft errors caused by α rays also occur in various memory circuits described below.

First, there is a case of a static type MOS memory cell circuit as shown in FIG. This cell circuit is constituted by a diffusion region (dotted line) formed in the semiconductor substrate 1 and a wiring layer formed on the surface of the semiconductor substrate 1, as shown in the plan view of FIG. Note that FIG. 2 only shows the wiring layer of the power supply line VL and word line WL, which are made of a diffusion region (dotted line) formed in the semiconductor substrate 1 and a polycrystalline silicon layer formed on the surface thereof. . The bit line b and the ground line G in FIG. 1, which are omitted to complicate the drawing, are made of an aluminum layer and are connected to the surface of the semiconductor substrate 1 through an insulating layer so as to cross the power supply line VL and word line WL. is formed.

Therefore, in the semiconductor memory device shown in FIG. 2 that constitutes one cell circuit as shown in FIG.
Assume that MOS transistor Q ₁ is turned off, while MOS transistor Q ₂ is turned on and holds information of "1". If the α rays emitted from the package in such a state hit the drain diffusion region D ₁ (connection point A in Figure _{1) of the transistor Q 1 ,} holes and A pair with electron occurs. on the other hand,
In this semiconductor memory device, a positive power supply voltage V _DD is applied to the power supply line VL, and since the MOS transistor Q ₁ is off, the drain diffusion region D has a
A potential level approximately equal to the power supply voltage V _DD is given. Therefore, negative electrons are induced into this drain diffusion region _D1 . Therefore, the MOS transistor Q ₂ connected to this drain diffusion region D ₁
The potential at the gate (connection point A in Figure 1) decreases,
The potential becomes lower than the potential of the gate of MOS transistor _Q1 (connection point B in FIG. 1).

As a result, MOS transistor _Q1 turns on,
The MOS transistor _Q2 is turned off, and the information of "1" is inverted to the information of "0".

Similarly, in this semiconductor memory device, “0”
Even if it holds the information of "1", it will be reversed to the information of "1" by being hit by alpha rays. In other words, when MOS transistor Q ₁ is on and MOS transistor Q ₂ is off, when α rays emitted from the package hit the drain diffusion region D ₂ of transistor Q ₂ (connection point B in Figure 1). , for the same reason as above, this time the drain diffusion region
The potential at the gate of the MOS transistor Q ₁ (connection point B in FIG. 1) connected to D ₂ is added and becomes lower than the potential at the gate of the MOS transistor Q ₂ (connection point A in FIG. 1).

As a result, MOS transistor _Q1 turns off,
The MOS transistor _Q2 turns on, and the information of "0" is inverted to the information of "1".

Next is the case of a dynamic 16K-bit NMOS memory circuit.

FIG. 3 shows part of the circuit. In the figure,
Dummy cell DMC ₁ is used to compare the voltage levels of memory cells MC ₃ and MC ₅ with sense amplifier AMP ₁ , while dummy cell DMC ₃ is used to compare the voltage levels of memory cell MC ₁ with sense amplifier AMP ₁ . used. Similarly, dummy cell
DMC ₂ is used to compare the voltage levels of memory cells MC ₄ and MC ₆ with sense amplifier AMP ₂ .
On the other hand, dummy cell DMC ₄ is used to compare the voltage level of MC ₂ with sense amplifier AMP ₂ . Note that AD ₁ and AD ₂ indicate address circuits.

In a semiconductor memory device constituting such a memory circuit, it goes without saying that malfunctions occur when the memory cells or dummy cells are hit by _alpha rays emitted from the package _. It also occurs where. Especially this sense amplifier AMP ₁ , AMP ₂
It was observed that the soft errors occurring in the memory cell and dummy cell portions were extremely high compared to the soft errors occurring in the memory cell and dummy cell portions. The reason for this is that the area of one sense amplifier is considerably larger than that of one cell, and the data lines DL ₁ ,
This is thought to be because DL ₂ is a diffusion layer and has a high probability of being hit by alpha rays.

Next, a soft error that occurs when the sense amplifier of this memory circuit is hit by alpha rays emitted from the package will be explained using the voltage fluctuation characteristic diagram shown in FIG.

Suppose that information "0" in the memory cell MC3 in FIG. ₃ is read out.

First, _the MOS
Turn on transistors Q ₅ and Q ₆ . As a result, the data lines DL ₁ and DL ₂ are precharged to the V _DD level, that is, the "1" level. t ₁ in FIG. 4 is the precharge start time. After precharging is completed, information is read. At the start of reading (t ₂ ), the dummy cell word line WD ₁ and the memory cell word line W ₂ are selected, and the dummy cell
MOS transistor Q ₇ of DMC ₁ and MOS transistor Q ₈ of memory cell MC ₃ are turned on. At this time, the voltage levels of the data lines DL ₁ and DL ₂ fall as shown in FIG. The capacitance value of capacitor C ₁ of dummy cell DMC ₁ is the capacitance value of capacitor C ₂ of cell MC ₃ .
The value is approximately 1/2 that of the capacitance value of . Therefore, immediately after _t2 , the voltage level of data line _DL1 drops as shown by the solid line. On the other hand, the data line
The voltage level of DL ₂ decreases as shown by the dash-dotted line. Since the voltage level difference between data lines DL ₁ and DL ₂ is amplified, α is released from the package when MOS transistor Q ₉ is turned on by the clock pulse φ ₃ signal, that is, before the amplification start time t ₃ has elapsed. If the line does not hit the data line DL ₁ , the voltage levels of the data lines DL ₁ and DL ₂ after the start of amplification t ₃ will be as shown by dotted lines DL ₁ ′ and DL ₂ ′ in FIG. 4. Then, amplification is completed at time _t4 .

However, when the α ray hits the data line DL ₁ at time t _x shown in Figure 4, the static type described above occurs.
For the same reason as in the case of the semiconductor memory device forming the MOS memory cell circuit, the voltage level of the data line _DL1 decreases. Then, at time _ty , the voltage levels of data lines DL ₁ and DL ₂ are reversed.

Therefore, the voltage levels of data lines DL ₁ and DL ₂ after the start of amplification (t ₃ ) are as shown in DL ₁ and DL ₂ in FIG. 4. Then, at the time _t4 when amplification is completed, the voltage levels of data lines _DL1 and _DL2 are completely inverted.

Therefore, originally, the potential of the data line DL ₁ is approximately at the V _DD level, turning on the MOS transistor Q ₁₀ , and the potential of the data line DL ₂ is at the ground level.
This turns off the MOS transistor _Q11 , but due to the influence of alpha rays, the potential of the data line _DL1 becomes the ground level and the potential of the data line _DL2 becomes the _VDD level, so the MOS transistor _Q10 is turned off. ,
MOS transistor _Q11 turns on.

As a result, the information in the memory cell _MC3 is read out as if it were "1".

Such a problem also occurred when reading out information "1" in the memory cell _MC3 . In this case, information inversion occurred when the α rays hit the data line DL ₂ .

The above-mentioned sense amplifier is constructed in and on the semiconductor substrate 1 as shown in FIG.
In the figure, a gate electrode made of polycrystalline silicon
G ₁₁ , source diffusion region S ₁₁ and drain diffusion region
_D11 constitutes a MOS transistor _Q11 . and a gate electrode made of polycrystalline silicon.
G ₁₂ , source diffusion region S ₁₂ and drain diffusion region
_D12 constitutes a MOS transistor _Q12 . Gate electrode G ₁₁ is connected to drain diffusion region D ₁₂ at connection point J ₁ . On the other hand, the gate electrode _G12 has a drain diffusion region at the connection point _J2 .
Connected to D ₁₁ . And it is connected to the drain diffusion region (not shown) of MOS transistor _Q9 . The second aluminum wiring layer 2 is connected to the source diffusion regions _S11 and _S12 at connection points _J3 and _J4 . Note that drain diffusion regions _D11 and _D12 are connected to data lines DL1 and _D12 , respectively.
Extends laterally for use as DL ₂ .

Furthermore, this is the case for bipolar memory cell circuits.

As shown in FIG. 6, the bipolar memory cell circuit consists of resistors R ₁ , R ₂ , diodes D ₁ , D ₂ , and multi-emitter transistors Q ₁₂ , Q ₁₃ .
The common connection line of the diodes D ₁ , D ₂ and the resistors R ₁ , R ₂ is connected to the word line W ⁺ and the transistors Q ₁₂ , Q ₁₃
One emitter of each is a bit line.
B ₀ and B ₁ , and the other emitter is connected to an information holding constant current source I _ST .

The above-mentioned bipolar memory cell circuit is known, and the retention of information is performed by the stable state of a bistable circuit, that is, a flip-flop circuit. In other words, if a potential difference occurs between the bases of transistors Q ₁₂ and Q ₁₃ , positive feedback is applied due to collector-base cross-coupling, and among transistors Q ₁₂ and Q ₁₃ ,
The transistor with the higher base potential is turned on, and the other transistor is turned off, resulting in a stable state.

In DC terms, this information retention ability is determined by the potential difference between the bases of transistors Q ₁₂ and Q ₁₃ in a stable state. In addition, in terms of AC, the ease of inversion of a flip-flop circuit depends on the transistor's current amplification factor, high frequency gain bandwidth, base resistance, parasitic capacitance, etc., and the resistance connected as a load to the collector of the transistor ( It is determined by the high frequency characteristics of R ₁ , R ₂ ) and diodes (D ₁ , D ₂ ).

In order to improve the information retention ability, it is sufficient to deteriorate the high frequency characteristics caused by these. However, in order to increase the speed of bipolar memory, it is necessary to improve these characteristics, and in ultra-high-speed bipolar memory, the information retention ability inevitably decreases as the speed increases.

In such a bipolar memory, information inversion can be explained as follows.

In a semiconductor substrate that constitutes a bipolar memory circuit, when alpha rays emitted from a package that seals the substrate enter the substrate, pairs of holes and electrons are generated due to the energy loss of the alpha rays during the incident path. These hole-electron pairs are collected through the collector-base region depletion layer and collector region-substrate depletion layer of the transistor, and generate a noise current. In FIG. 6, when transistor Q ₁₂ is on and transistor Q ₁₃ is off, in normal operation, the collector potential V _C1 of transistor Q ₁₃ is equal to the collector potential of transistor Q ₁₂ , as shown by the solid line in FIG.
It has a higher potential relationship than V _C0 . However, among the hole-electron pairs generated when α rays enter the substrate, the ones collected by the depletion layer between the collector and base regions become noise currents.
Generate _Io . This noise current I _o is a transistor
Flows through the parasitic capacitance C _TC2 between the collector and base region of Q ₁₃ , and the collector potential V _C1 of transistor Q ₁₃
to bring down. As a result, the flip-flop memory cell begins to perform an inversion operation, as shown by the dotted line and the dashed-dotted line in FIG. 7, and shifts to one stable state.
Then, a complete information reversal occurs.

In this way, memory circuits that use charges to retain information malfunction due to alpha rays.

Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor memory device that can eliminate the above-mentioned malfunction of a memory circuit caused by alpha rays.

The semiconductor memory device manufactured according to the present invention uses a polyimide resin or a polyimide-isoindolo-quinazolinedione resin (hereinafter referred to as PII resin) to attenuate and absorb α particles flying from impurities contained in a package material. Therefore, the resin coating film serving as the damping material and absorbing material is required to be thick enough to prevent α particles from passing through. In order to prevent variations in device characteristics, this thickness is preferably at least 10 μm or more, and more preferably 30 μm or more. The ability to prevent the transmission of alpha rays is not limited to the resin coating film, but is an ability generally possessed by insulating films. However, it is extremely difficult to deposit insulating films of silicon dioxide, phosphorous glass, silicon nitride, aluminum oxide, etc. conventionally used in semiconductor devices to a thickness of 10 μm or more on a semiconductor substrate. That is, these insulating films formed by vapor phase growth have extremely high film stress, and if the film is deposited to a thickness of several micrometers or more, cracks will occur. Furthermore, with the sputtering method, it is possible to deposit with a relatively low incidence of cracks, but the deposition rate is extremely low at several hundred Å/min, and it is practically impossible to deposit more than 10 μm. On the other hand, with polyimide resin and PII resin, the film stress is approximately 4 kg.
f/mm ² , which is extremely small, and the breaking strain is about 30%, which is about an order of magnitude larger than that of the inorganic insulating film, so it is several tens of microns.
A thick film of m thick can be formed without any cracks. On the other hand, some polymer resins have film-forming properties similar to those of the above-mentioned polyimide resin and PII resin films. Generally, the sealing process for ceramic packages is performed at a high temperature of around 450°C, so heat resistance that can withstand this temperature is required. Examples of resins that satisfy this property include the above resins.

In other words, as shown in Fig. 8, when thermogravimetric loss analysis was performed on various polymer resins, silicone resin 13, epoxy resin 14, etc.
Weight loss begins at 250°C, but polyimide resin 12 starts to lose weight at 500°C. PII resin 11
It also has excellent heat resistance, with a weight retention rate of approximately 70% at 600°C. Thus, polyimide resin or PII resin has heat resistance to the above-mentioned high temperature process.

In addition, in PII resin or polyimide resin, the content of impurities such as uranium and thorium, which are sources of alpha rays, is extremely low at about 0.1 to several ppb (analysis of these impurities was based on activation analysis). Therefore, PII resin or polyimide resin is
At the same time, the resin itself can be easily obtained with extremely high purity, and therefore the amount of alpha rays it generates is extremely small. On the other hand, it can be said that organic polymer materials generally have a lower content of impurities than inorganic materials. However, as an example of organic polymer materials,
In the case of polyethylene resin, the uranium content is
It is relatively high at 40 to 50 ppb, and organic polymer materials are not necessarily suitable. Both PII resin and polyimide resin can be said to be excellent materials in terms of the content of impurities such as uranium and thorium. However, as mentioned above, PII resin is more preferable in terms of heat resistance.

In addition, polyimide resin here refers to a polymer obtained by reacting aromatic diamine and aromatic tetracarboxylic dianhydride, and PII resin refers to a polymer obtained by reacting aromatic diamine, aromatic tetracarboxylic acid, and aromatic diamino dianhydride. It refers to a polymer obtained by reacting with carbonamide, and all of them are well known. PII resin is described in detail, for example, in Japanese Patent Publication No. 48-2956, including its manufacturing method.

Since the area forming part of the memory circuit formed within the semiconductor substrate is affected by alpha rays, the resin coating film provided to prevent alpha rays from entering is present at least on that area. Must.

Note that, if the semiconductor substrate has an insulating layer, an electrode, a wiring layer, etc., these are also included. The semiconductor device of the present invention is mainly constructed from a monolithic integrated circuit.

Ceramic encapsulation is a well-known technology in the semiconductor technology field.
All can be used. These ceramic packages are, for example, what is called a corrugated dip or a ceramic dip. These ceramics usually have alumina ceramics as their main component, and glass, whose main component is lead glass, is used for adhesion between ceramics in the ceramic type.

Polyimide resins and PII resins may contain a small amount (about several ppm) of alkaline impurities such as Na. In this case, if a resin film such as polyimide resin is formed on the semiconductor substrate and subjected to high-temperature heat treatment, pinholes etc. will be present in the insulating film provided on the surface of the semiconductor thin plate forming the semiconductor substrate.
The alkali impurities may enter from this portion and change the device characteristics. In order to prevent this, it is effective to form a phosphorous glass film or a silicon nitride film having a high ability to block alkali ions on the semiconductor substrate and to interpose it between the film and the polyimide resin.

Hereinafter, the effects of the present invention will be explained in more detail with reference to Examples.

Example 1 This will be explained with reference to FIG. P-type silicon semiconductor substrate 21 constituting a memory circuit as described above
A PII resin film 23 having a thickness of 4 to 37 μm was formed thereon.

PII resin is applied onto the wafer by spin-on method, heat treated at 200℃ for 1 hour to semi-cure,
The bonding pad portion 22 was opened by photoetching with an aqueous hydrazine solution. Then 350℃
It was heat treated at 450°C for 10 minutes for 1 hour to completely cure it. The heat treatment is preferably carried out in nitrogen or an inert gas. PIQ (registered trademark of Hitachi Chemical Co., Ltd.) was used as the PII resin. In each of the following examples, PIQ is also used as the PII resin. Further, this substrate was sealed in a ceramic package (ceramic package) as shown in FIG.

In addition, in FIG. 9, 20 is an N-type diffusion region constituting a part of the memory circuit, 21' is an insulating film,
For example, the SiO ₂ film 21' is a wiring conductor layer, and 24 is a bonding wire connected to an external connection lead.
Further, in FIG. 10, reference numeral 25 indicates an external connection lead, and reference numeral 26 indicates molten glass to which the ceramic 27 is bonded in a sealed manner.

Example 2 PII resin is formed on a semiconductor substrate by another method as follows.

As shown in FIG. 11, a P-type silicon semiconductor substrate 61 is die-bonded to a predetermined position of the package, a bonding wire 62 is bonded by wire bonding for external connection, and then a PII resin 63 is bonded. ,200℃
Heat treatment was performed at 350°C for 1 hour, and at 450°C for 10 minutes. The PII resin film thickness is approximately 40 to 70 μm. It is desirable to extend the insulating film 61' over the scribe region 64.

Example 3 As mentioned above, polyimide resin contains a small amount (several ppm
It may contain alkaline impurities such as Na. At this time, if a polyimide resin film is formed on the semiconductor substrate and subjected to high-temperature heat treatment, pinholes may be present in the insulating film 71' as shown in FIG.
If a portion 76 or the like occurs due to a 1" mask misalignment, impurity ions may enter from these portions and change the device characteristics. Therefore, phosphorus glass or phosphorus glass with high alkali ion blocking ability may be used. It is effective to form a silicon nitride film on a semiconductor substrate and interpose it between the silicon nitride film and the polyimide resin. That is, as shown in FIG.
A phosphorus glass 73 is formed on a silicon semiconductor substrate 71 by vapor phase growth, and a polyimide film 74 is further formed thereon. Phosphorus glass is 3mol%~
At a phosphorus concentration of 12 mol%, the film thickness is preferably about 0.3 μm to 1.5 μm. In other words, the ability of the phosphorus glass membrane to block alkali ions depends on the phosphorus concentration, and
% or more, the effect becomes apparent. On the other hand, as the phosphorus concentration increases, the hygroscopicity increases, so if it exceeds 12 mol%, defects such as corrosion of Al wiring begin to occur.
The thickness of the phosphor glass needs to be at least 0.3 .mu.m or more in order to almost completely cover the semiconductor substrate, and is preferably 1.5 .mu.m or less so that cracks do not occur due to the tensile stress of the phosphor glass itself.
The polyimide resin film 74 was formed by the same method as in Example 1. There is no such ring glass,
If there are pinholes or mask misalignment 76 in the insulating film 71' as described above, forming a polyimide resin film 74 and applying high-temperature heat treatment at 400°C or higher will reduce the yield by about 0.5 to 40%. It was seen.
However, in this example, it was confirmed that the yield did not decrease due to the formation of the polyimide resin film, and furthermore, it was confirmed that malfunctions due to α-ray irradiation did not occur.

A similar effect is confirmed when a silicon nitride film is used instead of the phosphorus glass 73. Silicon nitride film is made by sputtering method, plasma CVD
(Plasma Enhanced Chemical Vapor
Although it can be formed by a known method, it is preferable to use a plasma CVD method. Film thickness is 0.2~
A range of 3 μm is desirable. The film thickness of silicon nitride is
Again, in order to cover the semiconductor substrate almost completely.
The thickness is required to be 0.2 .mu.m or more, and the upper limit is preferably about 3 .mu.m so that plasma etching of the silicon nitride film described below can be easily performed. This silicon nitride film can be opened, for example, by plasma etching using CF ₄ . In FIG. 12, 75 indicates a bonding wire.

In this example, it is clear that the same effect as this one can be achieved even if PII resin is used instead of polyimide resin, and if these resins are formed by the potting method.

Example 4 In this example, a polyimide resin or PII resin film 8 having openings 82 shown in FIG.
1 was pressure-bonded onto a silicon semiconductor wafer. Openings 82 correspond to bond pad areas and scribe areas of the semiconductor body. This film is 50-500 μm thick. Also in this example, soft errors caused by α-ray irradiation did not occur. The effect of the present invention on ceramic sealing is also clear. Note that this semiconductor wafer is film 8
1 and then diced into pellets.

Example 5 The area of the silicon wafer other than the element area (area where soft errors occur due to α-ray irradiation) was covered with a printing mesh screen, and a prepolymer solution of PIQ (concentration 19.5%, viscosity Approximately 10,000 cp) and then at 200℃
Bake for 60 minutes, then bake for another 60 minutes at 350°C until the thickness
A 50 μm PIQ film was formed only on the element region. In this example as well, no soft errors occurred due to α-ray irradiation. Furthermore, the effect on the soft error occurrence rate after ceramic sealing is clear.

Example 6 After a pellet (semiconductor device) was mounted on the base of a package, the pellet was covered with an uncured or semi-cured film of polyimide resin or PII resin, and then baked at 350°C for 30 minutes. An uncured film was obtained as follows. In other words, a polyimide prepolymer solution (e.g., Toray's Trenice #3000) or PIQ prepolymer is applied onto a flat substrate (e.g., a glass plate), and then baked at 100°C to substantially volatilize the solvent and reduce the thickness. An uncured film of 30-50 μm was formed. Next, use a sharp cutter to cut the pellet into a size that matches the size of the pellet, and peel it off the substrate.
This was placed over the pellets that make up the memory circuit. Similarly, if you bake at 200℃,
Again, a semi-cured film with a thickness of 30 to 50 μm was obtained. When uncured and semi-cured films are placed on top of pellets and baked at 350°C for 30 minutes,
These films adhere well to the pellets and function well as a protective film. Furthermore, the semiconductor memory device manufactured in this manner did not suffer from any soft errors due to alpha ray irradiation.

As a variation of this method, polyimide resin or
This effect is not lost even if instead of a PII resin film piece, a Si piece of the same shape is adhered onto the active element region with a polyimide resin or a PII resin prepolymer and then thermally cured. At this time, it is desirable to oxidize the surface of the Si piece using a thermal oxidation method.
Furthermore, before bonding with polyimide or PII resin prepolymer, for example, Al is applied to the surface of the thermal oxide film.
Forming a heat-treated product of the chelate compound improves adhesion.

According to the present invention, the following specific effects were obtained.

Figure 14 shows a _16K -bit NMOS dynamic RAM (Random Access
Memory) In the semiconductor substrate that constitutes the circuit,
It is a graph showing the number of soft errors caused by α rays when a PII resin film is coated on this substrate and when it is not coated with a PII resin film.

In this figure, the vertical axis shows the number of soft errors per minute, and the horizontal axis shows the intensity of the α-ray source (Americium) with an energy of 5 MeV. The unit of alpha source intensity is microcuries (μCi).

Semiconductor substrate E not coated with PII resin film at all
As shown in the figure, a considerable amount of soft errors occur. On the other hand, although the α-ray source intensity is only 10 ² μCi, the semiconductor substrate F coated with a 20μ PII resin film is
Compared to semiconductor substrate E, the number of soft errors was reduced to about 1/10 ⁴ . Furthermore, in semiconductor substrate G coated with a PII resin film of 50 μm, the deterioration was approximately 1/10 ⁶ or less compared to semiconductor substrate E.

By the way, the maximum energy of alpha rays is 8.8 MeV, and the energy to create hole-electron pairs within a silicon semiconductor substrate is 3.7 eV. As a result, the number of electrons created by one α ray is approximately 2.4×10 ⁶ . Therefore, regardless of whether it is a MOS, bipolar, dynamic type, or static type, a semiconductor memory device that forms information "1" or "0" in a memory circuit with a charge smaller than this will always be affected.

Therefore, it is extremely effective to apply the present invention to such a semiconductor memory device.

The present invention can also be applied to a semiconductor memory device constituting a memory circuit such as a CCD (Charge-Coupled-Device). In the case of a CCD, a diffusion region is not provided, and a portion of the semiconductor substrate surface itself forms part of the memory circuit.

It should be noted that the sealing body applied to the present invention is not limited to the one made of the above-mentioned ceramic material,
It also includes those made of metal materials or insulating materials such as glass.

Furthermore, a ladder polymer, such as Phenyl Ladder Silicon, is used as a heat-resistant resin.

[Brief explanation of the drawing]

Figure 1 is a static MOS memory cell circuit diagram, Figure 2 is a plan view of a semiconductor substrate that forms part of the cell circuit in Figure 1, and Figure 3 is a partial circuit diagram of a 16K-bit dynamic NMOS memory circuit. , Fig. 4 is a voltage level change characteristic diagram in the memory circuit of Fig. 3, Fig. 5 is a plan view of the semiconductor substrate that constitutes the sense amplifier part of Fig. 3, Fig. 6 is a bipolar memory cell circuit diagram, and Fig. 7 is the voltage (potential) level change characteristic diagram in the cell circuit of Fig. 6, and Fig. 8
The figure is a graph showing thermogravimetric reduction curves of various polymer resins, FIG. 9 is a cross-sectional view of a semiconductor substrate on which a polymer resin film is formed according to an embodiment of the present invention, and FIG. 10 is a graph showing the semiconductor substrate sealed with ceramic. FIG. 11 is a cross-sectional view of a semiconductor substrate in which a resin film is formed on a semiconductor substrate by a potting method in an embodiment of the present invention, and FIG. 12 is a cross-sectional view of a semiconductor substrate in an embodiment of the present invention. FIG. 13 is a cross-sectional view of a semiconductor substrate on which a phosphorus glass or silicon nitride film and a resin film are formed; FIG. 13 is a plan view of the semiconductor substrate with a resin film pressed onto the semiconductor substrate in an embodiment of the present invention; FIG. is a graph showing the number of soft errors caused by alpha rays when a PII resin film is coated on a semiconductor substrate and when it is not coated with a PII resin film. 1, 21, 61, 71... Semiconductor substrate constituting a memory circuit, 11, 23, 63... PII resin,
DESCRIPTION OF SYMBOLS 12, 74... Polyimide resin film, 20... Diffusion region, 27... Ceramic, 73... Phosphorous glass film, 76... Mask alignment misalignment part, 81... Resin film, 82... Opening part.

Claims (1)

[Claims] 1. A step of forming a region constituting a static memory circuit in a semiconductor region on one main surface of a semiconductor wafer, a step of forming a metal wiring layer having a bonding pad portion on the region constituting the static memory circuit, forming a coating film of one resin material selected from the group consisting of polyimide resin and polyimide-isoindolo-quinazolinedione resin on one main surface of the semiconductor wafer on which the region constituting the static memory circuit is formed; 1. A method for manufacturing a semiconductor memory device, comprising the steps of dividing a semiconductor wafer into pellets and sealing the divided pellets in a ceramic package or a plastic package.