JPS6228585B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD This invention relates generally to capacitor structures, and more particularly to improved high field capacitor structures using carrier capture regions, which are particularly useful in semiconductor capacitor structures.

[Prior art]

It is generally believed that roughness or defects on the silicon surface increase the leakage current of the insulator and lead to breakdown at low voltages in metal oxide semiconductor (MOS) devices. This suggests that for thermally grown oxides on polycrystalline silicon, Applied
DJ DiMaria from Physics Letters, Vol. 27, No. 9 (November 1, 1975), pp. 505-507
and DRKerr's paper “Interface Effects and
High Conductivity and Oxides Grown From
Thermally grown oxides on polycrystalline silicon have been dramatically unveiled in ``Polycrystalline Silicon.'' This is important for various types of devices based on Si technology, such as (CCD). Such roughness generates strong local electric fields, which can lead to - Nordheim tunneling effect) It is thought that this causes strong local dark current density and breakdown at low voltages. (Structure shown in Figure 1) [Invention] Roughness on the surface of the metal substrate of a thin film capacitor This is thought to lead to breakdown at low electric fields, much in the same way as observed in the case of thermally grown oxides on polycrystalline silicon.Therefore, it is necessary to reduce the leakage current and breakdown voltage of the capacitor structure. In order to improve A carrier trapping region or layer is provided in the insulator near the SiO ₂ insulator 4. When applying the invention to a MOS structure, the trapping region or layer is
It is in the form of an electronic trap introduced inside. If there is a large local current density due to roughness, electron traps will quickly charge at points of strong electric field, thus reducing the local electric field and current. The trapping region or layer should be as close to the silicon as possible to maximize the effect of the trapped charge on the local electric field, but reverse tunneling due to trap discharge occurs in the absence of applied voltage. We must keep them far enough away to eliminate fear.

Polycrystalline silicon (poly-Si) 2 was first deposited on top of the polycrystalline Si layer 1 and then partially thermally oxidized.
In the case of MOS structures, there are specifically two ways to form the trapping region or layer. The first is to form a thin thermally grown SiO ₂ layer 4 on top of the polycrystalline Si layer 2 .
This thin thermally grown SiO ₂ layer 4 can be formed by thermal oxidation of the polycrystalline Si layer 2. thin thermal growth
A relatively thick CVD SiO ₂ layer 6 is deposited on top of the SiO ₂ layer. In this structure, the CVD SiO ₂ layer 6 acts as an electron trapping region. Second, relatively thick CVD
By depositing a very thin scavenging layer 5 on top of the thermally grown SiO ₂ layer 4 before depositing the SiO ₂ layer 6.
The electron capture efficiency of this structure can be substantially improved. The preferred metal for this layer is tungsten, but other atoms such as aluminum can also be used. This layer is not continuous and is
DR published in the August 1977 issue of Applied Physics magazine
Young, DJDiMaria and NABojarcuk's paper “Electron Trapping Characteristics of W in
As described in ``SiO ₂ '', it can be regarded as a large number of very thin dots.The present invention uses the second method described above to create a high-field capacitor that can determine the position of the electron trap very precisely. provide.

For thin film capacitors, typical substrates can be tantalum or aluminum. A substrate oxide is chemically grown on this substrate.
When the substrate is tantalum, the insulator is Ta ₂ O ₅ , but when the substrate is aluminum, the insulator is Ta 2 O 5.
_It is _Al2O3 . When applied to this structure, an electron trapping region or layer is formed by ion implantation in close proximity to the interface between the substrate and the chemically grown oxide.

Deposition of polycrystalline silicon on degenerate n-type single crystal silicon, doping of the polycrystalline and subsequent thermal oxidation is described, for example, in the article by DJ DiMaria and DR Kerr, supra. FIG. 1 shows this structure in cross section. Polycrystal as an electrode on single crystal Si substrate 1
A Si layer 2 is deposited and then a SiO ₂ insulator 4 is created by thermal oxidation. A metal electrode 7, typically aluminum, is deposited onto this SiO ₂ insulator. As shown in FIG. 1, the interface 3 between polycrystalline Si and thermal SiO ₂ is very rough and uneven. High points due to this roughness,
That is, the point closest to the metal electrode is the point where the electric field is strong. Although the average current through this interface is relatively _small , the localized large currents caused by strong electric fields at local high points can cause Surrender may occur.

In the MOS structure shown in FIG. 2, the thermal SiO ₂ layer 4 is relatively thin, with a thickness of a. This layer is polycrystalline
It can be formed by thermal oxidation of Si. On top of this relatively thin thermally grown SiO ₂ layer 4 is formed a significantly thicker pyrolysis or CVD SiO ₂ layer 6 . The thickness of the CVD SiO ₂ layer 6 is denoted by b. thermal growth
Although the SiO ₂ layer 4 does not have a large number of electron traps, the CVD SiO ₂ layer 6 has a certain electron trapping efficiency. This electron capture efficiency is considered to be related to the water content of CVD SiO ₂ .

Modifications such as those shown in FIG. 3 can substantially improve the structure shown in FIG. In FIG. 3, a tungsten layer 5 is first deposited over a relatively thin thermally grown SiO ₂ layer 4, before a thicker CVD SiO ₂ layer 6 is deposited. This tungsten layer is extremely thin, on the order of about 10 ¹⁴ atoms/cm ² , so that the layer is not continuous. This layer can be considered to be composed of a large number of tungsten dots. Although tungsten was used in the particular implementation of this invention, those skilled in the art will appreciate that other atoms, such as aluminum, may also be used.

〔Effect of the invention〕

To illustrate the advantages of the present invention, MOS structures such as those shown in FIGS. 1, 2, and 3 were fabricated and are referred to as Samples A, B, and C, respectively. These are:

Sample A Al - thermally grown SiO ₂ (450Å) - polycrystalline Si (3.5×
10 ^-3 Ωcmn) [Conventional structure shown in Figure 1] Sample B Al—CVD SiO ₂ (520Å)—Thermally grown SiO ₂ (70
Å) - Polycrystalline Si (3.5 x 10 ^-3 Ωcmn) [Structure in Figure 2] Sample C (invention) Al - CVD SiO ₂ (520 Å) - W (〓10 ¹⁴ atoms/cm ² ) - Thermal growth SiO ₂ (70Å) - Polycrystalline Si
(3.5×10 ^-3 Ωcmn) [Structure shown in Figure 3] In each sample A to C, the area of the circular aluminum gate electrode is 1.3×10 ^-2 cm ² and the thickness is about 3000 Å. It was hot. No annealing was performed after metallization. All oxide thicknesses are MOS
It was measured by the capacitance of . Dark current-applied gate voltage characteristics were measured on raw samples using a constant slope voltage or a step voltage. When experimenting with a voltage with a constant slope, the slope ratio is 5.1×
10 ^-2 MV/cm-second or 9.5× ^10-3 MV/cm-second. until the current level reaches 8×10 ^-7 A/cm ² .
A voltage ramp was used to increase the magnitude of the positive or negative bias, and when this current level was reached, the direction of the ramp was reversed. The data is shown in Figures 4 and 5.
As shown in the graphs in the figure, these graphs are
The displacement current (〓3.5×10 ⁻⁹ A/cm ² ) due to the temporal change rate of the gate voltage has been corrected. The first starting voltage for ramp-type experiments was when the electronic conduction current began to dominate the displacement current. In step voltage experiments, for either gate polarity, the sample is
The magnitude of the average electric field was increased in steps of 1 MV from 0 V. Although there are slight differences in current-voltage characteristics when looked at in detail due to differences in the accumulation of negative charges captured in the structures, the two experimental methods yielded roughly the same results.

Figures 4 through 7 clearly demonstrate that the charge trapping layer eliminates the effects of strong local electric fields due to roughness at the interface between polycrystalline silicon and thermally grown silicon dioxide. . 4 and 5, the average electric field strength (the magnitude of the gate voltage divided by the total oxide thickness of the structure) required for a given current to be measured in the external circuit is: When an electron trapping layer is present, the voltage Al ⁺ (fourth
Figure) and Al ^- (Figure 5) are also larger. Sample C
Note that the structure of sample B (with W layer) is better than the structure of sample B (without W layer). This shows that the trapping efficiency of the structure with W layer (sample C) is
This is consistent with the experimental observation that it is larger than the structure with only CVD oxide (Sample B). 520Å CVD
I of both structures of samples B and C with _two layers of SiO
-V characteristics are based on the structure of sample A (conventional structure).
The average electric field is gradually moving to higher places. Structure with CVD oxide layer on top of thermal oxide layer (Sample B)
The increased trapping efficiency compared to a structure with only thermal oxide grown on a polycrystalline silicon substrate (Sample A) is related to the water content of the high-temperature decomposition or CVD oxide. I think that the. Samples B and C
The IV characteristics of the structure are within the range of MOS structures with thermal oxide grown from single crystal silicon substrates.

The sequence of events that occurs within the structures of Samples B and C to reduce the effects of roughness appears to be as follows.

(1) When the applied gate voltage is low, a local trapping effect occurs and the roughening effect disappears rapidly.

(2) When the electric field becomes stronger, a uniform trapping effect occurs,
That shifts the IV characteristic to a higher average electric field.

From step voltage IV measurements, the local trapping effect appears to be at very low current levels (7.9×
10 ^-12 A/cm ² ) and low applied electric field (2 MV/cm)
It seems to happen. Near this current level, the IV characteristics of the structure of sample B or C are similar to those of sample A.
The characteristics of this structure are markedly different from those of other structures. This difference appears in the shape of the crosspiece (1.5 to 2 MV/cm width). Here, the current slowly increases to 7.9×10 ^-12 A/
cm ² to a level of 3.9×10 ⁻¹¹ A/cm ² .
In the structure of Sample C (with W layer), this crosspiece was wider than in the structure of Sample B (without W layer).
After the appearance of this crosspiece, the uniform trapping effect appears to become the dominant factor and govern the IV characteristics.
The data in FIGS. 4 and 5 represent this uniform capture effect.

The hysteresis appearing in the data shown in FIGS. 4 and 5 is due to electron trapping effects. Data similar to Figures 4 and 5 obtained for a MOS structure with a 563 Å thermal oxide on a single-crystal degenerate silicon substrate show that the gate polarity is It has been found that there is less hysteresis in either case of voltage polarity than is observed when is negative. In either polarity, the magnitude of hysteresis was the largest in the structure of sample C, followed by the structure of sample B, and the smallest in the structure of sample A. Fourth
The hysteresis for the sample A structure shown in the figure with positive gate bias is determined by DJDiMaria and DR
Kerr's above-mentioned paper and others have reported that the large local current density enhances local trapping within the thermal oxide layer near points of strong electric field. This is thought to be due to the In subsequent ramp voltage cycles, all structures exhibit a memory effect, with the trapping of negative charges in the previous cycle causing the IV characteristic to shift towards a higher average field at the beginning of the next cycle. I was pushed up. The rapid current increase with positive gate bias in the sample C structure indicates the beginning of a current runaway condition near destructive breakdown.

If the difference in the IV data of the structures of Samples B and C as shown in Figures 4 and 5 is due to the uniform negative charge trapping effect in the W layer, then in principle is a paper by DJ DiMaria “Determination of
Insulator Bulk Trapped Charged Densities
and Centroids From Photocurrent―Voltage
It should be possible to determine the position of this layer from the voltage difference between samples B and C using a method recently published in ``Charateristics of MOS Structures''.The relationship between this photocurrent and voltage is as follows.

/L=[1+(|ΔV _g ⁻ |L)/(|ΔV _g ⁺
|/L)] ^-1 Here, the centroid measured from the interface between Al and CVD SiO ₂・L is the total thickness of the oxide of the structure, |ΔV _g ⁺ | and |ΔV _g ⁻ | are, It is the magnitude of the change in gate voltage at a constant level of photocurrent for positive and negative gate biases, respectively. Using this equation and the experimental values of |ΔV _g ⁺ |/L and |ΔV _g ⁻ |/L from the data in FIGS. The distance from the interface with ₂ is 72 Å, which is 70 Å.
It agrees well with the measured value of Å. To avoid the current runaway region in the sample C structure when the gate bias is positive, only data for current levels lower than 3x10 ^-8 A/cm ² were used.

Figures 6 and 7 are the structures of samples A and C,
The distribution of self-healing and destructive breakdown for positive gate bias (polycrystalline Si implantation) is shown. 7th
Both distributions in sample C of the figure show very little breakdown at low average electric fields. Breakdown at low average electric fields is characteristic of thermally oxidized polycrystalline silicon surfaces, as shown for sample A in FIG. The histogram in FIG. 7 shows that, compared to a thermally oxidized single-crystal Si MOS structure, even in a capacitor with such a large area, the electric field is concentrated near the average electric field of about 8.8 MV/cm.

This maximizes the negative trapped charge and the reduction of the electric field between the polycrystalline Si and thermally grown SiO ₂ interface, while at the same time reducing the The location of the W trapping layer was chosen close to the interface between polycrystalline Si and thermally grown SiO ₂ to minimize thermal or field emission with the aid of an electric field into the conduction band. However, the W region was spaced far enough from the polycrystalline Si and thermally grown SiO ₂ interface to prevent reverse tunneling into the polycrystalline Si. Generally, the W regions should be separated by more than about 40-50 Å. On the other hand, the W region should not be placed so far from the interface between polycrystalline Si and thermally grown SiO ₂ that the effect that the trapped charges have on the electric field due to silicon surface roughness is reduced. From a practical point of view, polycrystalline Si
The maximum distance of the W region from the interface between SiO 2 and thermally grown SiO ₂ should be about 150 Å or less, preferably less than 100 Å.

Although it is very effective to use a metal such as tungsten in the trapping layer of the structure of Sample C, the structure of Sample B is constructed using other metals to reduce the current and increase the breakdown voltage according to the present invention. It has been demonstrated that it is possible to use a trapping layer of Such a trapping layer can be formed by ion implantation, vapor deposition or chemical vapor deposition. The implanted ions may be phosphorous, arsenic or aluminum. Arsenic has been found to be particularly effective in forming electron traps within thermally grown _SiO2 layers. The method of using a trapping layer to increase breakdown voltage can also be used in capacitor structures other than MOS structures. For example, it is known to make thin film capacitors from tantalum or aluminum substrates by chemically growing the oxide of the substrate as the capacitor's insulator. If tantalum is the substrate, the insulator is Ta ₂ O ₅
become. If aluminum is the substrate, the insulator is
It becomes Al ₂ O ₃ . The oxide interface between the substrate and the insulator is rough, which tends to limit the breakdown field of such thin film capacitors. In this type of structure, ion implantation allows an electron trapping region to be formed in close proximity to the interface between the substrate and the oxide insulator.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a conventional MOS structure, FIG. 2 is a sectional view of another MOS structure, FIG. 3 is a sectional view of a MOS structure according to an embodiment of the present invention, and FIG. Graphs showing the dark current density as a function of the average electric field magnitude for positive gate bias for specimens A, B and C corresponding to Figures 2 and 3; Figure 5 is for specimens A, B; A graph showing the dark current density as a function of the average electric field magnitude for negative gate biases and C as a function of the average electric field magnitude. Histogram, shown as a function of the size of
FIG. 7 is a histogram showing the percentage of dielectric breakdown events for Sample C as a function of average electric field magnitude for positive gate bias.

Claims (1)

[Claims] 1. A high-field capacitor structure comprising a pair of spaced apart electrodes and an insulating layer distributed between the pair of electrodes and having a carrier trapping region therein,
One electrode consists of a layer of polycrystalline silicon (e.g. 2), and the insulating layer comprises a relatively thin layer of silicon oxide (e.g. 4) formed by partially thermally oxidizing the polycrystalline silicon layer. , a layer (e.g. 5) of a metal selected from the group comprising tungsten and aluminum deposited even thinner on the relatively thin layer of silicon oxide, and deposited on the layer of metal; comprising a relatively thick carrier trapping layer (e.g. 6) of CVD silicon dioxide, the other electrode comprising a layer of metal (e.g. 7) deposited on the layer of CVD silicon dioxide;
A high field capacitor structure that reduces local high electric fields caused by roughness between a layer of polycrystalline silicon and a layer of silicon oxide.