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JPS6229909B2 - - Google Patents
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JPS6229909B2 - - Google Patents

Info

Publication number
JPS6229909B2
JPS6229909B2 JP55151259A JP15125980A JPS6229909B2 JP S6229909 B2 JPS6229909 B2 JP S6229909B2 JP 55151259 A JP55151259 A JP 55151259A JP 15125980 A JP15125980 A JP 15125980A JP S6229909 B2 JPS6229909 B2 JP S6229909B2
Authority
JP
Japan
Prior art keywords
resin
semiconductor device
layer
semiconductor element
ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55151259A
Other languages
Japanese (ja)
Other versions
JPS5775447A (en
Inventor
Junji Tajima
Masato Tameda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP55151259A priority Critical patent/JPS5775447A/en
Publication of JPS5775447A publication Critical patent/JPS5775447A/en
Publication of JPS6229909B2 publication Critical patent/JPS6229909B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00Arrangements for protection of devices
    • H10W42/20Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H10W42/25Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons against alpha rays, e.g. for outer space applications
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68Shapes or dispositions thereof
    • H10W70/682Shapes or dispositions thereof comprising holes having chips therein
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07551Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/931Shapes of bond pads
    • H10W72/932Plan-view shape, i.e. in top view
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 本発明は、半導装置の製造方法に係り、特に半
導体素子を放射線から保護する保護膜の形成方法
に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a protective film that protects a semiconductor element from radiation.

近年、樹脂封止型半導体装置及びセラミツク封
止型半導体装置において、これらの樹脂及びセラ
ミツクの封止材料が放出するα粒子による、半導
体装置の誤動作が問題になつている。
In recent years, malfunctions of the semiconductor devices due to α particles emitted by resin and ceramic sealing materials have become a problem in resin-sealed semiconductor devices and ceramic-sealed semiconductor devices.

従来、行われている樹脂封止型半導体装置の断
面図を第1図aに、セラミツク封止型半導体装置
の断面図を第1図bに、それぞれ示す。すなわ
ち、樹脂封止型半導体装置は、半導体素子1をリ
ードフレーム6に固定し、半導体素子の電極2,
3は、前記リードフレーム6と異なるリードフレ
ーム7,8に、アルミニウムなどの金属線4,5
によつて接続している。これらを樹脂9によつて
おおい、全体を固定している。また、セラミツク
型半導体装置第1図bは、半導体素子1を、セラ
ミツク容器10の空洞部内の金属薄板12上に固
定し、半導体素子の電極13,14をそれぞれリ
ード13,15に金属線4,5を用いて、接続
し、セラミツク又は金属製の蓋板11で封止して
いる。
A cross-sectional view of a conventional resin-sealed semiconductor device is shown in FIG. 1a, and a cross-sectional view of a ceramic-sealed semiconductor device is shown in FIG. 1b, respectively. That is, in the resin-sealed semiconductor device, a semiconductor element 1 is fixed to a lead frame 6, and electrodes 2,
3, metal wires 4, 5 such as aluminum are attached to lead frames 7, 8 different from the lead frame 6.
connected by. These are covered with resin 9 and the whole is fixed. In the ceramic type semiconductor device shown in FIG. 1B, a semiconductor element 1 is fixed on a thin metal plate 12 in a cavity of a ceramic container 10, and electrodes 13 and 14 of the semiconductor element are connected to leads 13 and 15, respectively, by metal wires 4, 5 to connect and seal with a lid plate 11 made of ceramic or metal.

このような従来の封入方式では樹脂及びセラミ
ツクなどの容器の材料から放出されるα粒子は、
半導体素子内に入射され素子内に電荷を発生させ
ることになる。とくにランダムアクセスメモリー
(RAM)などの電荷を蓄積して情報を保持する半
導体集積回路素子ではα粒子の入射で生じる電荷
によつて情報が破壊されることになる。
In such conventional encapsulation methods, alpha particles released from container materials such as resin and ceramics are
The light enters the semiconductor device and generates charges within the device. In particular, in semiconductor integrated circuit devices such as random access memories (RAMs) that store information by accumulating charges, the information is destroyed by charges generated by the incidence of alpha particles.

これらの対策としてα粒子に対する阻止能力を
有する樹脂を半導体素子表面に塗布し、保護する
方法が一般的になされている。たとえば樹脂封止
型半導体装置において第2図aに示す様に半導体
基板の表面全体にポリイミド樹脂膜17を形成す
る。しかしながらこの場合はα粒子に対する阻止
能力は充分であるが、半導体素子電極2,3とリ
ードフレーム7,8とを接続している金属線4,
5が断線しやすく、高信頼性の半導体集積回路は
得られにくかつた。一方、従来においては第2図
bに示す様に、ポリイミド樹脂17′を電極を除
いて形成する場合もあるが、樹脂17′の厚さは
30〜100μmとなるように塗布し、フオトレジス
ト技術を用いて形状形成するので、ポリイミド樹
脂膜が厚いためパターン精度が非常に悪く実用的
ではない。
As a countermeasure against these problems, a common method is to apply a resin having an ability to block α particles to the surface of the semiconductor element to protect it. For example, in a resin-sealed semiconductor device, a polyimide resin film 17 is formed over the entire surface of a semiconductor substrate as shown in FIG. 2a. However, in this case, although the blocking ability against α particles is sufficient, the metal wires 4 connecting the semiconductor element electrodes 2, 3 and the lead frames 7, 8,
5 was easily disconnected, making it difficult to obtain a highly reliable semiconductor integrated circuit. On the other hand, conventionally, as shown in FIG. 2b, polyimide resin 17' is sometimes formed excluding the electrodes, but the thickness of resin 17' is
Since the polyimide resin film is coated to a thickness of 30 to 100 μm and shaped using photoresist technology, the pattern accuracy is very poor and is not practical.

本発明の目的は、従来の半導体装置にみられる
上記の欠点を除去した樹脂封止型半導体装置及び
セラミツク封止型半導体装置の製造方法を提供す
ることにある。
An object of the present invention is to provide a method for manufacturing a resin-sealed semiconductor device and a ceramic-sealed semiconductor device that eliminates the above-mentioned drawbacks of conventional semiconductor devices.

上記の目的を達成するために、本発明ではポリ
イミド及びシリコンなどの樹脂膜を、半導体素子
のα粒子感受性の高い部分の表面に、選択的に2
層以上に形成することを特徴とする。
In order to achieve the above object, the present invention selectively applies a resin film such as polyimide or silicon to the surface of a portion of a semiconductor device that is highly sensitive to α particles.
It is characterized by being formed in more than one layer.

以下に、実施例によつて本発明を説明する。 The present invention will be explained below with reference to Examples.

第3図及び第4図は本発明をMOS型RAMに適
用した場合である。半導体素子1の表面全体に、
ポリイミド樹脂を数μm程度の厚さで塗布したの
ち、フオトレジストを用いて、メモリセル及びセ
ンスアンプなどのα粒子の影響を受けやすい部分
だけに、ポリイミド樹脂膜15を形成する(第3
図a)。その後、滴下方法により形成される前記
ポリイミド樹脂膜16は、表面張力及び、前記ポ
リイミド樹脂膜15表面と半導体素子1表面の密
着性の違いから前記ポリイミド樹脂膜15の外側
へ流れ出さない。その後、熱処理でポリイミドを
硬化させる。この時、1層目の樹脂15と2層目
の樹脂16は異種の樹脂でもよい。これをエポキ
シ樹脂9を用いて全体を固定すれば、第4図に示
す樹脂封止型半導体装置が形成される。尚第5図
は第3図aの平面図である。又、第3図乃至第5
図で第1図aと同じ機能のところは同一符号で示
している。
3 and 4 show the case where the present invention is applied to a MOS type RAM. On the entire surface of the semiconductor element 1,
After applying polyimide resin to a thickness of approximately several μm, a polyimide resin film 15 is formed using photoresist only on areas susceptible to the influence of α particles, such as memory cells and sense amplifiers (third step).
Diagram a). Thereafter, the polyimide resin film 16 formed by the dropping method does not flow out to the outside of the polyimide resin film 15 due to the difference in surface tension and adhesion between the surface of the polyimide resin film 15 and the surface of the semiconductor element 1. Thereafter, the polyimide is cured by heat treatment. At this time, the first layer resin 15 and the second layer resin 16 may be different types of resin. If this is fixed as a whole using epoxy resin 9, a resin-sealed semiconductor device shown in FIG. 4 is formed. 5 is a plan view of FIG. 3a. Also, Figures 3 to 5
In the figure, the same functions as in FIG. 1a are indicated by the same reference numerals.

又本発明において、1層目と樹脂と2層目の樹
脂に異種の樹脂を使用することによつて樹脂のエ
ツチング特性の差を利用することが出来る。すな
わち、フオート・レジストをマスクとして2層目
の樹脂をエツチングし、次に2層目の樹脂をマス
クとして1層目の樹脂をエツチングすることが出
来る。このようにすることによつて精度の良いパ
ターンを形成することが可能となる。
Further, in the present invention, by using different types of resins for the first layer resin and the second layer resin, the difference in etching characteristics of the resins can be utilized. That is, the second layer of resin can be etched using the photo resist as a mask, and then the first layer of resin can be etched using the second layer of resin as a mask. By doing so, it becomes possible to form a highly accurate pattern.

第6図は本発明の他の実施例を示すもので、セ
ラミツク封止型半導体装置の半導体素子1の表面
に部分的に第1層目の樹脂15および第2層目の
樹脂16を設けたものである。尚、第6図におい
て第1図bと同じ機能のところは同一の符号で示
している。
FIG. 6 shows another embodiment of the present invention, in which a first layer of resin 15 and a second layer of resin 16 are partially provided on the surface of a semiconductor element 1 of a ceramic sealed semiconductor device. It is something. In FIG. 6, the same functions as in FIG. 1b are indicated by the same reference numerals.

このような、本発明によれば素子内のメモリセ
ル及びセンスアンプなどのα粒子の影響を受けや
すい部分の表面のみ2層目の樹脂膜を形成するこ
とにより、製造が容易で、充分に高い信頼性を特
つた半導体集積回路が実現できる。
According to the present invention, the second layer of resin film is formed only on the surfaces of the parts that are easily affected by alpha particles, such as memory cells and sense amplifiers in the device, making manufacturing easy and achieving a sufficiently high A highly reliable semiconductor integrated circuit can be realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a及び第1図bは、それぞれ従来の樹脂
封止型半導体装置及びセラミツク封止型半導体装
置の断面図である。第2図aおよび第2図bは第
1図aの半導体装置を従来技術により、放射線か
ら保護した構造を示す断面図である。第3図a及
び第3図bは本発明の一実施例の各工程を示す断
面図であり、第4図は一実施例の断面図であり、
第5図は第3図aの平面図である。第6図は本発
明の他の実施例を示す断面図である。 図中、1……半導体素子、2,3……半導体素
子のボンデイングパツド、4,5……金属線、
6,7,8……リードフレーム、9……封止樹
脂、10……セラミツク容器、11……蓋板、1
2……金属薄板、13,14……リード、15…
…第1層の樹脂、16……第2層の樹脂、17,
17′……樹脂である。
FIGS. 1a and 1b are cross-sectional views of a conventional resin-sealed semiconductor device and a conventional ceramic-sealed semiconductor device, respectively. FIGS. 2a and 2b are cross-sectional views showing a structure in which the semiconductor device of FIG. 1a is protected from radiation using a conventional technique. 3a and 3b are cross-sectional views showing each step of an embodiment of the present invention, and FIG. 4 is a cross-sectional view of an embodiment,
FIG. 5 is a plan view of FIG. 3a. FIG. 6 is a sectional view showing another embodiment of the present invention. In the figure, 1...semiconductor element, 2, 3... bonding pad of the semiconductor element, 4, 5... metal wire,
6, 7, 8... Lead frame, 9... Sealing resin, 10... Ceramic container, 11... Lid plate, 1
2... Metal thin plate, 13, 14... Lead, 15...
...First layer resin, 16... Second layer resin, 17,
17'...Resin.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体素子の表面を放射線に対する阻止能力
を有する第1の樹脂で部分的に被覆し、該第1の
樹脂上に第2の樹脂を滴下し、しかる後滴下した
第2の樹脂を熱硬化せしめるか、もしくは前記第
1の樹脂上に該第1の樹脂とはエツチング特性の
異なる第2の樹脂を重ねて被覆することを特徴と
する半導体装置の製造方法。
1. Partially covering the surface of a semiconductor element with a first resin having radiation blocking ability, dropping a second resin onto the first resin, and then thermosetting the dropped second resin. Alternatively, the first resin is coated with a second resin having different etching characteristics from the first resin.
JP55151259A 1980-10-28 1980-10-28 Semiconductor device Granted JPS5775447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55151259A JPS5775447A (en) 1980-10-28 1980-10-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55151259A JPS5775447A (en) 1980-10-28 1980-10-28 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5775447A JPS5775447A (en) 1982-05-12
JPS6229909B2 true JPS6229909B2 (en) 1987-06-29

Family

ID=15514747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55151259A Granted JPS5775447A (en) 1980-10-28 1980-10-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5775447A (en)

Also Published As

Publication number Publication date
JPS5775447A (en) 1982-05-12

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