JPS6230391B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece having a built-in battery as a driving source, and relates to a pressure reducing circuit system for reducing the voltage of the battery and supplying the voltage.

Conventional electronic watches have a built-in silver battery as a driving source, divide the oscillation natural frequency of a crystal oscillator as a time standard using a frequency divider circuit, and display the time using the divided frequency through a counter circuit, decoder circuit, and driver circuit. The waveform is suitable for The silver battery used has a battery voltage of 1.4V~
Most have a voltage of 1.6V and a current capacity of 100 to 150 mAH, and their battery life is 2 to 3 years.

Recently, there has been a demand for thinner batteries from a design perspective, and a demand for longer battery life from an ease of use perspective. In response to this, the development of high-density batteries such as lithium batteries is progressing. However, although lithium batteries have several times the electric capacity compared to silver batteries, the operating voltage is about twice as high at 2.8 to 3.0V, and therefore the current consumption is also about twice as high, so I wonder if they could have been used as is. It has almost no effect.

In view of this, an object of the present invention is to extend the life of the battery by supplying a reduced pressure battery voltage to an electronic timepiece circuit. Furthermore, another object of the present invention is to provide an electronic timepiece that does not require any external elements and is equipped with a pressure reducing circuit that has a small number of elements.

FIGS. 1 and 2 show block diagrams of the electronic timepiece of the present invention. FIG. 1 shows an embodiment of a pointer type electronic timepiece.
The voltage VDD of the lithium battery 19, that is, 2.8 to 3.0 V, is reduced by the pressure reducing circuit 18 and supplied to the oscillation circuit 11 and the frequency dividing circuit 12 as a reduced voltage V _CC .
3. The driver circuit 14 is directly supplied with battery voltage. 15 is a step motor, 16 is a wheel train, and 17 is a pointer. Most of the current consumption of an electronic clock circuit is determined by the high-frequency circuit side, that is, the oscillation circuit and the high-frequency frequency divider circuit, so by supplying a reduced voltage to the high-frequency circuit side as shown in Figure 1, the current consumption can be reduced. Can be made smaller.

Furthermore, since the pressure reducing circuit 18 is formed in series with the oscillation circuit and the frequency dividing circuit, the pressure reducing circuit does not consume any extra current by itself.

FIG. 2 shows an embodiment of a liquid crystal display type electronic timepiece.
The voltage V _DD of the lithium battery 29 , that is, 2.8 to 3.0 V, is reduced by the pressure reducing circuit 28 and supplied as a reduced voltage V _CC to the oscillation circuit 21 and the frequency dividing circuit 22 .
3. The counter circuit 24, decoder circuit 25, and driver circuit 26 are directly supplied with battery voltage. 27 is a liquid crystal display. In FIG. 2, the pressure reducing circuit is arranged in series with the oscillation circuit and the frequency dividing circuit, as in FIG. 1.

In the embodiments shown in FIGS. 1 and 2, the frequency divider circuit is divided into two groups and each is driven by a reduced voltage V _CC and a battery voltage V _DD , but the selection of the driving voltage is as shown in FIG. , 2. There are various variations of Figure 2. In an embodiment as a modification of Fig. 1, all the oscillation circuits and frequency dividing circuits are driven with reduced pressure voltage, the driver circuit is driven with battery voltage, and the oscillation circuit, frequency dividing circuit, and driver circuit are all driven with reduced pressure voltage. That's true. In addition, in the modified embodiment shown in FIG. 2, the oscillation circuit and the frequency dividing circuit are all driven by reduced voltage, and the counter circuit and
Driving the decoder circuit and driver circuit with battery voltage, or driving the oscillator circuit, frequency divider circuit, and counter circuit with reduced voltage voltage, and driving the decoder circuit and driver circuit with battery voltage, or oscillating circuit and frequency divider circuit. In addition to driving the , counter circuit, and decoder circuit with reduced voltage and the driver circuit with battery voltage, the oscillation circuit, frequency dividing circuit, counter circuit, decoder circuit, and driver circuit are all driven with reduced voltage.

In any of the above embodiments, the battery voltage reducing circuit is
It is formed in series with an electronic circuit including at least an oscillation and frequency divider circuit, and is configured to optimally reduce the current consumption of the electronic circuit, and to avoid the consumption of excess current by the pressure reducing circuit itself. There is.

An embodiment of the pressure reducing circuit for an electronic timepiece according to the present invention is shown in FIGS. 3 and 4. The pressure reducing circuit shown in FIGS. 3 and 4 consists of a voltage standardization circuit (regulator) using a differential amplifier circuit having an amplification stage circuit whose current load is an electronic circuit including at least an oscillation and frequency division circuit.

This circuit of FIG. 3 will be explained in detail. The circuit shown in FIG. 3 is composed of a differential amplifier circuit having an amplifier stage circuit whose current load is an electronic circuit including an oscillation and frequency dividing circuit.
P channel MOS transistor 31 and N channel
The MOS transistor 32 forms a bias circuit and generates a gate bias voltage for the constant current source MOS transistor 33 of the differential amplifier stage circuit. N-channel MOS transistors 33, 34, 35 and P-channel MOS transistors 36, 37 form a differential amplifier stage circuit, and 35 has a threshold voltage higher than 34 by V _CC . (A broken line is attached to the gate to indicate that 35 has a higher threshold voltage than _34. ) The output of the differential amplifier stage circuit is controls the current source transistor 38 and the amplification stage circuit whose current load is an electronic circuit including an oscillation and frequency divider circuit, and the reduced voltage V _CC is achieved. Oscillation at this reduced voltage V _CC ,
The frequency dividing circuit etc. are driven.

By the way, the threshold voltage difference between the pair of differential input transistors in the circuit shown in FIG. The material of one of the gates 34 and 35 is changed, and the amount of threshold voltage variation is determined by the difference in work function. Particularly in the case of a gate made of polycrystalline silicon, the amount of impurities introduced into the polycrystalline silicon is varied. Alternatively, this can be achieved by introducing impurities of different conductivity types into polycrystalline silicon. In the embodiment shown in FIG. 3, the gate 34 is made of N-type polycrystalline silicon, and the gate 35 is made of P-type polycrystalline silicon. Furthermore, both 34 and 35 are depletion mode transistors, and the other transistors are enhancement mode transistors.

FIG. 4 shows another embodiment of the pressure reducing circuit. This circuit of FIG. 4 will be described in detail. The circuit shown in FIG. 4 is composed of a differential amplifier circuit having an amplifier stage circuit whose current load is an electronic circuit including an oscillation and frequency dividing circuit. N channel
The MOS transistor 41 and the P-channel MOS transistor 42 form a bias circuit, and generate a gate bias voltage for the constant current source MOS transistor 43 of the differential amplifier stage circuit. P-channel MOS transistors 43, 44, 45 and N-channel MOS transistors 46, 47 form a differential amplifier stage circuit.
4 has a threshold voltage higher than 45 by V _CC . (44 is 45
A higher threshold voltage is indicated by a dashed line attached to the gate. ) so that the reduced voltage is equal to the threshold voltage difference V _CC of this differential input transistor pair,
The output of the differential amplification stage circuit controls the amplification stage circuit whose current load is an electronic circuit including a current source transistor 48 and an oscillation and frequency divider circuit, and a reduced voltage V _CC is achieved.

Similarly to FIG. 3, the threshold voltage difference between the differential input transistor pair is composed of the work function difference due to a) channel doping and) a gate material. 45 has a gate made of P-type polycrystalline silicon. The difference from FIG. 3 is that both circuits are composed of enhancement mode transistors.

In FIGS. 3 and 4, capacitors 39 and 49 can both be formed by parasitic capacitances of source diffusion layers of P-channel transistors such as oscillation and frequency divider circuits, and both can be constructed from CMOS integrated circuits formed on P-type substrates. For example, it can be formed by an N-well diffusion layer of a P-channel transistor. Naturally, the polarities of the transistors in Figures 3 and 4 are completely reversed, V _DD is grounded, and the ground is set to V _DD , and the polarity of the battery is reversed in Figures 1 and 2, so that V _DD and ground are connected. A configuration in which the symbols are exchanged is also possible. In that case, the capacitor can be formed by the source diffusion layer of the N-channel transistor or the P-well diffusion layer of the N-channel transistor.

Since the pressure reducing circuit of the present invention is CMOS, it does not require any external elements outside the integrated circuit, so the circuit can be made smaller by the unnecessary elements, and the current consumption by the elements can be eliminated. be able to. Furthermore, it has the advantage that it can be formed completely on the same CMOS integrated circuit board together with the electronic clock circuit.

Furthermore, depending on the usage situation, the electronic circuit after the frequency divider circuit is reset at the initial stage or when setting the time.
While obtaining stable oscillation output and pressure reducing circuit output, it is also possible to further save current consumption by the frequency division current.

As described above, according to the method of the present invention, a high-density battery with a high output voltage, such as a lithium battery, can be used effectively, and thereby a long life of the battery can be achieved. Although the present invention has been described using a lithium battery with its battery voltage reduced as an example, the present invention is equally effective for any battery.

Furthermore, the concept of reducing the battery voltage and using it is
In addition to electronic watches, it is applied to general electronic devices that use batteries as a driving source, such as calculators.

[Brief explanation of the drawing]

1 and 2 are block diagrams of an electronic timepiece according to the present invention. FIGS. 3 and 4 show embodiments of a pressure reducing circuit for an electronic timepiece according to the present invention. 19,29...Lithium battery, 11,21...Oscillating circuit, 12,22...Frequency dividing circuit, 18,28...Reducing circuit, _VDD ...Battery voltage, _VCC ...Reducing voltage.

Claims (1)

[Claims] 1. An electronic watch comprising a battery serving as a driving source and a pressure reducing circuit for reducing the battery voltage of the battery, the pressure reducing circuit being connected in series with an electronic circuit including an oscillation circuit and a frequency dividing circuit, wherein the pressure reducing circuit is connected to a first a differential amplifier stage comprising a polarity constant current source transistor, a pair of differential input transistors connected in series with the constant current source transistor and having mutually different threshold voltages, and a second polarity load transistor connected in series with the differential input transistor. a bias circuit that generates a gate bias voltage of the constant current source transistor, and a current source transistor whose gate is connected to a connection point between the differential input transistor and the load transistor, and one end of the current source transistor. An electronic timepiece characterized in that a reduced voltage is supplied to the electronic circuit.