JPS6230654B2 - - Google Patents

Description

[Detailed description of the invention]

(1) Technical Field of the Invention The present invention relates to an address modification circuit for a general-purpose digital signal processing device such as a microcomputer.
Especially when entering the inner loop in double loop processing, the contents of the index register (IX) related to the outer loop are saved to the index save register (IXS), and at the same time the IXS
This invention relates to an address modification circuit that uses a value stored in IX as an initial bias value. (2) Prior art and problems Conventionally, in order to facilitate processing of a double loop configuration in a general-purpose digital signal processing device, an address modification circuit is provided with an index save register for saving the value of an index register. is used. However, in the address modification circuit described above, when specifying an address related to the values of the indexes (i, j) of the outer loop and the inner loop, the desired value is obtained by extracting the value of each index and calculating it one by one. There is a problem in that the address must be calculated. (3) Object of the Invention In view of the problems of the conventional type described above, the main object of the present invention is to bias the index register when entering the inner loop in processing of a double loop configuration in a general-purpose digital signal processing device. The object of the present invention is to provide an address modification circuit that can very easily generate addresses that depend on parameters of both outer and inner loops by initializing values. (4) Structure of the Invention The present invention provides an index register and an addition method in which the output of the index register is one input and the output of a selection circuit capable of selecting an instruction specified address or a constant is the other input. an index save register capable of selectively inputting the output of the adder circuit or the output of the index register;
When the contents of the index register are temporarily saved in the index save register, the contents of the index save register can be simultaneously stored in the index register,
When the contents saved in the index save register are returned to the index register, the value obtained by adding the constant to the contents of the index register can be simultaneously stored in the index save register. An address modification circuit for a general-purpose digital signal processing device is provided. (5) Embodiment of the Invention An address modification circuit as an embodiment of the present invention is shown in FIG. In FIG. 1, 1 indicates an instruction given to the address modification circuit. The address modification circuit includes an instruction designation address latch 2, a selection circuit A3, an addition circuit 4, a selection circuit B5, and a selection circuit C.
6, IX (index register) 7, selection circuit D8, and IXS (index save register) 9. 10 is an address bus within the general purpose digital signal processing device. FIG. 2 shows the selection states of selection circuits A, B, C, and D corresponding to each process in the address modification circuit of FIG. 1. In FIG. 2, the address S1 specified by the instruction is directly outputted to the address bus so that direct addressing by the instruction can be performed. Also, the instruction-specified address S5 can be loaded into IX as an initial value. Further, by outputting an index modification, an address value obtained by adding the address value S1 specified by the instruction to the content value S4 of the index register 7 can be output to the address bus. The contents of the index register can be incremented by one. As a result, when processing a single loop configuration in the circuit shown in FIG. It can be output. i.e. first
If IX=0 and the address operand of instruction 1 is A, then

[Table] becomes. By the way, in the circuit shown in FIG. 1, when processing a double loop configuration, inside the second loop, the index register 7 for the outer loop is used to store the inner loop in the index register 7. The contents of index, save,
It is necessary to temporarily save it in register 9. For example, the most typical operation in a double-loop configuration is expressed in FORTRAN as follows.

[Table] In the above operation, the loop arguments (J, I) are quoted as-is in the address operation within the loop. The array A of addresses processed within the loop is A(1, 1), A(2, 1), ..., A(m,
1), A(1, 2), A(2, 2)..., A(m,
n), the address of A(J, I) is expressed as follows. Letting the address of A(1,1) be a+1, then a+((I-1)×m+J) Here, if a is set as the address specified by the instruction, in order to modify the above address with an index, the index register In 7 (I-
1) ×m+J must be set. In the circuit of FIG. 1, it is easy to populate the index register 7 with the above values, as will be explained below. If the contents of IX and IXS are both zero when entering the outer loop for the first time, then when entering the inner loop for the first time, the contents of IX and IXS are exchanged as shown in Figure 2, and IX = 0. , IXS=0. At the inner loop end, the content of IX becomes 1
Since the index is incremented by
+IX i.e. a, a+1, a+2, ..., a
+(m-1). When IX = (m-1), that is, when exiting the inner loop for the first time at J = m, the value saved in IXS is returned to IX, and at the same time as IX = 0, IXS = (m- 1)+1
= m. At the end of the outer loop, IX=1, and the process returns to the beginning of the outer loop. Then, when entering the second inner loop, IX=m and IXS=1. Therefore, in the inner loop, addressing by index modification is a+m, a+m+1, ..., a
+2m-1, A(2,1), A(2,2),
..., A(2, m) may be specified. When exiting the inner loop for the second time, IX=1, IXS=
(2m-1)+1=2m. Similarly below,
The addressing of A(J,I) in the inner loop can occur without special address operations. As explained above, in the address modification circuit shown in Fig. 1, when data is transferred between IX and IXS, the numbers shown in Fig. 2 can be set. Addressing by the most standard index modification of loops can be realized without using special address calculation circuits. (6) Effects of the Invention According to the present invention, in a general-purpose digital signal processing device, the most standard addressing method for temporarily saving the index register value in double loop processing can be achieved with only a slight increase in hardware. It is possible to generate an address for the address without performing any special calculations, thereby allowing a simple circuit to perform address designation calculations using high-speed index modification.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an address modification circuit as an embodiment of the present invention, and FIG. 2 is a diagram showing a selection state of a selection circuit in the circuit of FIG. (Explanation of symbols), 1: Instruction, 2: Latch of instruction specified address, 3: Selection circuit A, 4: Addition circuit,
5: Selection circuit B, 6: Selection circuit C, 7: Index register, 8: Selection circuit D, 9: Index save register, 10: Address bus.

Claims (1)

[Claims] 1 An index register, an adder circuit whose one input is the output of the index register, and whose other input is the output of a selection circuit that can select an instruction-specified address or a constant; It is equipped with an index save register that can select and input the output of the index register, and when the contents of the index register are temporarily saved to the index save register, the contents of the index save register are simultaneously saved. The contents can be stored in the index register, and when the contents saved in the index save register are returned to the index register, the value obtained by adding the constant to the contents of the index register can be saved at the same time. An address modification circuit for a general-purpose digital signal processing device, characterized in that an address modification circuit can be stored in an index save register.