JPS6231376B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention aims to speed up processing in an information processing device by arranging a plurality of arithmetic units and performing the same arithmetic processing sequence on a plurality of data in different arithmetic units.
It relates to circuits for parallel arithmetic processing.

Conventionally, attempts have been made to arrange multiple arithmetic units in order to process multiple pieces of data using the same arithmetic processing instruction example, but each arithmetic unit must have memory to store the instruction sequence for arithmetic processing, which is expensive. It was hot. Furthermore, it is necessary to simultaneously supply a plurality of pieces of data to a plurality of arithmetic units, making it difficult to supply the data.

An object of the present invention is to provide a register for holding instruction data in each arithmetic unit when operating multiple arithmetic units at the same time, and to use this register to instruct the processing function of the arithmetic circuit. It is an object of the present invention to provide an economical parallel arithmetic processing device with a simple configuration that includes a logic circuit for determining whether to operate or not and connects each arithmetic unit with a common input bus and a common output bus.

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention.

In this embodiment, a parallel arithmetic processing device constituted by four arithmetic units 11 to 14 will be described. Command data is passed through the data line 61 to the register 41.
After a unit time, the instruction data is transferred to the register 42, and at the same time, the following instruction data is input to the register 41. Registers 41 to 44 are
It operates as a shift register, and instruction data is transferred to the next stage register every unit time. Arithmetic unit 1
1 to 14 operate according to the contents of registers 41 to 44, respectively. The register 41 is composed of, for example, 24 bits. Of these, 16 bits are used by the arithmetic circuit 21
4 with function data that determines the processing function of
The bits are state control data that change the state of the operation control circuit, and the remaining four bits are module prohibition data that instructs to prohibit the operation of the arithmetic circuit. The state control data consisting of 4 bits is a status reset signal, a zero detection signal, a negative detection signal, and a positive detection signal. Each bit of the 4 bits of module prohibition data corresponds to the calculation units 11 to 14, the first bit is the module prohibition signal of the calculation unit 11, and the second to fourth bits are the module prohibition signals of the calculation units 12 to 14, respectively. It is. When each module inhibition signal is "0", the arithmetic circuit of the corresponding arithmetic section does not operate. Among the data output from the register 41 to the data line 71, function data is output to the data line 7.
6 to the arithmetic circuit 21. Further, state control data and a module inhibit signal are input to the operation control circuit 31 through the data line 81.

The calculation data line 51 is a common input bus to the calculation section,
The calculation data line 52 is a common output bus from the calculation section. The arithmetic circuit 21 outputs a negative signal of "1" when the value of the arithmetic result is negative and a zero signal of "0" when the value is zero to the data line 91 as two signal lines. If the module inhibit signal inputted from the data line 81 is "1" and the negative signal zero signal inputted from the data line 91 matches the condition of the state control data inputted from the data line 81, the clock of the clock line 53 is turned off. is output to the signal line 96, causing the arithmetic circuit 21 to operate. When the operation signal is input from the signal line 96, the arithmetic circuit 21 performs an operation according to the function data input from the data line 76. Arithmetic unit 1
2 to 14 also perform similar operations.

FIG. 2 is a block diagram showing an example of the arithmetic circuit 21. As shown in FIG. The arithmetic circuit 21 will be explained using an example in which arithmetic processing is performed on 16-bit data.
Blocks 201 to 204 are each 4-bit CPU
For example, "μPB2901 manufactured by NEC Corporation" can be used. Bidirectional data lines 251-254 are data lines used when bit shifting is performed. Further, data lines 261 to 263 are data lines for propagating a carry that occurs when performing addition and subtraction. Function data is provided to the CPUs 201-204 through a data line 76. When an operation signal is input from the signal line 96, the CPUs 201-204 perform operations according to this function data.

When the operation result data of the CPUs 201 to 204 is 0, a signal of "0" is outputted through the data lines 271 to 274, logically negated by the logical NOT circuits 205 to 208, and outputted to the signal lines 281 to 284, respectively, and the NANDed signal is outputted through the data lines 271 to 274. A NAND operation is performed in the circuit 209 and a zero signal is output to the signal line 285. or
The most significant bit of the calculation result of CPU 204 is output as a negative signal to data line 275, and a zero signal and a negative signal are output through data line 91.

When the function data input via the signal line 76 indicates an input operation, the data divided into 4 bits each from the lower order of the 16-bit common input bus 51 is applied to the data lines 211 to 214, and the data is divided into 4 bits each. is input to the CPUs 201-204. When the function data indicates an output operation, data of 4 bits each is outputted from the CPUs 201-204 to the data lines 231-234 and then outputted to the common output bus 52 as 16-bit data.

FIG. 3 is a block diagram showing an example of the operation control circuit 31. Five signals constituting the state control data input from data line 81, namely, a module inhibit signal, a status reset signal, a zero detection signal, a negative detection signal, and a positive detection signal, are transmitted to signal lines 330, 335-338, respectively. Two signals, a zero signal and a negative signal, constituting the data input from the data line 91 are connected to the signal lines 320 and 3, respectively.
21 will be informed.

The signals on signal lines 320 and 321 are logically negated by logical negation circuits 306 and 307, respectively, and outputted to signal lines 322 and 333 as negation rate signals and negation signals. When the zero detection signal on the signal line 336 is “1” and the negative zero signal on the signal line 322 is “1”, the negative AND circuit 308 outputs a “0” signal to the signal line 341.
is output to. Further, when the negative detection signal on the signal line 337 is "1" and the negative signal on the signal line 321 is "1", the NAND circuit 309 outputs a signal of "0" to the signal line 342. In the NAND circuit 310, when the positive detection signal on the signal line 338 is “1”, the signal line 33
When both the negative signal and the zero signal of 3 and 320 are "1", "0" is output to the signal line 343. When the AND circuit 311 takes the AND of the signal lines 341 to 343 and outputs "0" to any of them, the signal line 34
4 and outputs "0" to the flip-flop 312 to set the operating status of the flip-flop 312 to "1". Signal line 33
The status reset signal transmitted to 5 is “1”
At this time, the operating status of the flip-flop 312 is set to "0". flipflop 312
The operation status of is input to the logic NOT circuit 313 through the signal line 345, and a logic NOT signal is output to the signal line 346.

When the module inhibit signal on the signal line 330 is "1" and the output of the flip-flop 312 is "0", the clock input through the signal line 53 passes through the AND circuit 314 and is output to the signal line 96.

FIG. 4 shows the arithmetic unit 1 of the parallel arithmetic processing device of the present invention.
It is a time chart showing an example of operations 1 to 14.

16-bit data A ₁ whose upper 8 bits are “0”,
…, A ₄ and B ₁ , …, B ₄ , A ₁ ×B ₁ , …, A ₄ ×B ₄
The flow of processing for calculating will be explained as an example.

The horizontal axis is numbered by unit time, and the vertical axis shows the instruction data set in the register of the calculation section at that time. Referring to Figure 2, CPU201-2
Each of the CPUs 201-204 constitutes a 16-bit/16-word memory. Referring to FIG. 4, I1 to I27 indicate command data, and unless otherwise specified, a 4-bit module inhibit signal, status reset signal, zero detection signal, negative detection signal,
“0” is used as the positive detection signal. The 0th address of the memory is cleared by the instruction data of I1. I
Operational data given to the common input bus as instruction data No. 2 and I3 are respectively stored at the first address and the second address of the memory. I4, I7, I10, I1
3.In command data of I16, I19, I22, and I25, status reset signal, zero detection signal,
The positive detection signal is set to "1", and the data at the second address of the memory is rotated one bit to the right by these command data. When the most significant bit of the shifted data is 0, the operation status becomes "1". I5, I8, I11, I14, I17, I2
In the instruction data of 0, I23, and I26, the status reset signal is set to "1", and when the operation status is "0", the contents of the 0th address and the 1st address of the memory are added to the 0th address. Stored.
When the operation status is "1", no processing is performed in the arithmetic circuit. I6, I9, I12, I15, I
The data at the first address of the memory is shifted one bit to the left by the instruction data of 18, I21, and I24 and stored at the first address. The multiplication operation ends with instruction data I4 to I26. The contents of the 0th address of the memory are outputted to the common output bus with the instruction data of I27.

At times 2 to 9, data A ₁ to A ₄ and B ₁ to B ₄ are externally supplied to the common input bus, and at time 30
Data output in ~33 A ₁ ×B ₁ , A ₂ ×B ₂ ,
..., A ₄ × B ₄ are output from the common output bus to the outside.

By using the parallel arithmetic processing device of the present invention, by connecting the arithmetic units in series, it is possible to easily realize an arithmetic processing device that is nearly twice as many as the number of connected arithmetic units at low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the parallel arithmetic processing device of the present invention, and FIG. 2 shows the arithmetic unit 21 of FIG.
24, FIG. 3 is a detailed block diagram of the operation controllers 31 to 34 of FIG. 1, and FIG. 4 is a time chart for explaining an example of the operation of the parallel arithmetic processor of the present invention. In the figure, 21 to 24 are arithmetic units, 31 to 34
is an operation controller, 41 to 44 are registers, and 201 to 44 are registers.
204 is a CPU, 205 to 208 are logical NOT circuits, 209 is an AND circuit, 306 to 307 are logical NOT circuits, 308 to 310 are NOT AND circuits, 3
11 is an AND circuit, 312 is a flip-flop,
313 is a logical NOT circuit, and 314 is an AND circuit.

Claims (1)

[Claims] 1. A shift register in which a plurality of registers are connected in series so that the input instruction data is transferred to the next register one after another every unit time, and a shift register corresponding to each register of the shift register. an arithmetic circuit provided for each of the arithmetic circuits and receiving output instruction data from the register; and an arithmetic circuit provided for each of the arithmetic circuits and operating the arithmetic circuit using state data output from the arithmetic circuit and output instruction data from the register. and an operation control circuit that outputs a signal indicating whether or not, and the input/output lines of the calculation data of all the calculation circuits are connected by a corresponding common input bus and a common output bus. Device.