JPH0623977B2 - Vector processor - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a vector processing device.

[Background of the Invention]

In the conventional vector processing device, in order to increase the processing speed,
It has a plurality of data transfer circuits that control the data transfer between the vector arithmetic unit and the main memory and the vector register.

However, in the vector instruction group that constitutes the actual vector processing, the number of vector instructions that can be executed at the same time is small, these vector operation units and data transfer circuits cannot be used at the same time, and the use efficiency of the vector operation units is low, There is a drawback that speedup of processing cannot be expected. As a conventional example, there is a vector processing device described in JP-A-58-114274.

[Object of the Invention]

An object of the present invention is to provide a vector processing device which enhances the use efficiency of the vector arithmetic unit and the data transfer circuit, speeds up the processing, and is easy to manage when adding the vector arithmetic unit and the data transfer circuit. is there.

[Outline of Invention]

According to the present invention, in a vector processing device including a plurality of vector registers, a plurality of vector operation units, and a plurality of data transfer circuits, a plurality of vector registers and at least one
A plurality of vector operation processing units including one vector operation unit and at least one data transfer circuit are prepared, and when executing one vector instruction, the number of vector elements to be processed is designated for each vector operation processing unit, and as a whole, It is possible to perform vector processing by the number of elements to be processed originally.

In addition, the data transfer circuit of each vector arithmetic processing unit,
The vector register and the vector arithmetic unit are respectively associated with the data transfer circuits, vector registers, and vector arithmetic units of other vector arithmetic processing units, and a plurality of vector transfer processing units each including one data transfer circuit are provided. A vector register group, a plurality of vector operation unit groups each including one vector operation unit, and a plurality of data transfer circuit groups each including one data transfer circuit are configured, and the element parallel operation for the vector instruction is performed in group units. The vector register, the vector arithmetic unit, and the data transfer circuit required for the arithmetic are selected to facilitate the expansion in the vector arithmetic processing unit.

Example of Invention

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an overall configuration diagram showing an embodiment of a vector processing device of the present invention. 1 is a main storage device, 2 is a storage control unit, 3 is a scalar operation processing unit, and 4 to 7 are vector operations, respectively. The processing unit 8 is a vector operation control unit that controls the operations of the vector operation processing units 4 to 7. The scalar arithmetic processing unit 3 has an ordinary arithmetic processing function well known in this field. Each of the vector arithmetic processing units 4 to 7 has a plurality of vector registers 9, one or a plurality of vector arithmetic units 1
0, data transfer circuits 11 to 13 for transferring data to and from the main storage device 1 via the storage device control unit 2, data between the vector register 9 and the vector calculator 10 or the data transfer circuits 11 to 13 It includes connection path selection circuits 24 and 25 that form a path, and an instruction execution control unit 15 that is connected to these elements and controls the operation of the entire vector arithmetic processing unit.

Although only the vector operation processing unit 4 is shown in detail in the figure, the other vector operation processing units 5 to 7 have the same configuration.

Note that the data transfer circuits 11 and 12 are for futish, and the data transfer circuit 13 is for store. Also, the connection path selection circuit 24,2
Although 5 is independent for each vector operation processing unit in the figure, all the vector operation processing units may be connected.

In the system shown in FIG. 1, when the scalar arithmetic processing unit 3 is processing a certain task and vector processing has to be performed in the middle of the task, the scalar arithmetic processing unit 3 transmits it via the vector arithmetic processing unit 8 to the vector arithmetic processing unit 4.
~ 7 to process.

Consider the case where the following program is executed by the scalar arithmetic processing unit 3.

DO 10 I = 1,100 10 A (1) = B (1) + C (1) This is one LIN (Load I
nclement) command and three LMAs (Load Multiple Addres)
s) instruction and one EXVP (Execute Vector Processor) instruction, which are respectively executed by the scalar arithmetic processing unit 3.

LININR0, INR2, INR4: Command to set constants in increment registers INR0, INR2, INR4 (increment register is prepared in vector operation control unit 8 as described later.) LMA VAR0: Matrix A Start address of vector address register VA
Command to set to R0.

(The vector address register is prepared in the vector operation control unit 8 as described later.) LMA VAR2: The start address of the matrix B is the vector address register VA
Command to set to R2.

LMA VAR4: Matrix C start address is vector address register VA
Command to set to R4.

EXVP X: Instructing that the number of vector elements to be processed is L, reading the vector instruction sequence from the address X of the main memory 1 as the start address, and sending it to the vector operation control unit 8. Order.

The address control data relating to the matrices A, B, and C are set in the vector address register and increment register in the vector operation control unit 8 by the above LIN and LMA instructions, and the vector instruction string is read by the EXVP instruction. Be done. This vector command sequence consists of two LVR (Load Vector Register) commands and one V
EA (Vector Elementwise Add) instruction and one STVR (Stor
e Vector Register) instructions.

LVR VR2, VAR2, INR2: An address of the main memory 1 is created based on the head address and the constant of the matrix B set in the vector address register VAR2 and the increment register INR2, respectively.
Command to read the data of matrix B from there and set it in vector register VR2.

The constant is used as the increment value of the address, and the same applies hereinafter.

LVR VR4, VAR4, INR4: An address of the main memory 1 is created based on the head address and the constant of the matrix C set in the vector address register VAR4 and the increment register INR4, respectively.
Command to read the data of matrix C from there and set it in vector register VR4.

VEA VR6, VR2, VR4: Matrix B and C are read from vector registers VR2 and VR4, respectively, and both are added and the result is a vector register.
Commanded to set to VR6.

STVR VR6, VAR0, INR0: Read data from vector register VR6, and read it from vector address register VAR0 and increment register
It is instructed to write to the address of the main memory 1 created based on the head address and the constant of the matrix A set in INR0 respectively.

Each of these vector instructions is sent to the vector instruction buffer 16 in the vector operation control unit 8.

Further, the number L of vector processing elements is sent to the vector length register 17 in the vector operation control unit 8.

FIG. 2 is a block diagram showing details of the vector operation control unit 8 and the data transfer circuit in the vector operation processing unit. First operation of the vector operation control unit 8
It will be described with reference to FIG. 2 and FIG.

As described above, with respect to the vector instruction buffer 16 to which the vector instruction has been input from the scalar arithmetic processing unit 3, the instruction execution determination circuit 18 makes 1 from the leading fetch position.
Take one vector instruction and determine if it is feasible.

That is, the display circuit 19 includes the vector arithmetic processing unit 4
7 to 7, a vector register 9, a vector calculator 10, and a data transfer circuit therein are provided.
There is one indicator corresponding to each of 11 to 13 and indicates whether or not they are in use.

For example, the indicator corresponding to the vector register VR1 is not provided corresponding to each of the vector operation processing units 4 to 7, but only one indicator is provided. The same applies to other items.

The instruction execution determination circuit 18 refers to these indicators to determine whether the vector register 9 designated by the fetched vector instruction or the vector computing unit 10 for performing the computation designated by the vector instruction is free. Examine
When it is detected that all necessary items are free, it is determined that the vector instruction can be executed. Then, in that case, the indicators corresponding to the vector register 9, the vector calculator 10, and the data transfer circuits 11 to 13 used in the vector instruction are set so as to indicate that they are in use, and the vector instruction is set. The start signal 22 is sent to the instruction register 20 and the start control circuit 21.

The vector instruction buffer 16 shown in FIG. 2 shows the format of one vector instruction sent from the scalar processing unit 3.

Further, the instruction register 20 shown in FIG.
The format of one vector instruction issued from 18 is shown.

In this case, OP is an operation code indicating the type of operation, VRN1 to 3 are vector register designating parts for designating vector registers, VARN is a vector address register designating part for designating vector address registers, and INRN is an input register for designating increment registers. It is a clement register designating part.

Some vector instructions do not use a vector address register or the like (for example, the VEA instruction), and in that case, there is no corresponding designated section.

Hereinafter, for convenience of explanation, all VRNs 1 to 3 are treated as existing unless otherwise specified.

OP, VRN1-3, VARN, and INRN in the instruction register 20 are those output from the vector instruction buffer 16 and output by the instruction execution determination circuit 18 as they are. ALN and TRN are both newly added in the instruction execution judgment circuit 18, and the arithmetic unit designating part that designates the vector arithmetic unit and the data transfer circuit corresponding to the indicator newly used in this circuit, the data This is a transfer circuit designating unit.

The vector processing device described here pays attention to a vector element number and processes one vector instruction by dividing it into four vector operation processing units as follows.

That is, if the vector element number is, vector element vector arithmetic processing unit = 0,4,8 ... 4 = 1,5,9 ... 5 = 2,6,10 ... 6 = 3,7,11. It is divided into 7 and so on.

Portions of the instruction register 20 other than VARN and INRN are sent to the instruction execution control unit 15 in each of the vector operation processing units 4 to 7. Upon receiving the unit activation signal 23 from the activation control circuit 21, each of the instruction execution control units 15 causes the vector arithmetic processing unit to perform the vector processing operation based on the information received from the instruction register 20.

In each instruction execution control unit 15, the vector instruction to be executed is LVR.
In the case of a vector instruction that uses the vector register 9 and the data transfer circuit like the instruction or the STVR instruction, one of VRN1 to 3 (only one vector register is used in the LVR instruction and the STVR instruction. It is designated by VRN1) and TRN are sent to the connection path selection circuit 24 or 25. At this time, the connection path selection circuit 24 or
25 is the vector register 9 and T designated by VRN1
A connection path to the data transfer circuit designated by RN is selected and activated. And each instruction execution control unit 15
Causes each of the contents to be read from one of the plurality of vector address registers 27 and one of the plurality of increment registers 28 based on VARN and INRN in the instruction register 20.

The data transfer circuit designated by TRN (hereinafter, this will be described as the data transfer circuit 11) sends the contents read from the vector address register 27 to the storage control unit 2 as an access address via the selector 29 and the register 30. To do.

Meanwhile, during that time, the contents read from the increment register 28 are input to the adder circuit 33 via the quadrupling circuit 31 and the register 32, and the sum with the contents of the register 30 is obtained. Then, this result is set in the register 30 via the selector 29.

This new content is sent to the storage control unit 2 as an access address in the same manner as before. Hereinafter, the same operation is repeated.

Further, the data transfer circuit 11 in the vector operation processing unit 5 obtains the sum of the contents read from the vector address register 27 and the contents read from the increment register 28 by the adder circuit 34, and outputs the sum to the selector 29 and the register 30. It is sent to the storage control unit 2 as an access address via the.

Meanwhile, during that time, the contents read from the increment register 28 are input to the adder circuit 33 via the quadrupling circuit 31 and the register 32, and the sum with the contents of the register 30 is obtained. Then, this result is set in the register 30 via the selector 29. This new content is sent to the storage control unit 2 as an access address as before. Hereinafter, the same operation is repeated.

In the case of the data transfer circuit 11 in the vector operation processing unit 6, the input of the adder circuit 35 corresponding to the adder circuit 34 is the content read from the increment register 28 via the doubling circuit 36. The only difference is the above.

In the case of the data transfer circuit 11 in the vector operation processing unit 7, the input of the adder circuit 37 corresponding to the adder circuit 34 is the content read from the increment register 28 via the triple circuit 38. The only difference is the above.

The adder circuits 34, 35, 37, the double circuit 36, the triple circuit 38, 4
Although only one address operation circuit 26 including the multiplication circuit 31 is provided for the data transfer circuit 11 in the figure, it is assumed that this is also provided for the other data transfer circuits 12 and 13.

Therefore, when the data transfer circuit designated by TRN is 12 or 13, the instruction execution control unit 15 sends a signal to the corresponding address operation circuit to operate it.

The access address sent from the data transfer circuit 11 in each of the vector operation processing units 4 to 7 to the storage control unit 2 is given to the main storage device 1. If the data transfer circuit designated by TRN is 11 or 12 for fetching, the read data from the main memory 1 is sent to the data transfer circuit 11 or 12 via the signal line 39, and then the connection path selection circuit It is loaded via 24 into the vector register 9 specified by VRN1. If the data transfer circuit specified by TRN is 13 for store, after the read data from the vector register 9 specified by VRN1 is sent to the data transfer circuit 13 via the connection path selection circuit 25,
It is written in the main recording device 1 via the signal line 40 and the storage control unit 2.

Each instruction execution control unit 15 determines that the vector instruction to be executed is VEA.
In the case of a vector instruction that uses the vector register 9 and the vector calculator 10 like the instruction, VRN13 and ALN are sent to the connection path selection circuits 24 and 25. At this time, the connection path selection circuits 24 and 25 select a connection path between the three vector registers 9 designated by VRN1 to 3 and one vector arithmetic unit 10 designated by ALN, and activate it. To do.
Thereafter, the data is read from the selected two vector registers 9, the operation is performed by the selected vector operation unit 10, and the result is written in the selected one vector register 9.

As described above, one vector instruction is divided and processed by the four vector operation processing units 4 to 7.

That is, the vector operation processing units 4 to 7 have MOD4 = 0, MOD4 = 1 and M of L elements, respectively.
The elements of OD4 = 2 and MOD4 = 3 are shared.

Each of the connection path selection circuits 24 and 25 can simultaneously activate a plurality of connection paths. As a result, the instruction execution control unit 15
Is a designated vector register 9 or vector calculator 10
And the data transfer circuits 11 to 13 are free, the instruction register
The execution of vector instructions given from 20 is started one after another,
Multiple vector instructions can be executed simultaneously.

Next, control of the number of vector elements processed by each of the vector operation processing units 4 to 7 will be described with reference to FIG.

In the instruction execution control unit 15 in each of the vector operation processing units 4 to 7, one counter is prepared corresponding to each of the vector register, the vector operation unit, and the data transfer circuit therein. If the vector instruction to be executed is an LVR or STVR instruction that uses a vector register and data transfer circuit, the vector register specified by VRN1 and TRN and the counter corresponding to the data transfer circuit, and the vector instruction to be executed are vector registers. In the case of the VEA instruction using the vector calculator and the vector calculator, the operation of the vector register designated by VRN1 to 3 and ALN and the counter corresponding to the vector calculator is as follows.

Note that in FIG. 3, one of the counters as described above is shown as 41, but the same applies to the other counters.

The portion excluding the lower 2 bits of the data, which is given from the scalar arithmetic processing unit 3 and is set in the vector length register 17 and represents the number L of vector elements, is set as it is in the counter 41 via the correction circuit 42. Vector length register 17
When the lower 2 bits are "00", no output is generated from the correction circuit 42. If it is "01", the output from the OR gate 43 in the correction circuit 42 is output to the counter 41 of the vector operation processing unit 4.

If it is "01", vector operation processing units 4 and 5
To the counter 41 of the OR gate 43 in the correction circuit 42 and the output line
Output from 44.

If it is “11”, the vector operation processing units 4, 5,
Outputs are output from the OR gate 43, the output line 44 and the AND gate 45 in the correction circuit 42 to the counter 41 of No. 6. The counter 41 in each of the vector operation processing units 4 to 7 is configured to add 1 to the value when an output is issued from the correction circuit 42.

When the vector instruction is executed by each of the vector operation processing units 4 to 7, the value of the counter 41 set as described above is decremented by 1 every time one vector element is processed. When it becomes 0, an output is emitted to the signal line 46. The output of each signal line 46 is sent to the counter 48 via the priority order circuit 47 in the vector operation control unit 8. The priority circuit 47, the counter 48, and the final value register 49 are commonly provided for the vector operation processing units 4 to 7,
One is provided for each of the vector register 9, the vector calculator 10, and the data transfer circuits 11 to 13 among them.

The final value register 49 is set to 4 when the activation signal 22 is output.
Is set to. The priority order circuit 47 gives the outputs to the counter 48 as they are when the outputs do not appear on the plurality of signal lines 47 at the same time. When the outputs appear at the same time, they are given to the counter 48 by shifting them by one clock time. is there. The counter 48 counts the output from the priority circuit 47, and when the count value becomes equal to the final value register 49, the comparison circuit 50 outputs the output. The display circuit 19 is a comparison circuit
Based on the output from 50, the indicator of the corresponding vector register, vector operation unit, and data transfer circuit is reset to display the vacancy.

Number of vector elements set in vector length register 17 L
May be less than 4. Therefore, the activation control circuit 21 for activating as many vector arithmetic processing units as necessary is prepared in the vector arithmetic control unit 8.

This will be described below with reference to FIG.

When the number L of vector elements is 4 or more, when the instruction execution determination circuit 18 outputs the activation signal 22, the activation control circuit 21 outputs the unit activation signal 23 to all the vector operation processing units 4 to 7. To be done.

The final value register 49 is set to 4 as described above. When L is 1, an output is issued from the 1 detection circuit 51 in the activation control circuit 21, and the OR gates 52, 53 and AND gates 54, 55, 56 work to the vector operation processing units 5, 6, 7. Unit activation signal 23 is blocked.
When L is 2, an output is generated from the 2 detection circuit 57, so that the OR gates 52, 53 and AND gates 55, 56 work to activate the unit activation signals to the vector operation processing units 6, 7.
23 is blocked. When L is 3, an output is generated from the 3 detection circuit 58, so that the OR gate 53 and the AND gate 56 act to prevent the unit activation signal 23 to the vector operation processing unit 7.

When L is less than 4, the number of vector operation processing units to be activated is set in the final value register 49. In this case, the data set in the final value register 49 can be obtained, for example, by counting the unit activation signal 23 sent to each vector arithmetic processing unit through the same circuit as the priority order circuit 47.

The above is an example of the case where one vector instruction is divided into four vector operation processing units.
It may be configured so that it can be arbitrarily switched so as to be processed by four vector arithmetic processing units.

For example, in the case of a vector instruction for obtaining an inner product or a sum or a vector instruction for performing a primary cyclic operation, it is necessary to process the vector instruction processing unit.

As described above, for example, the configuration for arbitrarily switching the processing by one to four vector arithmetic processing units may be as follows.

In FIG. 3, an AND gate 54 in the activation control circuit 21
Gates are provided on each output side of ~ 56. When only the vector operation processing unit 4 processes, the outputs of the AND gates 54 to 56 are prohibited and the vector operation processing unit 4
If only 5 and 5 are processed, the outputs of AND gates 55 and 56 are prohibited.

Regarding the correction circuit 42, a path for giving all bits of the vector length register 17 only to the vector operation processing unit 4 and a portion excluding the lower 1 bit are given to the vector operation processing units 4 and 5, and the lower 1 bit is " In the case of "1", a route or the like for causing the counter 41 of the vector operation processing unit 4 to perform +1 is provided so that these routes can be selected.

When the former route is selected, the vector operation processing unit 4 processes all vector elements, and in the latter case, the vector operation processing units 4 and 5 perform division processing.

In the case where only the vector arithmetic processing unit 4 is processed, in FIG.
In the register 32 in the data transfer circuit of the above, the value itself read from the increment register 28 is initialized, and when only the vector operation processing units 4 and 5 are processed, The address arithmetic circuit 26 is configured so that the register 32 in the data transfer circuit is initialized with a value obtained by doubling the value read from the increment register 28.

In the former case, the value set in the final value register 49 is
Needless to say, it is necessary to set the number equal to the number of vector operation units to be activated.

〔The invention's effect〕

According to the present invention, since one vector instruction is divided and processed by a plurality of vector operation processing units, the use efficiency of the vector operation unit and the data transfer circuit can be improved, and thus the processing speed can be increased.

When adding a vector operation processing unit to increase the degree of parallel execution of vector instructions, replace each vector register, each vector operation unit and each data transfer circuit in the added vector operation processing unit with each vector before addition. Registering each register group, each vector operation unit group and each data transfer circuit group to form a new vector register group, each vector operation unit group and each data transfer circuit group, thereafter, by the display circuit and the reset means, Whether or not a vector register, a vector arithmetic unit, and a data transfer circuit are used can be managed in group units before and after the addition of vector arithmetic processing units. That is, since the presence / absence of use of each vector register, each vector operation unit, and each data transfer circuit is managed in a unified unit called a group, it is easy to expand in units of vector operation processing units and Enhance can be done easily.

[Brief description of drawings]

FIG. 1 is an overall block diagram showing an embodiment of the vector processing device of the present invention, and FIG. 2 shows the details of the vector operation control unit and the data transfer circuit in the vector operation processing unit in FIG. A block diagram and FIG. 3 are block diagrams showing details of an instruction execution unit in the vector operation control unit and the vector operation processing unit of FIG. In the figure, 1 ... main storage device, 2 ... storage control unit, 3 ... scalar operation processing unit, 4-7 ... vector operation processing unit, 8 ... vector operation control unit, 9 ... vector register, 10 ... … Vector arithmetic unit, 11 to 13 …… Data transfer circuit, 15 …… Instruction execution control unit, 17 …… Vector length register, 18 …… Instruction execution judgment circuit, 21 …… Startup control circuit, 26 …… Address arithmetic circuit , 41,48 …… Counter, 42 …… Correction circuit, 49 …… Final value register, 50 …… Comparison circuit.

Claims (1)

[Claims] 1. A scalar arithmetic processing unit for exchanging data via a main memory device and a storage control unit, a plurality of vector registers, a plurality of vector registers for receiving data from the vector registers, and outputting arithmetic results to the vector registers. A plurality of vector operation processing units including a vector operation unit and a plurality of data transfer circuits for transferring data between the main memory device and the vector register via the storage control unit, and a vector of each vector operation processing unit. The register, the vector arithmetic unit, and the data transfer circuit are the vector register, the vector arithmetic unit of another vector arithmetic processing unit,
One of the vector registers in each of the vector operation processing units is associated with a data transfer circuit.
A plurality of vector register groups each including one by one, a plurality of vector operator groups each including one of the vector operator, and a plurality of data transfer circuit groups including one of the data transfer circuits, and A display circuit for displaying whether each of the plurality of vector register groups, the plurality of vector operation unit groups, and the plurality of data transfer circuit groups is in use or unused, and a vector instruction received from the scalar operation processing unit. On the other hand, a vector register group, a vector arithmetic unit group, and a data transfer circuit group necessary for performing element parallel operation are represented by the plurality of vector register groups in the unused state of the display circuit, and the plurality of vector arithmetic units. Group, and the selected vector register group, vector operation unit group, and data unit selected from the plurality of data transfer circuit groups. While the display circuit corresponding to the transfer circuit group is in use, the use of the vector register, the vector arithmetic unit, and the data transfer circuit belonging to the selected group is notified to each vector arithmetic processing unit, and the vector instruction is transmitted. The instruction execution determination circuit for notifying the vector arithmetic processing unit, and the vector length designated by the vector instruction from the scalar arithmetic processing unit, determines the number of vector element processing to be processed by each vector arithmetic processing unit, and the plurality of vectors A vector length determination circuit for notifying an arithmetic processing unit, executing the notified vector instruction while operating the vector register notified of the use, the vector operation unit, and the data transfer circuit, and Completion of execution of vector elements corresponding to the notified number of vector element processes And an instruction execution control unit provided in each of the plurality of vector operation processing units that notifies the display reset unit of the execution end of the vector register, the vector operation unit, and the data transfer circuit notified of the use, , A means for resetting the display in the display circuit corresponding to the group to an unused state when receiving the end notification for all the vector registers, the vector calculators, and the data transfer circuits belonging to each group. Vector processing device characterized by.