JPS6231384B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to control of data memory in in-home equipment, telephone exchanges, etc., and more particularly to a data memory protection circuit in data memory write control.

FIG. 1 is a circuit diagram of the main parts of a conventionally used data memory protection circuit and data memory. In FIG. 1, flip-flop 12
2 performs write control (hereinafter referred to as write control) of the data memory 120, and when the output terminal Q of this flip-flop 122 is at a low level (hereinafter referred to as L level), the data memory 120 is placed in a writable state ( When the level is high (hereinafter referred to as H level), the write-enabled state is set (hereinafter referred to as write-enabled state). The flip-flop 122 that performs this write control will hereinafter be referred to as a write enable flip-flop. Here, a set signal from the central controller is sent to terminal 100.
When the signal is input to the write enable flip-flop 1, noise superimposed on this set signal is removed by a delay circuit consisting of a resistor 110 and a capacitor 111, and a signal having a pulse width of a certain value or more is input to the write enable flip-flop 1.
Only by inputting to the input terminal R of 22,
This write enable flip-flop 122
puts the data memory 120 into a writable state. Next, when the write signal input to the terminal 102 (hereinafter referred to as a write signal) goes to L level, the output terminal of the OR gate circuit 121 goes to L level, and therefore the write control input terminal of data memory 120 also goes to L level. This data memory 12
0 is a write-enabled state. That is, if write enable flip-flop 122 makes data memory 120 writable, data memory 120 is writable even if data to be written is continuously input to terminal 102.

Next, in order to protect the system data in this data memory 120, at the end of the data write control to the data memory 120, a reset signal from the central control unit is input to the terminal 101, so that the write enable flip-flop is activated. Since the output terminal Q of the loop 122 becomes H level, even if a write signal is input to the terminal 102, the output terminal of the OR gate circuit 121 remains at the H level, and the data memory 120 becomes in a writable state. This conventional data memory protection circuit has a circuit configuration that protects system data in the data memory in this manner.

The disadvantage of this circuit configuration is that when the set signal from the central controller is input to terminal 100, resistor 11
The circuit is configured such that the write enable flip-flop 122 is set only when a signal having a pulse width exceeding the delay time determined by the time constant of the noise prevention circuit consisting of the 0 and the capacitor 111 is input. However, since the pulse width of the set signal input from the central control unit is generally around several hundred nanoseconds, it is important not to set the delay time of the noise prevention circuit consisting of resistor 110 and capacitor 111 to a too large value. Therefore, if a pulse with a pulse width comparable to that of the set signal is input due to external noise, the write enable flip-flop 122 may be set. .
If it is set, the data memory 120 will be in a writable state, so if a write signal is sent from the central controller to the terminal 10.
2, a write signal is sent to the data memory 120, and the data stored in the data memory 120 is rewritten.

It is an object of the present invention to eliminate the above-mentioned drawbacks, to prevent data memory from becoming writable due to external noise, and to prevent data from being written within a certain period of time even after the data memory becomes writable. A flip-flop is provided that automatically disables writing when no signal is input, and the system data in the data memory is protected by controlling the writing of the data memory using the output of the flip-flop. An object of the present invention is to provide a data memory protection circuit.

To achieve this objective, the data memory protection circuit of the present invention inputs set and reset signals from a central controller to a flip-flop;
For example, if the pulses formed by repeating the input of these signals alternately and output to this flip-flop are output according to the predetermined format, such that the input of these signals follows a predetermined format. It is set by a counter that only counts the pulses and determines its format, and changes in the output of that counter.Once the counter is set, if no write signal is input from the central controller within a certain period A counter is provided to detect this, and a write enable flip-flop is reset by a change in the output of the counter or by inputting a clear signal from the central controller, and the output of the write enable flip-flop is The present invention is characterized in that the data memory is protected by performing write control of the data memory.

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 2 is a circuit diagram of the main parts of the embodiment of the present invention and the data memory, and FIG. 3 is a time chart for explaining the operation of the circuit of the embodiment of the present invention. In FIG. 2, a terminal 200 receives a set signal from the central control unit, and the other terminal 201 receives a reset signal, and has input terminals R and S connected to these two terminals 200 and 201, respectively. Output terminal Q of flip-flop 223
outputs pulses by alternately repeating the set signal and reset signal input from the central controller. The output terminal Q of this flip-flop 223 is connected to a monostable multivibrator (hereinafter referred to as a monostable multivibrator) 22.
The counter 228 is connected to the falling detection input terminal A of the counter 228 and the input terminal CP of the counter 228.
A clear terminal CL of 28 is connected to an output terminal of a monostable multivibrator 224. Therefore, the monostable multivibrator 224 is operated by the fall of the output of the flip-flop 223, and its resistor 210 and capacitor 2
The output terminal is at L level only during a certain period of time determined by the time constant of the circuit consisting of 13 and 13. While this output terminal is at the L level, the clear terminal CL of the counter 228 is also at the L level, making it possible to count the pulses input to the input terminal CP of the counter 228. In other words, when input from the central controller via terminals 200 and 201, the alternating repetition of the set and reset signals is a retrigger determined by the time constant of the circuit consisting of resistor 210 and capacitor 213 of monostable multivibrator 224. If it is within the period, the counter 228 continues counting pulses, and a carry output signal (hereinafter referred to as a carry output signal) is output to the carry output terminal (hereinafter referred to as a carry output terminal) CR of the counter 228. This carry output signal is input to the input terminal of a NAND gate circuit 230 via an inverter 226, and the output terminal of the NAND gate circuit 230 is connected to the clear terminal CL of the counter 229. Therefore, when the carry output signal of the counter 228 is output at H level, the clear terminal CL of the counter 229 also becomes H level, and the output terminal D of the counter 229 becomes L level. As a result, the input terminal of the NOR gate circuit 232 becomes L level, and the other input terminal of this NOR gate circuit 232 becomes the L level unless a clear signal is input from the central controller to the write enable flip-flop 222 via the terminal 203. is at L level, so the NOR gate circuit 232
The output terminal of the write enable flip-flop 222 becomes H level, and the clear terminal CL of the write enable flip-flop 222 also becomes H level. As a result, when the carry output signal of the counter 228 falls, this carry output signal is also input to the terminal CP of the write enable flip-flop 222 via the inverter 226, so that the write enable flip-flop, which is a D-type flip-flop, is activated. The flip-flop 222 is set and its output terminal Q goes to L level. This enables the write enable flip-flop 22.
The output signal No. 2 puts the data memory 220 in a writable state. Next, when an L level write signal is input from the central control unit to the terminal 202, data can be written to the data memory 220.

On the other hand, the output terminal D of the counter 229 is further connected to the input terminal of a NOR gate circuit 231, and the other input terminal of this NOR gate circuit 231 is
It is connected via terminal 204 to the clock of the central control unit. Therefore, when an H level carry output signal is output from the carry output terminal CR of the counter 228, it passes through the inverter 226 and the NAND gate circuit 230 to the clear terminal CL of the counter 229.
Counter 2 starts from the moment the H level signal is input to
The output terminal D of the counter 229 changes from H level to L level, and the clock pulse from the central controller is inputted to the terminal CP of the counter 229 via the terminal 204 and the NOR gate circuit 231. Start counting the clock pulses. When the counter 229 counts up to eight clock pulses, it automatically stops counting and its output terminal D remains at the H level, so that the clear terminal CL of the write enable flip-flop 222 goes to the L level. level, this write enable flip-flop 22
The output terminal Q of No. 2 becomes H level, that is, the data memory 220 is rendered unwritable. Therefore, the output terminal D of this counter 229
before it stops at H level, that is, counter 2
When an L level write signal is input from the central control unit through the terminal 202 while the output terminal D of the OR gate circuit 29 is at the L level, the input terminals of the OR gate circuit 221 are both at the L level, and the output terminal of this OR gate circuit 221 is connected to the write control input terminal of the data memory 220, so that write control to the data memory 220 is possible. moreover,
The output terminal of the OR gate circuit 221 is also connected to the fall detection input terminal A of the monostable multivibrator 225, and the output terminal of this monostable multivibrator 225 is connected to the other input terminal of the aforementioned NAND gate circuit 230. . For this reason, when data is continuously written from the central controller to the data memory 220, the counter 2 is
29 is cleared, and the counter 229 returns to its initial state and starts counting the clock pulses input from the central controller again from the beginning.
This is a feature added to the data memory protection circuit of the present invention to enable continuous data writing from the central controller to data memory 220.

Next, at the end of write control to the data memory 220, when an L-level clear signal is input from the central controller to the terminal 203, the clear signal is passed through the inverter 227 and the NOR gate circuit 232 to the write enable flip-flop 222.
input to the clear terminal CL of the write enable flip-flop 222, and sets the output terminal Q of the write enable flip-flop 222 to H level, making the data memory 220 in a writable state. Therefore, from this point on, even if a write signal is input from the central controller to the terminal 202, no write control will be performed on the data memory 220.

As explained above, the present invention inputs a set signal and a reset signal from the central control unit to the flip-flop 223, and by repeating these signals alternately, the pulses formed and output to the flip-flop 223 are constant. If the pulses are not output at regular intervals, it is determined that the output pulses are caused by noise, etc., the output terminal of the monostable multivibrator 224 becomes H level, and the counter 228 outputs the output pulses. By immediately stopping the counting without counting, the data memory 220 is prevented from becoming writable due to noise or the like, and the write enable flip-flop 222 is immediately set and the data memory is 2
Even if a write signal is not input from the central controller within a certain period of time after the data memory 20 becomes write-enabled, the output terminal Q of the write enable flip-flop 222 is set to H level to prevent the data memory 220 from being written to. By configuring it to be enabled, there is an effect of preventing important data such as system data from being rewritten due to noise or other causes.

In the embodiment of the present invention, prior to writing data from the central controller to the data memory, a set signal and a reset signal are alternately and repeatedly input to the flip-flop of this data memory protection circuit, and the output pulse from the flip-flop is The configuration is such that writing to the data memory is not allowed unless the signals are output at a certain period, but it is clear that this is to make it possible to distinguish those signals from noise; Needless to say, any signal that follows a format that can be distinguished from noise may be used.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of the main parts of a conventional data memory protection circuit and data memory, FIG. 2 is a circuit diagram of the main parts of an embodiment of the present invention and data memory, and FIG. 3 is an embodiment of the present invention. This is a time chart to explain the operation of the circuit. 100-102...terminal, 110...resistance, 1
11... Capacitor, 120... Data memory,
121...OR gate circuit, 122...Flip-flop, 200-204...Terminal, 210,2
11...Resistor, 212, 213...Capacitor,
220...Data memory, 221...OR gate circuit, 222, 223...Flip-flop, 2
24,225...Monostable multivibrator, 226,227...Inverter, 228,
229... Counter, 230... NAND gate circuit, 231, 232... NOR gate circuit.

Claims (1)

[Scope of Claims] 1. A data memory protection circuit that is provided between a central control unit and a data memory and protects system data written from the central control unit to the data memory, wherein the central control unit protects system data written to the data memory. Before writing data consisting of at least one unit data, a first signal consisting of first and second pulse trains each including first and second pulses arriving alternately and in a predetermined sequence from the central control unit; determining means for outputting a second signal when it is determined that the first signal conforms to a predetermined format; control means including a permitting means for permitting writing of the unit data; a prohibiting means for inhibiting this writing by inputting a third signal; and a means for outputting a fourth signal each time this writing occurs; , means for counting the elapsed time after inputting either the second signal or the fourth signal, and inputting the fourth signal within a predetermined time after inputting the second signal. When not, and the fourth
and counting means for outputting the third signal to the inhibiting means when the fourth signal is not continuously input within a predetermined time after inputting the signal. A data memory protection circuit featuring: 2. A patent claim characterized in that the prohibition means also includes means for inhibiting writing of the unit data from the central control device to the data memory by inputting a fifth signal from the central control device. The data memory protection circuit according to item 1.