JPS6231556B2 - - Google Patents

Description

Detailed Description of the Invention The present invention provides stabilization of multi-frequency signals (hereinafter abbreviated as MF signals), which are numerical signals with strict transmission and pause timing, among telephone signals such as called party numbers in telephone networks. This invention relates to a multi-frequency signal transmission method for transmitting signals to

Conventional multi-frequency signal transmission methods involve storing all digits of the transmission number in hardware and transmitting them one digit at a time, or transmitting MF signal control information one digit at a time while controlling the timing in a central processing unit. The system uses a method to send out . Therefore, the former method has the disadvantage that the amount of hardware increases, and the latter method has the disadvantage that timing management in the central processing unit becomes complicated, resulting in a reduction in processing capacity.

In the present invention, all numeric information is stored in the software of the exchange main body, and the transmission and pause timing control for each numeric signal is configured in hardware.
The central processing unit solves the above drawback by sending the next digit signal to the hardware for each digit in accordance with the next digit request information from the hardware, thereby reducing the amount of hardware and simplifying the processing of the central processing unit. This provides an economical multi-frequency signal transmission method.

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes an input selector 102 connected to a central processing unit 900 via an information line 101;
and an input data memory 100 for receiving the output signal of. This input data memory 100 receives the line number and MF signal from the central processing unit 900,
The MF signal is stored in the storage location corresponding to the line number.

On the other hand, a transmission synchronization clock 201 and a control clock 202 are input to the sequence counter 200. As the sending synchronous clock 201,
A convenient clock is required for sending signals and counting pause timing. In this description, the transmission timing and pause timing are assumed to be 10 ms, and the period of the transmission synchronization clock 201 is 5 ms. When the sequence counter 200 receives the sending synchronization clock 201, it starts an internal counter, and the internal counter is counted up by the control clock 202 and the sequence clock sc0 is started.
~sc4 are output sequentially.

First, when sc0 is output, the output register 103
and down counter 301 from the address position of input data memory 100 and timing memory 300 indicated by address counter 104.
Read and store MF signal information and timing values. The output of the output register 103 is analyzed for signal type by the signal analyzer 106, and the output is sent to the gate 10.
8, the timing generator 500 generates the timing necessary for signal sending and pausing. Here, the explanation will proceed assuming that the signal sending and pause timing is 10 ms as described above. On the other hand, when a timing value is input from the timing memory 301 to the counter 301, that value is input to the zero detector 30.
2 is output. Next, sequence clock sc1 is output from sequence counter 200, and if zero detector 302 detects that the timing value is "0", flip-flop 304 is set via gate 303. At this time, if MF signal information is input into the output register 103, the data selector 600 is switched to the output register side via the gate 305. Also, since the counter value is “0”, the timing selector 70 is activated by the detection output of the zero detector 302.
0 is switched to the timing generator 500 side. Next, sc2 is output, but since flip-flop 304 is set, gate 306 does not operate. Next, when sc3 is output, gate 3
The output of 05 is sent to gate 3 via OR gate 308.
09, the gate 309 operates and sends a write pulse of signal information to the signal device 901. The signal device 901 draws in the MF signal data via the data line 601 and the line number via the address line 107 in response to the write pulse. Since the MF signal data is an MF signal, the signal device 901 sends the MF signal to the line. Next digit request flip-flop 800 is set by the output of gate 305 and central processing unit 9
Notifies 00 of a request to send the next digit. This flip-flop 800 is operated by the central processing unit 900.
It is reset when MF signal information is input. Also, in the timing memory 300 by sc3,
The output of timing generator 500 is stored via timing selector 700. In this case the timing value is 2. Furthermore, the input selector 102 is switched to the 109 side by the output of the gate 305, and "0" is written and cleared in the input data memory 100 by the output of the gate 310. Next, when sc4 is output, the flip-flop 304
is reset, and the address counter 104 increases by +1.
When the processing for that line is completed and processing for the next line is started, the sequence counter 200 again outputs from sc0, but the address counter 10
When the value of 4 returns to "0", it is detected by the detector 105 and the sequence counter 200 is stopped.
Sequence counter 200 does not operate until the next outgoing synchronization clock 201 is received.

When the next sending synchronization clock 201 is received, the sequence counter 200 starts operating and is output from so0. When sc0 is output, the signal information of that line is stored in the output register 103 and counter 301 as described above. Next, sc1 is output, but since the value of counter 301 is not "0", flip-flop 304 is not set. sc2
When the flip-flop 304 is not set, a countdown pulse is output from the gate 306 to the counter 301, and the counter value is set to -1. Next, sc3 is output, but since the counter value is "1", gate 307 does not operate, and gate 305 also does not operate, so
No write pulse from gate 309 is generated.
Since the timing value is not "0", the timing selector 700 is switched to the counter 301 side,
The value of the counter 301 is written into the timing memory 300 by sc3. The operations after sc4 are as explained above.

Next, when the sending synchronization clock 201 is received, the sequence counter 200 starts operating again, and the steps up to sc2 are the same as described above. Next, sc3 is output, but at this time the counter value is "0" and the flip-flop 304 is not set, so the gate 307 is activated and the timing selector 700 is switched to the timing generator 500 side. Conversely, since the gate 305 is not operating, the data selector 600 is switched to the no-call signal generator 400 side. The output of gate 307 is input to gate 309 via gate 308, and when sc3 is input, gate 309 sends a write pulse to signaler 901. Signal device 901 receives a no-call signal via data line 601 and a line number via address line 107 in response to a write pulse, and sends a no-call signal to the corresponding line. Further, the output of the timing generator 500 is input to the timing memory 300 via the timing selector 700, and the output of the timing generator 500 is input to the timing memory 300 via the timing selector 700.
3 stores the timing value "2". sc
4 and subsequent steps are the same as the above explanation.

The timing operation for transmitting the no-call signal is the same as described above, and when the timing is out, the operation for transmitting the next numeric information is performed, and the above operation is repeated until the transmission of all numeric information is completed. When all numbers have been sent,
The data in the input data memory 100 cleared via the input selector 102 is sent to the output register 103.
and signal generator 90 via data selector 600.
1, and the signal device 901 stops the signal sending operation.

In the above embodiment, the timing value is “2”.
However, it goes without saying that the timing generator 500 controlled by the signal analyzer 106 can generate values corresponding to each signal system. Further, although the sequence counter is provided internally, it may also be provided externally, and although the transmission synchronization clock is set to 5 ms, it goes without saying that a transmission synchronization clock for each line may also be used.

As explained above, the present invention aims to simplify the processing of the central processing unit, and to simplify the processing of the central processing unit by using software to store numerical information and share the timing of transmitting numerical signals and pauses with hardware. This has the effect of providing an extremely stable and economical multi-frequency signal transmission system, which can stably transmit signals with accurate timing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 100...Input data memory, 102...Input selector, 103...Output register, 104...
Address counter, 105...Detector, 106...
...Signal analyzer, 200...Sequence counter,
300...Timing memory, 301...Counter, 302...Zero detector, 304,800...Flip-flop, 108,303,305,30
6,307,308,309,310...gate, 400...no call signal generator, 500...timing generator, 600...data selector, 7
00...Timing selector, 900...Central processing unit, 901...Signal device.

Claims (1)

[Claims] 1. An input data memory having a capacity for at least one circuit and storing a multi-frequency signal corresponding to one digit from a central processing unit, and a clear signal for the multi-frequency signal from the central processing unit and the input data memory. an input selector for switching and supplying the input data memory to the input data memory; an output register for storing the multi-frequency signal read from the input data memory; and a timing memory having a capacity for at least one line;
a down counter that stores a timing value from the timing memory and counts down a countdown pulse from the stored value; an address counter that specifies addresses of the input data memory and the timing memory; and an output signal of the down counter that is set to "0". ”, a no-call signal generator, a data selector that switches between the output signal of the no-call signal generator and the output signal of the output register and supplies the signal to the signal generator, and a timing generator. switching between the output signal of the timing generator and the output signal of the down counter;
a timing selector that supplies the timing memory, a signal analyzer that analyzes the multifrequency signal from the output register, a sequence counter that generates a plurality of clocks for sequence control, and an output signal of the zero detector. A first flip-flop held by the first clock of the sequence counter, and when the first flip-flop is set and valid information is stored in the output register, the data is a first gate that outputs a switching signal that allows the selector to output the output signal of the output register and the input selector to output the clear signal, when the first flip-flop is not set; Moreover, when the sequence counter generates the second clock, the second gate that sends a countdown pulse to the down counter and the first flip-flop are not set, and the zero detector is " a third gate that outputs a signal when detecting "0", and when the first gate outputs the switching signal, and when the sequence counter generates the third clock, a fourth for sending a write pulse to the input data memory;
a fifth gate that takes the logical sum of the switching signal output from the first gate and the signal output from the third gate, and the output signal of the fifth gate and the sequence. 3rd counter
is set by a sixth gate that performs an AND with the clock of the clock and sends a data write pulse to the signal device, and the switching signal output from the first gate, and one digit is output from the central processing unit. a second flip-flop for the order digit request which is reset when a corresponding multi-frequency signal is sent out; the reset output signal of the second flip-flop is ANDed with the output signal of the signal analyzer; and a seventh gate that controls a timing generator.