JPS6231831B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sample and hold device that holds an instantaneous voltage value at the time of sampling for a predetermined period of time.

As is well known, sample-and-hold devices are used for recording voltages that change over time and for digital conversion.They have a capacitor hold the instantaneous value of the sampled voltage, and the voltage held by the capacitor is transferred to a buffer amplifier with high input impedance. It is configured to be taken out using.

Conventionally, as shown in FIG. 1, this sample-and-hold device has been equipped with a transistor 4 forming a charging circuit and a transistor 6 forming a discharging circuit in a holding capacitor 2 according to an input voltage during sampling.
and input sampling pulse P
transistors 8, 10, 12 and resistors 16, for controlling transistors 4, 6 in response to _s;
18 is installed, and a buffer amplifier 14 for extracting the terminal voltage of the capacitor 2 is installed. The input voltage to be sampled and held is applied to the input terminal 20, the sampling pulse is applied to the input terminal 22, and the power supply terminal 2
6 is applied with the power supply voltage Vcc, and the hold voltage is taken out from the output terminal 24.

In this sample-and-hold device, in an interval where there is no sampling pulse P _s , transistors 8 and 10 are off, transistor 6 is off, and at this time, transistor 12 is on, so transistor 4 is off. , the capacitor 2 is placed in an open state and its charging voltage is maintained. Furthermore, in the period of the sampling pulse P _s applied to the input terminal 22, the transistor 6 is turned on together with the transistors 8 and 10, and the transistor 12 is turned off due to the on state of the transistor 6, so the transistor 4 is It is activated or deactivated depending on the relationship between the input voltage applied to the terminal 20 and the voltage held by the capacitor 2. That is, input terminal 2
If the instantaneous value of the input voltage applied to the capacitor 2 is higher than the previous input voltage held by the capacitor 2, the transistor 4 becomes active and the capacitor 2 is charged through the transistor 4.
If it is low, transistor 4 remains inactive, capacitor 2 is discharged through transistor 6, and the discharge continues until the point where transistor 4 becomes active. In this way, the instantaneous value of the voltage to be held sampled at the sample time is held in the capacitor 2 for a certain period of time, and is taken out from the output terminal 24 as a hold output.

By the way, with this sample and hold device,
If the hold voltage of the capacitor 2 is higher than the base-emitter breakdown voltage of the transistor 4, there is a drawback that the hold function is lost when the transistor 12 is turned on. In this sample-and-hold device, since the input signal is sampled by turning on and off the transistor 12, a pull-up type high impedance condition is required as the input condition.

In addition, in this sample and hold device,
A in FIG. 2 is the input voltage waveform V _I applied to the input terminal 20, B in FIG. 2 is the sampling pulse P _s applied to the input terminal 22, and C in FIG. 2 is the hold voltage V taken out from the output terminal 24. Indicates ₀ . That is, in this sample-and-hold device, when switching the transistors 6 and 12, if the transition to the OFF state of the transistor 6 occurs earlier than the transition to the OFF state of the transistor 12, as shown in C in FIG. Therefore, there is a drawback that abnormal pulses P ₁ , P ₂ , and P ₃ are generated during sampling, and in order to prevent the generation of such abnormal pulses, measures are taken to compensate for the time delay of transistors 4, 6, and 10. is necessary.

Therefore, the present invention improves the hold function and eliminates irregularities such as time delays in switching operations, thereby preventing the occurrence of abnormal pulses.

The sample and hold device of the present invention divides an epitaxial layer by separating regions of the same conductivity type as the semiconductor substrate, sets this epitaxial layer as a base, and forms a first collector together with an emitter in the epitaxial layer. , and an input signal to be sampled and held at the emitter by connecting a hold capacitor between the first and second collectors of a lateral transistor whose second collector is set to the semiconductor substrate through a separation region, and
The capacitor is charged through a first collector in response to a sampling pulse and an input signal in addition to a sampling pulse at the base, and the capacitor is discharged by conduction between the first and second collectors. be.

Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings.

FIG. 3 shows an embodiment of the sample and hold device of the present invention, in which the same parts as those of the sample and hold device shown in FIG. 1 are given the same reference numerals.

This sample-and-hold device has a lateral type PNP transistor 30 (hereinafter simply referred to as transistor 30) installed as a charging circuit and a discharging circuit in a holding capacitor 2 during sampling, and the transistor 30 has a base B, an emitter E,
It includes first and second collectors C ₁ and C ₂ . In the transistor 30, the collector of the transistor 10 is connected to the base B, and a sampling pulse P s is applied through the transistor 10, and the emitter E is connected to the emitter of the transistor 4, and the sampling pulse P _s is applied through the transistor 4.
For example, input voltage as an input signal to be held.
V ₁ is applied, and a hold capacitor 2 is connected between the collectors C ₁ and C ₂ .

As shown in FIG. 4, the transistor 30 is constructed by, for example, forming a buried layer 34 on a P-type semiconductor substrate 32, and then forming an epitaxial layer 36 of a conductivity type opposite to that of the semiconductor substrate 32 thereon. Then, the epitaxial layer 36 is divided into a certain range by a separation region 38 of the same conductivity type as the semiconductor substrate 32, and
A base B, an emitter E, and a first collector _C1 are formed therein, and a second collector _C2 is formed therein.
is set on the semiconductor substrate 32 through the isolation region 38.

The operation of the above configuration will be explained with reference to FIG. In FIG. 5, A is the input voltage V ₁ ,
B shows the waveform of the sampling pulse P _s and C shows the waveform of the hold voltage V ₀ . In this sample-and-hold device, when there is no sampling pulse P _s , the transistor 10 is in an off state, so that no base current flows into the transistor 30 . Therefore, irrespective of the base current flowing through the transistor 30, the hold capacitor 2 is released, and the hold voltage of the capacitor 2 is maintained.

Next, a sampling pulse P _s is applied to the input terminal 22.
is applied, the transistor 10 turns on during the period of the sampling pulse P _s , and the input voltage at the next sample is higher than the input voltage at the previous sample that formed the hold voltage of the capacitor 2. At this time, the capacitor 2 is charged through the first collector C ₁ of the transistor 30 using the emitter potential of the transistor 4 as a clamping point. In this case, the collector of transistor 30
C ₁ is clamped to a potential (V _{E4 -V} C1E30(SAT)) which is the emitter potential of the transistor 4 minus the collector saturation voltage V _{C1E30(SAT) of} the transistor 30. Furthermore, if the input voltage at the time of the current sample is lower than the input voltage at the time of the previous sample when the hold voltage of the capacitor 2 was formed, the base potential V _B30 of the transistor 30 is lower than the input voltage at the time of the previous sample.
From the emitter potential of the transistor 30,
Until the emitter-to-emitter forward drop voltage drops to V _F ,
Capacitor 2 is discharged via transistor 30. That is, the discharge circuit of the capacitor 2 is constituted by a PNP transistor (Sub-PNP transistor) formed with the collector C ₁ of the transistor 30 as an emitter, the base B as a base, and the collector C ₂ as a collector. In this case, the potential of the collector _C1 of the transistor 30 is the potential obtained by subtracting the emitter-base voltage V _BE30 of the transistor 30 from the emitter potential V _E4 of the transistor 4, and adding the collector-base voltage V _BC130 of the transistor 30 to this value. It is clamped at (V _E4 - V _BE30 + V _BC130 ). Due to such a sampling operation, approximately the emitter potential of the transistor 4 is applied to the capacitor 2 during sampling, and the sampling pulse P
In the absence of _s , the transistor 30 is in an off state, so its potential (V _E4 ) is held in the capacitor 2.

As explained above, the lateral type PNP transistor 30 is used in the sampling section, and the capacitor 30 is charged through the collector _C1 according to the sampling pulse _Ps and the input voltage _V1 , and
Sample and hold is achieved by discharging the capacitor 30 through conduction between the collectors C ₁ and C ₂ , and the switching operation due to the sample and hold operation is performed by the transistor 30 , so there is no delay in operation time. Therefore, as shown in C in FIG. 5, an abnormal pulse unlike the conventional one does not occur. In addition, when the sampling on/off operation is performed by the transistor 30 in this way, a reverse bias voltage is not directly applied between the emitter and the base, so a hold voltage higher than the withstand voltage between the emitter and base is also possible. ,
Hold function is enhanced. In addition, in terms of withstand voltage, it can be used up to the withstand voltage between the collector C ₁ and the base of the transistor 30, and this withstand voltage is
0 has a lateral structure, so it is high, and generally the number + V
can be used up to a high value.

Since such an operation can be obtained, this sample-and-hold device has the advantage that charging/discharging imbalance is small. That is, if the collector current of the transistor 10 is I _C10 and the current amplification factor of the lateral type PNP transistor consisting of the emitter E, base B, and collector _C1 of the transistor 30 is β ₁ , then the charging current is given by β ₁ I _C10 . . On the other hand, if the current amplification factor of the Sub PNP transistor consisting of C ₁ of the transistor 30, emitter B, and collector C ₂ is β ₂ , then the discharge current is given by β ₂ I _C10 , and this value is the aforementioned β ₁ I _C10 Since it is almost equal to
The charging and discharging currents are balanced. To explain this in comparison with the conventional device shown in Fig. 1, in the case of the conventional device, as shown in the hold voltage waveform shown in Fig. 2 C, discharging b is slower than charging a, and the two are unbalanced. . On the other hand, in the case of this device, as shown in the hold voltage waveform shown in Figure 5C, charging a and discharging b rise or fall at almost the same slope due to constant current, and both are in a balanced state. I understand something.

Furthermore, since this sample-and-hold device does not switch the input signal applied to the input terminal 20, the impedance that enters the transistor 4 is sufficient as long as it can drive the transistor 4, and there is no need for it to be high impedance or low impedance. , the countermeasures required for conventional sample-and-hold devices are no longer required.

By the way, with this sample and hold device,
The hold voltage of capacitor 2 is approximately the emitter potential of transistor 4, but since transistor 30 has the structure shown in Figure 4, the collector area is wider than the emitter area, and this difference, although slight, appears as a voltage error. . In other words, base B.
Collector C ₁ voltage V _CIB and base B/emitter E
A relationship of V _C1B ≧ V _EB occurs between V EB and V _EB . If this becomes a problem, use a lateral structure in which the collector _C1 and emitter E have the same area as shown in FIGS. PNP transistor 30
You can use . That is, the collector-base voltage V _C1B and the emitter-base voltage V _EB
is V _CIB = V _EB , each current amplification factor βf, βr is βf
If ≒βr, the saturation voltage V _(SAT) 0 and V _C
B = V _EB , and the voltage error due to the difference can be made extremely small.

Note that the sample and hold device according to the present invention can be used as a device for driving a capacitive load if the input voltage for sample and hold is given as a constant voltage. In this case, since charging and discharging are performed by the transistor 30 according to the base input signal voltage of the transistor 4, there is an advantage that the capacitive load can be driven by one element, and the symmetry is also relatively good.

As explained above, according to the present invention, the epitaxial layer is set as the base, and the semiconductor substrate is connected to the second collector through the separation region of the epitaxial layer together with the emitter and the first collector installed in the epitaxial layer. Using a lateral transistor set as the collector, a hold capacitor is connected between the first and second collectors of this lateral transistor, and the hold capacitor is charged through the first collector according to the sampling pulse and input signal. In addition, since the capacitor is discharged by conduction between the first and second collectors, the hold function is enhanced and switching during sampling is improved when a charging/discharging circuit is configured using a plurality of transistors. It is possible to prevent irregularities in operating times, reliably suppress the occurrence of abnormal pulses, and achieve highly reliable sample and hold.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional sample and hold device, FIG. 2 is a diagram showing the operation of the sample and hold device shown in FIG. 1, and FIG. 3 is a diagram showing an embodiment of the sample and hold device of the present invention. Figure 4 is a diagram showing the structure of the lateral type PNP transistor used in the sample and hold device shown in Figure 3, Figure 5 is a diagram showing the operation of the sample and hold device shown in Figure 3, and Figure 6 is a diagram showing the operation of the sample and hold device shown in Figure 3. is a plan view showing another embodiment of a lateral type PNP transistor, and FIG. 7 is a plan view of another embodiment of the lateral type PNP transistor.
FIG. 2... Hold capacitor, 30... Lateral type
PNP transistor, 32...Semiconductor substrate, 36...Epitaxial layer, 38...Isolation region, _C1 ...First collector, _C2 ...Second collector, E...Emitter, B...Base.

Claims (1)

[Claims] 1. An epitaxial layer is divided by an isolation region of the same conductivity type as the semiconductor substrate, and this epitaxial layer is set as a base, and a first collector is formed in the epitaxial layer together with an emitter, and the semiconductor substrate is separated through the isolation region. A hold capacitor is connected between the first and second collectors of the lateral transistor with the second collector set to the input signal to be sampled and held at the emitter, and in addition to the sampling pulse at the base. and charging the capacitor through a first collector in response to an input signal;
and a sample-and-hold device that discharges the capacitor by conduction between the first and second collectors.