JPS6231874B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control system for a time-division digital exchange using storage program control.

Conventionally, in this type of system, the control of the communication path system and the control of the central processing system are separate systems, so that both control functions become redundant, and at the same time, the equipment becomes complicated.

Also, a method has been proposed in which the communication line system and the central processing system are controlled by the same microprocessor, but this method simply connects the communication line system equipment as an input/output device on the microprocessor, and The setter's software controls the communication line equipment, and the control software is stored in the same memory as other software. For this reason, it is necessary to prepare a special program for controlling with one microprocessor, which has the disadvantage that the scale of the control software becomes large and the burden on the microprocessor becomes heavy.

The present invention micro-controls both the control of the central processing system and the control of the communication path system, and as a result, integrates the two, eliminates the redundancy of both control functions, and stores various control memories for the communication path system of the time division switch. Taking advantage of the regular periodic operation of the drive, the execution cycles of the control microprograms for both devices can be set to a fixed ratio, simplifying the device configuration and making it easier to use the software of conventional time-sharing switches. The purpose is to be able to use it.

The present invention includes a central processing system that controls exchange connections and includes a main memory, a data buffer register, a memory address register, an instruction register, a register group for temporarily storing exchange connection information, and an arithmetic circuit;
In a time-division exchange equipped with a time-division communication path, a communication path system including a signal control memory for the time-division exchange, a communication path control memory for the time-division exchange, and a communication path system to which the communication path signal is relayed, each of the above-mentioned central processing systems A data bus connecting the elements and a data bus connecting each element of the communication path system are directly connected, and microinstruction control means for controlling the central processing system and microinstruction control means for controlling the communication path system are stored. a micro-instruction memory, a timing circuit connected to the micro-instruction memory, and a control means for causing the timing circuit to alternately execute the two micro-instruction control means at a preset ratio. shall be.

Next, a detailed explanation will be given with reference to the drawings.

The figure is a block diagram of an apparatus according to an embodiment of the present invention. The central processing system includes main memory MM, buffer register BR, memory address register MAR, instruction register IR, register group REG, and arithmetic circuit.
ALU is included, and these devices are connected to the data bus BUS
are commonly connected. In addition, the communication path system includes a time division communication path TDNW, a relay trunk TRK,
Includes communication path control memory NCM and signal control memory SCM.

The instruction register IR is connected to a micro-instruction address register CMA, and its output address signal is applied to the micro-instruction memory CM, and its read output is applied to each device via the micro-instruction register MIR.

Here, the feature of the present invention is that the communication path control memory NCM and the signal control memory of the communication path system are
The SCMs are commonly connected to the data bus BUS of the central processing system, are controlled by microinstructions stored in the microinstruction memory CM, and include a timing circuit TM that gives a period to the microinstruction memory CM. There is a particular thing.

The central processing system is controlled by a microcontrol system, and microprograms and data are stored in a microinstruction memory CM. On the other hand, the processing program (instruction words) and data necessary for exchange processing are stored in the main memory device MM, and these instructions and data are read out sequentially to the instruction register IR and buffer register BR by microcontrol. and performs a predetermined operation corresponding to the instruction, such as an operation between registers. In this case, the data used for these operations is read from the register group REG, processed by the arithmetic circuit ALU via the data bus BUS, and then transferred to the data bus again.
It is returned to the register group REG via the BUS. All these operations are executed by the microprocessor and microinstructions stored in the control memory CM.

On the other hand, in the communication path system of a time-division exchange, signals of subscriber lines and trunk lines are generally scanned at regular intervals, and the results of the monitoring are stored in a scanning memory that is part of the signal control memory SCM. In addition, time-division communication paths require a communication path control memory NCM that is accessed at regular intervals;
The NCM stores the address of the read memory and write memory (in the case of a time switch memory) or the highway number (in the case of a space switch) of the call data at each allocated time. Trunk TRK and subscriber line signal transmission data are
From the control memory SCM assigned to each subscriber line or trunk, the corresponding subscriber
Sent on SUB or trunk TRK.

Since each of the control memories of these communication path system devices is operated according to a certain fixed procedure, this operation sequence is stored as a microinstruction in the instruction memory CM of the microprocessor. Therefore, there are two independent types of microinstructions stored in the microinstruction memory CM, one for controlling the central processing system and one for controlling the communication path, but which one to execute is determined at a fixed period by the timing circuit TM. Fixedly assigned.

In this way, by micro-controlling the control logic of the central processing system and the control logic of the communication path system, and by sharing the micro-control and arithmetic circuits, it is possible to unify the functions of the control parts. As a result, redundancy in both control functions can be eliminated, efficiency can be increased, and exchange can be performed using the software of a conventional time division exchanger without preparing a special program.

Further, by allocating the instruction execution cycles of the central processing system and the communication path system at a fixed ratio, the microinstruction execution cycle mechanism can be simplified.

[Brief explanation of the drawing]

The figure is a block diagram of an apparatus according to an embodiment of the present invention. MM...Main memory, BR...Data buffer register, MAR...Memory address register,
IR...Instruction register, REG...Register group,
ALU...Arithmetic circuit, CMA...Micro instruction address register, CM...Micro instruction memory,
MIR...micro-instruction register, SCM...signal control memory for time-division exchange, NCM...talk control memory for time-division exchange, TDNW...time-division talk path, SUB...subscriber, TRK...relay trunk, BUS...data bus, TM...timing circuit.

Claims (1)

[Claims] 1. Main memory (MM), data buffer register (BR), memory address register (MAR), instruction register (IR), register group (REG) for temporarily storing exchange connection information, and arithmetic circuit. (ALU), and a central processing system that performs switching connection control, and a time division communication path (TDNW), a signal control memory (SCM) for a time division exchange, and a communication path control memory (NCM) for a time division exchange, In a time division exchange equipped with a communication path system to which communication path signals are relay-connected, a data bus connecting each element of the central processing system and a data bus connecting each element of the communication path system are directly connected. , a microinstruction memory (CM) storing microinstruction control means for controlling the central processing system and microinstruction control means for controlling the communication path system;
A timing circuit (TM) connected to the micro-instruction memory; and a control means for causing the timing circuit to alternately execute the two micro-instruction control means at a preset ratio. A control method for time division switching equipment.