JPS6235275B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate semiconductor device that operates with low power.

In recent years, advances have been made in technology for constructing large-scale integrated circuits by miniaturizing insulated gate (MIS) transistors. In large-scale integrated circuits, since a large number of elements are used, it is desirable that the power consumption of the constituent elements be low.

FIG. 1 shows an example of this type of insulated gate type semiconductor device conventionally used. In the figure, a first layer having a high p-type impurity concentration is placed on an insulating substrate 1.
A source region 2, an n-type active layer 3, and a first drain region 4 having a high p-type impurity concentration are arranged in parallel to form a first transistor. Further, on the insulating substrate 1, a second drain region 5 with an n-type high impurity concentration, a p-type active layer 6, and a second source region 7 with an n-type high impurity concentration are arranged in parallel to form a second transistor. ing. First and second source electrodes 8 and 9 are formed on the first and second source regions 2 and 7, respectively,
Furthermore, it is connected to first and second source terminals 10 and 11. Furthermore, gate electrodes 13 are provided on the n-type active layer 3 and the p-type active layer 6 via a gate insulating film 12, respectively, and both gate electrodes 13 are connected to a common gate terminal 14. Furthermore, a common drain electrode 15 is formed on the first and second drain regions 4 and 5.
is formed and connected to the common drain terminal 16.

In a semiconductor device having such a configuration,
The first source terminal 10 with respect to the second source terminal 11
The common gate terminal 1 is operated by applying a positive voltage to the common gate terminal 1.
4, the common drain terminal 16
The inverted output signal can be extracted from On this occasion,
The first transistor and the second transistor are in a relationship such that when one is conductive (ON), the other is not conductive (OFF), and current flows between the second source terminal 11 and the first source terminal 10. Flows only when the NO-OFF state is switched, so power consumption is low.

However, as shown in Figure b, the area of the first transistor is larger than the area of the second transistor, making it difficult to increase the degree of integration, and at the same time increases parasitic capacitance, making it difficult to increase speed. It had the disadvantage of being large in number.

An object of the present invention is to provide a low-power semiconductor device that operates at high speed, has a small area, and has a simple manufacturing process.

In order to achieve such an object, a low power semiconductor device according to the present invention uses a transistor having a pn junction anode terminal and exhibiting triode characteristics as a first transistor, and a drain of the first transistor. area and the second with pentode characteristics
It has a common structure with the drain region of the transistor. Hereinafter, a low power semiconductor device according to the present invention will be explained in detail using the drawings.

FIG. 2a is a sectional view showing an embodiment of a low power semiconductor device according to the present invention, and FIG. 2b is a schematic plan view thereof. In the figure, on an insulating substrate 1, for example, an anode region 17 having a p-type high impurity concentration, an n-type active layer 18, a drain region 19 having an n-type high impurity concentration, an n-type active layer 20, an n-type high impurity concentration A series of concentrated source regions 21 are formed,
The first three constitute a first transistor, and the latter three constitute a second transistor. The thickness of the n-type active layer 18 constituting the first transistor is
The Debye length is suppressed to less than three times the inherent Debye length of the semiconductor constituting 8. An anode electrode 22 is provided on the anode region 17 and the source region 21, respectively.
A source electrode 23 is provided, an anode terminal 24,
It is connected to the source terminal 25. n-type active layer 1
A gate electrode 13 is formed on both 8 and 20 with a gate insulating film 12 interposed therebetween, and a common gate terminal 26
It is connected to the. Furthermore, a common drain region 19
A drain electrode 27 is provided on top of the drain electrode 27 and connected to a drain terminal 28 . The operation of the low power semiconductor device having the above configuration will be explained in detail below.

To operate this device, first, a voltage is applied to the source terminal 25 so that the anode terminal 24 becomes positive, and then a signal is input to the common gate terminal 26. At this time, if the potential of the common gate terminal 26 is close to the potential of the source terminal 25, the first transistor is conductive (ON operation) and the second transistor is not conductive (OFF operation). Therefore, the voltage at the drain terminal 28 is high at this time. Conversely, when the potential of the common gate terminal 26 is close to the potential of the anode terminal 24, the first transistor is in an OFF operation, the second transistor is in an ON operation, and the drain terminal 28 is at a low potential. In this way, the signal input to the common gate terminal 26 is inverted and output to the drain terminal 28. This mechanism is similar to the device shown in FIG. 1, and current flows between the source terminal 25 and the anode terminal 24 at the first
It operates with low power only when the ON-OFF state of the second transistor is switched.

However, unlike the embodiment shown in FIG. 1, this embodiment has the characteristic that a large mutual conductance (gm) can be obtained because the first transistor has good triode characteristics. This will be explained in detail below.

First, the structure of only the first transistor portion can be shown as shown in FIG. That is, a cathode region (corresponding to the drain region in FIG. 2) 19 having a high n-type impurity concentration is formed on the insulating substrate 1;
An n-type active layer 18 and a p-type high impurity concentration anode region 17 are formed, a gate electrode 13 is provided on the n-type active layer 18 via a gate insulating film 12, and a cathode region 19 and an anode region 17 are formed. On top are a cathode electrode 27 and an anode electrode 22, respectively.
is formed. Thickness t _c of n-type active layer 18
As mentioned above, is less than three times the Debye length L _DE inherent to the n-type semiconductor constituting the n-type active layer 18 . The Debye length L _DE in this case is the so-called extrinsic Debye length, It is represented by. Here, ε _S is the dielectric constant of the semiconductor, which in the case of silicon is 11.7×8.85×10 ^-14
(F/cm), k is Boltzmann constant 1.38×10 ^-23
(J/K), T is the absolute temperature (〓), q is the unit charge of 1.6×10 ^-19 (C), N _D is the carrier concentration of the semiconductor containing impurities, and the impurity concentration is near room temperature (300〓). The value is approximately equal to . In such a transistor, [A] (i) First, for example, the thickness t _c of the active layer is set to 0.26
(μm), the Debye length L _DE is 0.22 (μm), the anode-cathode voltage V _AK is positive, and the gate-cathode voltage V _GK is negative as shown in Figure 4a. active layer 18
The inside of the active layer 18 is almost depleted, and an inversion layer due to holes is formed at the interface between the active layer 18 and the gate insulating film 12. On the other hand, since V _AK >0, holes are injected from the anode region 17 to the active layer 18 and from the active layer 18 to the cathode region 19 through this inversion layer. At the same time, from the cathode region 19 to the active layer 18 near the interface,
Electrons are injected from active layer 18 into anode region 17 . Therefore, the anode current I _AK increases without being saturated as V _AK increases, as shown in FIG. 5A for the case of V _GK =-1 (V). When V _GK is a positive voltage, electrons are excessively accumulated throughout the active layer 18 as shown in FIG. 4b. At this time, let n be the electron concentration in all the active layers 18, n _i be the carrier concentration of the intrinsic semiconductor, and hole concentration p inside the active layer 18 at a low injection level.
is approximately given by p=n _i2/o . Therefore, as shown in B, C, and D of Figure 5a, V _GK
As n increases from 0 (V) to 1 (V) to 2 (V), the fermi potential of electrons inside the active layer 18 increases, and as a result, the built-in・The potential effectively increases and the anode current I
_AK decreases.

(ii) Next, when the anode-cathode voltage V _AK is negative and the gate-cathode voltage V _GK is negative, first, if V _GK <V _AK <0,
As shown in FIG. 4c, an inversion layer of holes is formed in the entire interface region of the active layer 18 with the gate insulating film 12. At this time, since V _AK <0, the cathode region 19 and the hole inversion layer are reverse biased, but since the hole concentration in the inversion layer is high, there is a bias between the cathode layer 19 and the active layer 18. _IAK flows as an anode current having properties of tunnel current or avalanche current. This I _AK increases as |V _AK | increases. Moreover, when |V _GK | increases, I _AK also increases because the hole concentration in the inversion layer increases. Moreover, in the case of V _AK <V _GK <0,
At a certain point on the anode region 17 side of the interface between the active layer 18 and the gate insulating film 12, V _GK
The electric field due to V _AK becomes stronger than the inversion layer binding electric field caused by V AK , and a pinch-off phenomenon occurs in which the inversion layer disappears, as shown in FIG. 4d. In this case, the inversion vanishing point is called a pinch-off point, and the anode voltage at which pinch-off occurs is called a pinch-off voltage V _p . This pinch-off increases the resistance value between the pinch-off point and the anode region 13, which becomes sufficiently larger than the resistance value of the inversion layer. Therefore, when |V _AK | |V _P |, even if |V _AK | is increased, the anode current I _AK hardly increases and becomes saturated. This situation is shown in Figure 5b, where V _GK is -1 and -1 for A, B, and C, respectively.
The characteristics in the case of 2 and -3 (V) are shown.

[B] On the other hand, the thickness of the active layer 18 t _c (0.62μ
Considering the case where m) is much larger than the Debye length L _DE (0.19 μm), (i) When V _AK is applied positively and V _GK is negative, an inversion layer by holes is formed, and [ A〕(i)
By a mechanism similar to that described in , I _AK becomes V _AK
As a result, it increases exponentially with the increase of |V _GK |, and as a result, the
The characteristics shown in are obtained. That is, curves A, B, and C have V _GK of 0, -1, and -2, respectively.
The characteristics in case (V) are shown. On the other hand, V _G
When _K is positive, the high-density accumulation region of electrons is located from the interface of the active layer 11 with the gate insulating film 12.
Limited to less than 3L _DE , all active layers 1
In order not to cover 1, [A](i)
There is no effect of increasing the fermi potential as described in , and the active layer 18 increases with increasing V _GK .
By increasing the number of electrons that can pass through,
I _AK increases. I _AK also increases exponentially as V _AK increases, resulting in a characteristic curve as shown in FIG. 6b. A, B, and C in the figure show cases where V _GK is 0, 1, 2, and (V).

In this way, current non-saturation characteristics can be obtained even when t _c >>L _DE , but changing V _GK only changes its slope, and the point at which I _AK rises remains the same. Also, even if V _GK > 0 or V _GK < 0, V
The slope is never smaller than when _GK = 0. Therefore, the operating range in which an arbitrary _IAK can be obtained is extremely small.

On the other hand, since the transistor used as the first transistor in the low-power semiconductor device of the present invention has good current non-saturation characteristics as shown in FIG. 5a, the value of V _GK is appropriately selected. By doing this, any I _AK can be obtained at any V _AK .

In this way, the current non-saturation characteristic shown in FIG. 5a can be obtained only when the thickness of the active layer 18, t _{c ,} is not very large, about less than three times the Debye length L _DE . , The following can be considered as one theoretical basis.

First, in order for the transistor shown in FIG. 3 to exhibit the characteristics shown in FIG. 5a, it is necessary that electrons be excessively stored in all active layers 18. That is, as shown in FIG. 7, the interface A between the active layer 18 and the gate insulating film 12
When applying V _GK which is larger than the flat band voltage _{V FB of} There must be.

Therefore, the depth d of the carrier distribution in the active layer 18 when V _GK >V _FB will be approximately determined.

First, the distribution state of this carrier is shown by a model as shown in FIG. Here, x=0 represents interface A. First, n(x) can be approximately calculated from the following Poisson equation.

d ² φ/dx ² =qn(x)/ε _S (1) Here, φ is the potential measured from the Fermi level of the semiconductor. n(x) is expressed as follows.

n(x)=N _D exp(qφ/KT) ...(2) By combining equations (1) and (2), and setting the following boundary conditions, n
Solve (x).

Here, φ _S is the surface potential at x=0 (interface A). n(x) is expressed by the following formula.

n(x)=N _D {tan ² [x/L _DE −C]+1} C=tan ⁻¹ (√()−1) Usually, it is easy to set φ _S ≫kT/q (0026 (V)) Therefore, it becomes Cπ/2. Therefore, by inserting the condition n(d)= _ND , d is given by the following equation.

When d=π/2L _DE 1.57L _DE , that is, t _c <1.57L _DE , n(x)>N _D in all active layers 18, and the desired requirement is satisfied.

As mentioned earlier, this conclusion is a theoretical approximation, and in reality, the influence of other conditions is added, and t _c
If it is about <3L _DE , desired current non-saturation characteristics can be obtained.

As described above, since the first transistor exhibits good triode characteristics and a large mutual conductance (gm) is obtained, the embodiment of FIG. 2 operates at a higher speed than the conventional one.

Furthermore, as is clear from the figure, since the first transistor and the second transistor constituting the device overlap each other while sharing the drain region 19, the device area is small and the structure is simple. Another advantage is that the number of manufacturing steps is small.

As explained above, according to the low power semiconductor device according to the present invention, by using a transistor exhibiting good current non-saturation characteristics as the first transistor, a large mutual conductance value can be obtained, so that high-speed operation is possible. It is possible. In addition, since the first transistor and the second transistor are composed of semiconductor regions that are horizontally arranged in common on an insulating layer, the element area is small and the isolation between the elements is small. It has various excellent effects such as easy construction and easy construction of large-scale integrated circuits with excellent operating characteristics.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view and a schematic plan view showing an example of a conventional low-power semiconductor device, and FIG. 2 is a cross-sectional view and a schematic plan view showing an example of a low-power semiconductor device according to the present invention. 3 is a sectional view and a schematic symbol diagram showing the first transistor part in FIG. 2, FIG. 4 is a principle diagram explaining the operating mechanism of the transistor in FIG. 3, FIG. 5 is a voltage-current characteristic diagram, 6
The figure shows the voltage-current characteristics of a device in which the thickness of the active layer of the transistor shown in Fig. 3 is more than three times the Debye length. Schematic cross-sectional view, No. 8
The figure shows the carrier distribution map. 1... Insulator substrate, 12... Gate insulating film, 1
3... Gate electrode, 17... Anode region, 18
... n-type active layer, 19 ... drain region, 20 ...
... n-type active layer, 21 ... source region, 22 ... anode electrode, 23 ... source electrode, 26 ... common gate terminal.

Claims (1)

[Claims] 1 A source region formed of a highly impurity concentration semiconductor having a first conductivity type arranged in series on an insulating substrate, a first conductivity type active layer, and a high impurity concentration semiconductor having a first conductivity type arranged in series on an insulating substrate. a drain region formed of a first conductivity type active layer, an anode region formed of a highly impurity concentration semiconductor having a second conductivity type, a gate insulating film formed on both of the active layers, and a gate insulating film formed on both of the active layers; a gate electrode formed on the insulating film, a source electrode formed on the source region,
an anode electrode formed on the anode region;
a drain electrode formed on the drain region, and a first conductivity type active layer sandwiched between the anode region and the drain region has a Debye length of 3 which is specific to the semiconductor constituting the first conductivity type active layer. 1. A low-power semiconductor device, characterized in that the device has a thickness less than double the thickness of the device, and both gate electrodes are connected to a common terminal.