JPS6235697B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of the Invention The present invention relates to a reset method in a system in which microcomputers are arranged in parallel.

(b) Background of the Invention As microcomputer control of equipment such as vending machines is developed, inputs and outputs from the microcomputer control section become extremely large, and the weight of development and quality is concentrated on this control section. Another drawback is that as the degree of integration of the board on which the microcomputer is mounted increases, wiring processing becomes troublesome, and it also takes time and effort to detect a failure location in the event of an abnormality. Therefore, an effective method is to configure a main microcomputer that centrally controls the operation of the device, and a slave microcomputer that executes processing appropriate for each functional block for each terminal. It also has the advantage of being able to At this time, the main side microcomputer specifies the operation mode to the slave side microcomputer and performs the operation of the equipment while exchanging data with each other.However, if an abnormality occurs in any one of the slave side microcomputers, how can the multiple microcomputers be effectively controlled? The question is whether to reset the system.
Generally, such a system reset is performed by installing a watchdog timer circuit as an abnormality detection means in each microcomputer on the main side and slave side, and when an abnormality occurs, the system outputs a reset signal to itself and the other side with which data is exchanged. was becoming expensive.

(c) Object of the Invention In light of the above points, the present invention provides a reset system that can effectively reset the system simply by providing an abnormality detection circuit in the main microcomputer.

(D) Overview The system is equipped with a main side microcomputer that centrally controls the entire system and a slave side microcomputer that executes processing at the terminal, and data is exchanged via signal lines for mutual transmission and reception under the initiative of the main side. The system is configured to transfer data to each other, is provided with abnormality detection means for detecting program runaway on the main side, and connects the reset terminal on the slave side to the transmission signal line on the main side via a delay circuit, If the main side specifies the data transfer mode, but the slave side does not enter the data transfer mode, the main side outputs an "L" signal to the transmission signal line for a period longer than the delay time of the delay circuit. The slave side is reset, and the main side is reset by the abnormality detection means when an abnormality occurs, and after the reset is released, the slave side is reset by outputting an "L" signal to the transmission signal line for a period longer than the delay time of the delay circuit. do.

(E) Embodiments of the Invention Figure 1 shows an example of a circuit according to the present invention, where 1 is a main side microcomputer (hereinafter referred to as the main side), ₂₁ ... _2o is a slave side microcomputer (hereinafter referred to as the main side). (abbreviation) and main side 1 and 2
They are connected to each other by real signal lines. 4 is an integrating circuit consisting of a resistor R _{1 and} a capacitor C ₁ and is supplied with _a power supply V _{cc . A} Zener voltage Vz is applied to the (-) input terminal of the comparator 5 by a Zener diode 7 to which the power supply _Vcc is supplied via a resistor _R4 . Further, D ₁ is a diode for discharging the capacitor C ₁ when the power supply V _cc is cut off. Further, the output terminal of the comparator 5 is connected to the reset terminal R of the main side 1, and the abnormality detection means 3 is connected to the port _P1 of the main side 1. The abnormality detection means 3 is, for example, a watchdog timer circuit, and the output port P ₁ of the main side 1
As the program progresses, when pulses at predetermined intervals are no longer supplied, an "H" level signal is output to connection point A. Each slave side 2 ₁ ... 2 _o has a reception terminal RxDS and a transmission terminal TxDS connected to a transmission terminal TxDM ₁ ...TxDM _o and a reception terminal RxDM ₁ ...RxDM _o of the main side 1. Further, the reset terminal R of each slave side 2 ₁ . . . 2 _o is connected to the signal line from the main side 1 through a delay circuit 8 and an integration circuit 6. The delay circuit 8 is composed of an inverter 17, a resistor _R5 and a capacitor _C2 connected in series between a +5V power supply and ground, a protective resistor _R6 , and a diode _D2 . Diode D ₂
is to prevent charging of the capacitor _C2 when the output of the inverter 17 becomes "H", so that the delay time constant is determined only by the resistor _R5 and the capacitor _C2 . The integrating circuit 6 is composed of an inverter 18, a resistor R ₇ and a capacitor C ₃ connected in series between the +5V power supply and ground.

The operation of the above configuration will be explained. First, when the power is turned on, the power supply voltage _Vcc (24V in this example) rises sharply, and the main side 1 and slave side ₂₁ ... _2o are supplied with the predetermined operating voltage _VDD , and the comparator 5 is also supplied with the necessary operating voltage VDD. An operating voltage is supplied, and a Zener voltage _Vz from a Zener diode 7 is applied to each (-) input terminal. On the other hand, the potential at point A V _A
gradually increases due to the time constant of the capacitor _C1 and the resistor _R1 , so the comparator 5 produces an "L" level output, and the main side 1 is connected to the reset terminal R.
is being reset due to "L". Further, after the power is turned on, the capacitor _C2 is charged and the output side of the inverter 18 becomes "L", and the slave sides ₂₁ ... _2o are reset because the reset terminal R is "L". Therefore, the potential at point A is V
The voltage divided by the resistors R ₂ and R ₃ of _A is the Zener voltage V
When _z is exceeded, the output of the comparator 5 becomes "H", and the reset of the main side 1 is canceled and the input/output is set to the initial state. At this time, the transmit terminal
TxDM ₁ ...TxDM _o becomes "H", so the output side of inverter 17 becomes "L" and the capacitor
_C2 is discharged and the output side of the inverter 18 becomes "H". Therefore, the capacitor _C3 is charged and the reset terminal R of the slave side ₂₁ ... _2o becomes "H", so that the reset is released.

The main side 1 and slave sides ₂₁ ... _2o operate according to each program, and the main side 1 asynchronously transfers 11-bit serial data to either slave side ₂₁ ... _2o as necessary. We share each other. In this example, there is 1 between main side 1 and slave side 2 ₁ ...2 _o .
The time required to transfer bit data is set to 1/1200S, so one serial data transfer requires 11/1200S. Therefore, even if the main side 1 specifies the data transfer mode for one of the slave sides ₂₁ ... _2o , the slave side 21... _2o
...2 If _{the o} program runs out of control, it will not enter data transfer mode. In such a case, the main side 1 outputs "L" from the transmission terminal TxDM ₁ ...TxDM _o corresponding to the slave side 2 ₁ ...2 _o where the abnormality has occurred for a period exceeding the delay time of 20 ms set in the delay circuit 8. . As mentioned above, one data transfer requires 1/1200S, but if a signal is output from the transmission terminals TxDM ₁ ...TxDM _o for a long period of time exceeding 20ms, this means that this is not a normal data transfer. is detected by the delay circuit 8. That is, inverter 17
When the output side of is “H”, the capacitor _C2 is charged, but the output side of the transmitting terminal TxDM ₁ …TxDM _o is “L”
When a level signal is supplied for 20 ms or more, the input side of the inverter 18 becomes "H". Therefore, since the output side of the inverter 18 becomes "L", the capacitor _C3 is discharged, and the slave side ₂₁ ... _2o is reset because the reset terminal R becomes "L". After that, the main side 1 connects the transmission terminal TxDM ₁ ...
When TxDM _o is set to "H", the capacitor _C2 is discharged and the output side of the inverter 18 becomes "H", the capacitor _C3 is charged, and the slave side ₂₁ ... _2o is released from reset and operates from the initial address of the program. Start.

Such an abnormality on the slave side ₂₁ ... _2o is detected when, for example, there is no response even though the main side 1 requests preparation for data transfer. FIG. 2 is a functional block diagram showing an example of data transfer. In this example, data is transferred from the main side 1 to one of the slave sides 2. In the figure, the main side 1 includes a transmission control device 9 that stores transfer data and outputs a transfer preparation signal RDY ₁ through a transmission terminal TxDM in transfer mode, and a clock pulse generation circuit 10 that converts the transfer data into serial data. Shift register 1 outputs in synchronization with clock pulse CL ₁ of
1, and a timer device 12 connected to the receiving terminal RxDM. In addition, the slave side 2 outputs a response signal RDY ₂ from the transmission terminal TxDS for a certain period of time by setting the flip-flop circuit 13 which is set by the first "L" signal introduced to the reception terminal RxDS, and the flip-flop circuit 13. A one-shot circuit 14 and a sampling device 16 for sampling transfer data in synchronization with a clock pulse CL ₂ from a clock pulse generating circuit 15 are provided. FIG. 3 shows the format of the main side transmission terminal TxDM and the slave side transmission terminal TxDS, and the operation will be explained. Normally, each transmitting/receiving terminal
TxDM/RxDS/TxDS/RxDM is in the mark state "H", but in the transfer mode, the transmission control device 9 sets the transmission terminal TxDM to "L" to signal transfer preparation.
Output RDY ₁ . Therefore, the flip-flop circuit 13 detects and sets the transfer preparation signal RDY ₁ , and the one-shot circuit 14 sets the transmission terminal for a certain period of time.
Set TxDS to "L" and output response signal RDY ₂ . On the other hand, the transmission control device 9 sets the transfer data in the shift register 11, and the reception terminal RxDM
The clock pulse generating circuit 10 operates as the clock pulse CL1 falls from "H" to "L", and the shift register ₁₁ shifts and sequentially outputs the transfer data from the transmission terminal TxDM in synchronization with the clock pulse CL1. In this example, the transfer data consists of a 1-bit start bit "L", an 8-bit data character, and a 2-bit stop bit "H", so the clock pulse generation circuit 10 is configured to output 11 clock pulses _CL1 . has been done. The sampling device 16 is a flip-flop circuit 13.
Clock pulse generation circuit 1 that operates by setting
The transfer data is sampled in synchronization with the clock pulse _CL2 of 5, and when the sampling of 11 bits of transfer data is completed, the flip-flop circuit 13 is reset and the data transfer is completed. However, when the response signal RDY ₂ is not inputted from the slave side 2 within a certain period even though the main side 1 outputs the transfer preparation signal RDY ₁ , the timer device 12 outputs an abnormality detection signal. Also main side 1
When the slave side 2 does not transmit a response signal or code data indicating data transfer even though the main side 1 specifies data transfer from the slave side 2, the main side 1 determines that the slave side 2 is abnormal.

Furthermore, if an abnormality occurs in the main side 1 itself, a reset signal of "L" is generated from the watchdog timer circuit 3 for a certain period of time, and the divided voltage of the A point potential V _A by the resistors R ₂ and R ₃ increases the Zener voltage V _z . In order to divide, the comparator 5 outputs "L". Therefore, the main side 1 is in a reset state for a certain period of time. After the reset is released, the main side 1 sets the input/output to the initial state, and then starts processing from the initial address of the program. In addition, in the first flow of processing, the main side 1 outputs "L" from the transmission terminals _TxDM1 ... _TxDMo for the above period to reset the slave sides ₂₁ ... _2o once, and after the reset is released, the slave sides ₂₁ ... 2 _o starts processing from the initial address of the program.

(f) Effects According to the present invention, in a system including a plurality of slave microcomputers for each terminal with respect to a main microcomputer, the reset is also performed on the slave side in order to be achieved under the initiative of the main side. There is no need to provide each abnormality detection means, and the system becomes inexpensive. Moreover, since the main side uses the data transmission signal line to reset the slave side, no special reset signal line is required.

[Brief explanation of the drawing]

Figure 1 is a diagram showing an example of a circuit according to the present invention, Figure 2 is a functional block diagram when data is transferred from the main side to the slave side, and Figure 3 is a diagram showing each transmission when data is transferred from the main side to the slave side. Trust terminal TxDM
FIG. 3 is a diagram showing the format of TxDS and TxDS. 1... Main side microcomputer, 2 ₁ ~ 2
_o ...Slave side microcomputer, 3...Abnormality detection means, 8...Delay circuit.

Claims (1)

[Claims] 1 Equipped with a main side microcomputer that centrally controls the entire system and a slave side microcomputer that executes processing at the terminal, data is transferred via signal lines for mutual transmission and reception under the initiative of the main side microcomputer. In addition to providing an abnormality detection means for detecting an abnormality in the main side microcomputer, the slave side microcomputer does not enter the data transfer mode even though a data transfer mode is specified for the main side microcomputer. A reset terminal of the slave microcomputer is connected to the signal line for transmission of the main microcomputer via a delay circuit. Upon detection of an abnormality in the slave microcomputer, the microcomputer resets the slave microcomputer by outputting a signal to the transmission signal line for a period longer than the delay time of the delay circuit, and the main microcomputer resets the slave microcomputer when the error occurs. A reset method that is reset by the abnormality detection means.