JPS6236263B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to real-time data processing apparatus and, more particularly, to apparatus for processing "wait period" instructions.

For example, in real-time data processing equipment used to control telecommunications switching equipment and the like, it is often necessary to suspend processing for specified periods of time. For example, during call setup, the accumulation process of dialed digits is interrupted after each digit is received for a predetermined period of time (eg, an interdigital pause). Such behavior is called a "wait period" command,
Alternatively, this can be accomplished by executing a microinstruction, where the instruction itself specifies a time delay. In many other cases, ``wait period'' microinstructions are also planned, and in high capacity switching systems using processor stored program control schemes, the number of concurrent interrupt operations is substantial.

The object of the invention is to arrange all "waiting period" instructions in some kind of ordered list and to manage this list in a data processing device so that when the waiting period ends, the interrupted processing can be resumed. This is how it was done.

According to the present invention, there is provided a real-time data processing apparatus for handling processes having "waiting period" instructions, each of said instructions specifying one of a plurality of predetermined periods, and each of said instructions specifying one of a plurality of predetermined periods, and All processes that are interrupted by instructions with the same duration are
The timing chain headers are connected to each other in the order of their interruption times and are connected to timing chain headers that hold real-time information about the completion of the waiting period of the first process in the chain, and all the timing chain headers are in the list. The data processing device has a process for searching the list when a predetermined time interval has elapsed to ascertain which processes have completed their waiting period.

Further, according to the present invention, there is provided a real-time digital data processing apparatus that handles a plurality of processes each having a "waiting period" instruction specifying a plurality of predetermined periods, and the data processing apparatus has a memory for storing information regarding processing and at least one processor unit, and the processor is adapted to execute the processing.
Each process has an information segment in memory that holds the working parameters of that process at the time the process was interrupted, and that information segment has an indication of the time by which the waiting period for that process should be completed. The information segment link information forms the information segments of all processes interrupted by instructions having the same specific period into a first link list arranged in the order of the time when the processes were interrupted, and One linked list is linked to the timing chain header segments stored in memory and is exclusively assigned to the particular time period. The timing chain header segment stores a wake-up value indicating when the waiting period for the first information segment on the first linked list is complete. Each timing chain header has header link information that forms the timing chain header segment in the second list. The data processing device has a timing chain search process that causes the second list to be searched to ascertain the process for which the waiting period has been completed, and the device also monitors a time interval and at the end of the interval, the timing chain search process and a device for operating an interval timing device conditioned to operate the interval timing device.

Next, the present invention will be explained according to the accompanying drawings.

Before beginning a detailed description of the apparatus of the present invention, a central processor unit suitable for use in the data processing apparatus of the present invention will be briefly described. Such a central processing unit is shown in FIGS. 1a and 1b.
Figure 1a and Figure 1b are placed side by side, with Figure 1a on the left side.
A diagram is placed. Central processing unit has leads SOHCS, SDH, SIHCS and SIH
connected to the memory module via.
Leads SDH and SIH are the output and input data paths of the memory unit, respectively;
SOHCS and SIHCS are the output and input control signal highways to the memory module, respectively.

The central processing unit is a microprogrammed controlled μPROG that controls the data transfer gates that turn the unit's highways on and off for data passage. Its processing units are arithmetic unit MILL, comparator
COMP, instruction register IR, operation register OPRG,
It has a memory communication register SDIREG and three register stacks. The unit consists of a so-called functional register structure, which is detailed in GB 1329721. The stack comprises a general purpose register ACC STK (details shown in Figure 2) and functional registers divided into a base stack BASE STK and a limit stack T/CLMT STK, which are shown in detail in Figure 3. There is. The central processor is
“System250―a fault―tolerant, modular
“Processing system for control applications”
Pages26 to 34 of issue 27 of systeme
It is particularly suitable for use in modular processing equipment of the type described in Technology. In such systems, the functionality structure is such that a master list of all resources is maintained in a so-called system functionality table, with each process indicating the resources it is allowed to access. It contains a list of pointers to that table. Additionally, each process has a so-called dump stack (shown in Figure 4), which is maintained in a common memory. The common memory is the dump stack function register in the function register stack in the processor unit that executes the process.
Directed by DCR. Dump stack DA
is the sequence control register SCR and all working function registers RSP WCR0 through RSP
It is used to store the contents of the general register stack ACC STK when a change occurs (ie, when processing is interrupted) with the value of WCR7. Moreover, the dump stack DA of each process is
RIGHT LINK, LEFT LINK and
INCREMENT values, and these values are later used in operations necessary to implement embodiments of the present invention.

Each process is based on the so-called processing base (Figure 5) PB
and it processes dump stack
A list of key pointers that includes pointers to the WPDS, job link block WJLB, trap flag WFL, scheduler workspace link WLINK, and the workspace that holds the list of posts and wait flags.

The operations performed by the multiprocessor system of system 250 are organized by scheduler processes that operate on a running list. This list is shown in FIG. 6 and consists of three information blocks, one entry for each processor unit in the device. Figure 6 shows the arrangement of running lists for a three processor unit system, which lists, for each processor, (i) process-based pointers to the processes to be executed on the processor, (ii) each execution process. and (iii) a dump stack pointer to a previously executed operation on the processor unit.

Each processor has its own current time block, which is stored in the time function registers.
Addressed by TCR (Figure 3). TCR
The block directed by WIT,
It consists of three words named WITSUP and WETNI. WIT is the interval timer, WETNI is the estimated time when the next timer interrupt will occur, and WITSUP is used to record the interval timer value when one processor interrupts the other.

The time information for the waiting period is based on the "current time" for conceptual monitoring. There is actually no single value. Instead, each processor has its own version, and an external system controller (not shown) is kept synchronized with the processor.

Each version of the current time is maintained as follows. The word named WETNI is used to maintain a constant real time at which the next timer interrupt occurs, ie, the real time at which WIT is zero. Current time is CT
=WETNI−WIT is given. When WIT is updated at the end of a time interval to trigger a new internal timeout, WETNI is naturally changed by the same amount. The value WIT is set by the interval time process to a value indicating the number of 100 microsecond periods that elapse before the interval time process is activated again. Each processor is to be interrupted at 100 microsecond intervals and its interval timer word WIT is decremented by one and tested for zero conditions. When a zero condition is encountered, the interval timeout completes and re-entry is made into the process waiting for an interval to expire.

The actual interval time process used in the embodiment of the invention is the so-called "Usherette" process, which will be considered in detail later.

Each CT is normally an incremental value, but there are two exceptions to this. That is, (a) When time values are about to overflow the capacity of one word, all time values are reduced by a fixed value (generally 3 minutes).

(b) CT may undergo small corrections when synchronization is performed.

The use of the word named WITSUP is doubled. When one processor wants to interrupt another processor, it sets the other processor's WIT to zero (if it is not already zero or negative). The previous value is WITSUP so that the original interval being timed can be set again later. Also WITSUP
is used to achieve single threading of operations on a block. Thus, a value of -1 indicates that the block is "locked."

In the system according to the invention, processing can be interrupted for a time interval that specifies itself. The interval can take an integer value from 1 to a fixed maximum value, and there is no limit to the number of processes that can be interrupted simultaneously.

The data structures used to perform the functions are (i). The number of simultaneously interrupted processes is as large as an elbow, (ii). It is designed to be useful for applications where the number of time intervals available at any instant is relatively small. In a practical example, the number 30 is said to be a reasonable number, but there are many operations that request at different times and therefore need to be "waked up" at different times. Arrangements are made so that certain intervals are valid for .

All processes that are suspended waiting for the end of the same time interval are linked together in the requested order and connected to a "timing chain header". The chain is accomplished by the RIGHT LINK (RL) and (LEFT LINK (LL)) pointers in the processing dump stack as shown in Figure 7. In an example with three processes, we have dump stacks 1, 2, and 3, each interrupted and "requested" for a 15 ms interval. Since they are arranged to have slots,
Multiplied by 15 and 10 to convert to a range of 100 μs. The result, 150, is written into the interval INT location in the timing chain header. Considering the example chain shown in Figure 6, the first process in the chain takes time 1270
This is written in the WAKE UP location in the header. The dump stack of the first process in the chain has a value of zero written into the increment location INC. The second process in the chain requests to be processed at time 1270 plus 20 (or time 1290), while process 3 is processed after another increment of 10 (or time 1300). The increment value INC for the first operation in the chain is always zero, and the value in the header NEGSUM is the signed 22 which is the negative sum of the increments in the chain.
It is maintained as a bit value. NEGSUM
is calculated by making the sum of the increments negative and subtracting one. So in the example,
NEGSUM increments 20 and 10 to -31
become. This is important when adding treatments to the end of a chain, as it allows you to determine the INC value for a new treatment without crossing the complete chain.

FIG. 7 shows that process dump stacks for processes are concatenated for processes that have been suspended for a specific period of time (i.e., 15 milliseconds).
In multiprocessor systems that handle real-time processing, such as those found in the telecommunications field, there are processes that are interrupted at different intervals. Such a situation is handled by having several timing chains, each having a timing chain header.

The header is a downlink of the header shown in Figure 7.
They are connected using WDLINK as shown in Figure 8. The beginning of the header chain is a pointer FIRST to the beginning of the timing chain header list.
A timing chain master pointer block with a HEADER. Timing chain headers are not arranged in any particular order. When an individual timing chain becomes free (i.e.,
When there is no more processing), the header is said to be "free" and can be used again for a different interval if required. Timing chain master pointer block pointer
FREE is used to hold a pointer to a free header, and if there is no free header,
The pointer is set to NULL.

The above timing chain plan has three main operations in management.

1 Processing suspends execution (i.e., until a specified time interval elapses or until some external event (i.e., a flag) occurs, whichever occurs first)
WAITFOR time interval instruction). The processing must therefore be linked to an appropriate timing chain.

2 Processes in a timing chain are removed from that chain by the occurrence of an external event.

3. A process in a timing chain is removed from the chain by the expiration of its time interval.

The first operation is shown in flowchart form in FIG. 9, where a special process called the "Assharette" process searches for the timing chain header that handles the third operation, which is the tenth. As shown in the figure. The second operation is handled using some of the steps in FIG.

First, let's consider the operations necessary to interrupt processing, in other words, to place processing on the timing chain.

Interrupting Processing As mentioned above, FIG. 9 shows a flowchart of the operations that are performed when a wait period macro instruction is encountered. The processor unit encountering the instruction stores in one of its function registers a descriptor for the master pointer block (Figure 8) (i.e., the base value and limit value with the access type code).
Set. Then the processor unit
Execute the PS1 step and it will register SDIREG
Use MILL to form the actual required memory address in the master pointer block and address the memory module present on the block and leads SIH in Figures 1a and 1b. Address the FREE location of.
The content of the addressed location is the lead line.
On the SDH, it is returned in, for example, one of the general purpose registers in the ACC STK. Then the processor
Execute the PS2 step of FIG. 9, in which the contents of that register are tested by MILL using the arithmetic unit condition signal AVIS.

All processing operational steps in Figures 9 and 10 are as follows: 1a using conventional data processing operations.
The details of the remaining operational steps will therefore not be attempted herein, as they are obvious to those skilled in the art to be able to perform using the apparatus of FIGS. and FIG. 1b.

PS3 Step In this step, free timing headers are included because the master pointer block is not identified by a FREE location; in this step, the list of timing chain headers is filled in so that each header is free. Each timing chain header is scanned using the downlink WDLINK (Figure 8) to test each head. Once a header is found, pointer FREE in the master pointer block is conditioned to point to that header. If no such free header is found, a new storage block is obtained from the pool managed by the storage management process;
This new block is initialized as a timing chain header, and it is added to the end of the timing chain header list.

PS4 Step This step consists of setting the value X to a general purpose register in the processor unit.
This value X is calculated by adding the wait time interval () to the current system time. This value X is also later used to condition the WAKE UP value or the incremental value of the process.

PS5 step In this step, the timing chain header list (Figure 8) shows the required waiting period ().
is scanned to find a header with an interval time (INT Figure 7) equal to . If a timing chain with a waiting period exists, then the PS6 step completes the y pass; if the timing chain does not already exist, it becomes an n pass.

PS7 step In this step, the increment (INC) for the process dump stack is increased from the value X formed in the PS4 step to the WAKEUP -
It is formed by subtracting the value formed from NEGSUM-1. This step also updates the NEGSUM in the selected timing chain header by subtracting the newly formed increment for the new process.

PS8 Step Upon completion of the PS7 step, it is necessary to insert the process into the selected timing chain, which is done by inserting the LEFT LINK NL in the header.
By reading the LINK slot, the last operation in the chain is identified and executed. Note that if the chain is empty, the "last processed" is the header itself. Once the last process in the list is identified, the link between this last process and the header is broken and re-formed by introducing the new process as the last process in the chain. The value X is also used in this step to ensure that the asset processing is woken up at or before time X.
Upon completion of this operation, the interrupt process is completed and the processor unit executing the interrupt process enters the process scheduler.

PS9 Step If there is no timing chain with an interval equal to the waiting period of the newly suspended process, the PS6 step finishes on n passes.
Steps PS9, 10, and 11 are executed in this case, using the new timing chain header as well as removing that header from the FREE pointer in the master pointer block (Figure 8), WAKE UP,
Set INT and NEGSUM (Figure 9).

From the above, it can be seen that to suspend a process for a defined period of time, a process dump stack is added to the end of a chain of process dump stacks that are all waiting for the same interval during that defined period. The timing chain is managed by timing chain header WAKEUP, RIGHT LINK,
This is achieved by the values of LEFT LINK and NEGSUM.

When a process is interrupted by a wait period macro, (a) the process will continue until the required interval ends;
(b) The process is placed on the timing chain until removed by the occurrence of some external event. These operations are accomplished by the flowchart of FIG. 10, the so-called USHERETTE process, and are described in the order defined above.

Assyret Processing This process is performed when or before the shortest timing chain wakeup value is completed.
This is done under the control of the interval timer device of the processor unit that is conditioned to terminate and enters the assharette process. The method of identifying the shortest value is defined in the following process. Essentially, the asset processing is used as a timing check process to ascertain which processes have completed their waiting period.

UP1 Step In this process, a general purpose register in the processor performing the asset operation is used to store the value TIME for the process, and this register is set to the current system time.

UP2 step The second general-purpose register in the processor has a value
Used to store NEXT TIME, the contents of that register for this step are set to a large value, ie, all ones.

UP3 step The processor checks the first header in the chain. This is the FIRST HEADER pointer (8th
(Fig.) is achieved using. The operation performed in this step is based on the timing chain list pointer (TCL), which is one of the general-purpose registers of the processor.
Insert the FIRST HEADER reading into the POINTER).

UP4 step In this step, TCL POINTER
is used to read the WAKE UP value of the first timing chain header in the chain (see Figure 7).

UP5 step Processor unit has just loaded
Compare the WAKE UP value with the value TIME. Typically,
One of the two values held in separate registers in the processor is subtracted from the other by MILL and the result is monitored. If WAKE UP
>TIME, for the first header
Since the WAKE UP time is greater than the current system time, steps such as UP6 are executed to step to the next header in the chain. The result of the step comparison is that TIME is WAKE UP.
, then the UP11 step etc. is executed to pull the first process onto the first timing chain and place it on the "Ready to Run List". be done. WAKE UP of first header is TIME
It is assumed at this stage that .

UP6 step In this step, WAKE UP is NEXT
compared to TIME, if WAKE UP is NEXT
If it is less than TIME, the UP7 step is executed. In this state, the assumed
NEXT TIME is set to an elbow-high value in the UP2 step, so the UP7 step is executed.

UP7 step In this step, NEXT TIME is
Overwritten by the WAKE UP value read from the header addressed in the UP4 step.
This action controls the search "down" until the NEXT TIME encountered is equal to the current system time given by TIME, and the timing chain header sets NEXT TIME to the lowest value encountered.

UP8 Step The downlink WDLINK (FIGS. 7 and 8) addressed in the UP4 step is loaded into one of the processor's general purpose registers in this step.

UP9 Step This step tests the downlink to see if it is NULL indicating the end of the chain. It is assumed that the downlink is not NULL. However, it must also be pointed out that such a situation occurs because you are putting processing on a timing chain that is waiting for a timeout or an external event, and if the external event occurs before the timeout. The process is removed from the chain, so the asset process is WAKE UP to respond to its timeout. The operations required to remove processing from the timing chain are related to steps UP11 through UP18 and will be explained later.

UP10 Step In this step the downlink WDLINK read in the UP8 step is written to a general purpose register used as the timing chain list pointer TCL POINTER and then UP4 and again using the WAKE UP value from the next header in the chain.
Execute UP5 step. Steps UP6 through UP10 are executed repeatedly until a header with a WAKE UP value equal to TIME is found or a complete header chain is traversed. WAKE UP
If a condition equal to the TIME of the UP5 step is found, the UP11 step is executed and the WAKE UP
When the period ends, a chain of steps is activated that removes the interrupted process from the timing chain.

UP11 Step In this step, write link R of the timing chain header in TIMING LIST with WAKE UP value equal to the current system time.
LINK (Figure 7) is loaded into one of the processor's general purpose registers. This operation identifies the first processing dump stack on the timing chain provided by the header.

UP12 Step In this step, the write link read in the UP11 step is tested to see if the chain is free. If the timing chain has a dump stack waiting for a timeout or an external event to occur, then such a condition will occur again, and when the latter occurs, the WAKE for the particular timing chain
Remove the process from the timing chain before UP finishes. Assume that the timing chain that "entered" the UP5 and UP11 steps has a processing dump stack waiting to be processed at this point.

UP13 Step In this step, the general purpose register designated as X in the flowchart of FIG. 10 is used to read the increment value on the adjacent side of the timing chain.

UP14 step In this step, the current first process is put into a state ready to execute the list, so
Increment value (INC) on the right side of the timing chain so that this process is the first process in the chain.
is set to zero.

UP15 Step In this step, the X value is used to adjust the WAKE UP and NEGSUM values in the timing chain header to adjust for the removal of reactivated processes.

UP16 Step In this step, the right link (IR LINK) and left link (NL LINK) in the timing chain header are rewritten to point out what process 2 in the chain is, as configured earlier. It is formed.

The UP17 step causes the processor unit to place processes identified in steps UP5 through UP12 that are ready to be woken up on the scheduler's "ready-to-run" list.

The associated processes search for other processes to be woken up at the current system time given by TIME: UP8, UP9, UP10, UP4
and execute the UP5 step. eventually,
UP9 step is encountered at the end of Hezdachien,
UP19 step is executed.

UP19 Step This step sets the NEXT TIME value, which is the lowest WAKE UP value encountered while querying a header that is not equal to the current system time.
The final value of is written to the HARDWARE TIMER system, at which point the asset processing is activated again. Assharret processing is suspended waiting for the current system time and using an interval timer device on one of the processors to
The TIAER value is reached.

To remove processing from the timing chain, UP11, UP12, UP13, UP14, UP15, UP16
It is only necessary to perform the and UP17 steps. Point .alpha. in FIG. 10 indicates the point at which an assylet process is entered that is "forced" by the occurrence of a specific external event.

The timing chain mechanism described above has several advantages over other conventional mechanisms. Representative of these advantages are as follows.

1 Adding new processes to a chain is always done last, making it easier to operate due to the chain and NEGSUM values. Complete chain traversal is not necessary and operation is efficient no matter how long the chain is.

2 Removing the process from any part of the chain is an easy and efficient operation without the need to cross the chain.

3. Being a real-time system, only one value (WAKE UP) needs to be adjusted at each header, even if the absolute time value must be adjusted from time to time to avoid overflow. Time values within individual process dump stacks are relative and do not need to be adjusted.

4. When an individual chain becomes free (i.e. when there is no other processing on the chain), the header is said to be "free" and can be used again for another INTERVAL, so
Setting the INTERVAL value can be easily done to suit the needs of the moment.

[Brief explanation of the drawing]

1a and 1b, placed side by side with FIG. 1a on the left, are block diagrams of a central processing unit suitable for use in one embodiment of the present invention; FIG. is a diagram showing the registers in the CPU of FIGS. 1a and 1b, and FIG. 3 is a diagram showing the registers in the CPU of FIGS. 1a and 1b.
Figure 4 shows the memory protection (function) register in the CPU. Figure 4 shows the processing dump stack. Figure 5 shows the processing base. Figure 6 shows the running list of the scheduler. Figure 7 is
FIG. 8 is a diagram illustrating how the timing chain headers are linked; FIG. 9 is a flowchart of a process interruption algorithm; and FIG.
FIG. 2 is a flowchart of a so-called "assyret" process. ACC STK……General purpose stack, BASE STK…
...Base stack, RES REG...RES register, MILL...arithmetic unit, COMP...comparator, IR...instruction register, OP REG...arithmetic register, SDIREG...memory communication register, μPROG...microprogramming control type central Processing unit, TC/LMT
STK...TC/LMT stack.

Claims (1)

[Scope of Claims] 1. A real-time digital data processing apparatus for handling a plurality of processes, each having a "waiting period" instruction specifying one of a plurality of predetermined periods, the apparatus comprising: a memory for storing information regarding the processing, and at least one processor unit adapted to execute the processing, each processing retaining working parameters for the processing at the time the processing was interrupted. In order to do this, an information segment is provided in memory, the information segment (DA) having an indication (INC) of the time at which the waiting period for the process should be completed, and the information segment link information ( RIGHT
LINK; LEFT LINK) forms the information segments of all processes interrupted by certain instructions with the same duration into a first linked list in which the information is arranged in the order of the times in which they are interrupted; 1st
The linked list is also linked to a timing chain header segment stored in memory (TIMING CHAIN HEADER・Hetzder・
Segment (TIMING CHAIN HEADER X)
is a wake flag indicating when the waiting period for the first information segment (PROCESS DUMP STACK 1) on the first linked list is completed.
Accumulates the wake up value (WAKE UP) and uses it for each timing chain header segment (TIMING
CHAIN HEADER a timing chain search process for searching the second list;
The data processing device also monitors a time interval, and upon completion of the interval, the timing
The data processing apparatus characterized in that it comprises means for activating an interval timing device (ITR) conditioned to activate a chain search process. 2. In the data processing device according to claim 1, each information segment (DA) has a first link pointer (LEFT LINK) and a second link pointer (RIGHT LINK), A first link pointer (LEFT LINK) connects the information segment to the immediately preceding information segment in the first list, while a second link pointer (RIGHT LINK) connects the information segment to the immediately previous information segment in the first list. said data processing device connected to an information segment that immediately follows. 3. In the data processing device according to claim 1 or 2, each information segment (DA)
is the difference between (i) when the waiting period completes for a process with the information segment that immediately precedes the information segment, and (ii) when the waiting period completes for the process with the information process. Said data processing device having an incremental value (INC) defining a period in the form of . 4. In the data processing device according to any one of claims 1 to 3, each timing chain header segment (TIMING
CHAIN HEADER X) has a first chain link pointer (IRLINK) and a second chain link pointer (NLLINK), and the first chain link pointer The second chain link pointer points to the information segment (PROCESS DUMP STACK 3) at the beginning of the linked list, while the second chain link pointer points to the information segment (PROCESS DUMP STACK 3) at the end of the first linked list. ). 5. In the data processing device according to claim 4, each timing chain header segment (TIMING CHAIN HEADER X)
The data processing device has an additive value (NEGSUM) for the sum of incremental values of all information segments in the first list linked to the chain header segment (TIMING CHAIN HEADER X). 6. In the data processing device according to any one of claims 1 to 5, the data processing device includes a timing chain pointer block (MASTER POINTER block) related to the timing chain search process. BLOCK)
and the pointer block has a first header pointer (ERWC/RWD) pointing to a first timing chain header segment (XTVHEAD) in the second list. Processing equipment. 7. In the data processing device according to any one of claims 1 to 6, the processing device: (a) reads a wake-up value in each timing chain header segment; (b) the above. Compare the read value of the wake-up value with the time during which the timing chain search process is being executed, c) transfer the same process as the one whose waiting period has been completed to the running list of the device process scheduler, and d) assign it to the process. each first
adjusting the first linked list by moving the information segment from the linked list of each or reshaping the respective first linked list; and e) the timing chain search process is performed. The data processing device performs the timing chain search process, the data processing device comprising the step of calculating the time during which the timing chain search is performed. 8. In the data processing device according to claim 7, the processing device, in step d),
canceling the first and second link pointers of the information segment and adjusting the second link pointer of the information segment following each adjusted first link list pointing to the timing chain header segment; The data processing apparatus having an operation for adjusting a timing chain header segment of each adjusted first linked list pointing to the next succeeding information segment. 9. A data processing device according to claim 7 or 8, wherein in step d), the processing device performs the processing according to the increment value of the next succeeding information segment. 1 link list each timing chain header
The data processing device has an operation for adjusting a wake up value of a segment. 10. The data processing device according to any one of claims 1 to 9, wherein the information segment is a dump stack for the specific process. 11. In the data processing device according to any one of claims 7 to 10, each processor unit is set to a predetermined real-time value, and when the predetermined real-time value occurs, . The data processing apparatus comprising an interval timing device in which the timing chain search process is executed on the processor unit. 12. The data processing apparatus according to claim 7, wherein in step e), the processing apparatus sets the interval timing device of the processor unit to a time value according to the time at which the timing chain search process is executed. The data processing device has an operation for conditioning the timing chain search process to be performed at.