JPS6236270B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a processor monitoring system in a multiprocessor system.

Conventionally, in a multiprocessor system in which a plurality of processors are connected via a common bus, there has been no effective means for monitoring each processor at once.

An object of the present invention is to provide an effective means for collectively monitoring processors in a multiprocessor system.

The present invention includes a counting circuit corresponding to each processor in a control section of a common bus connecting each processor, a means for updating this counting circuit every predetermined period, and a common bus connecting from a processor corresponding to this counting circuit. and a means for clearing the contents of this counting circuit when activated, and detecting an abnormal state of the processor corresponding to this counting circuit when the contents of this counting circuit exceed a certain value. This is a processor monitoring method in a multiprocessor system.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of a multiprocessor according to an embodiment of the present invention. In FIG. 1, processor 20
1 to 20n are connected to each other via a common bus 10, and the common bus 10 is controlled by a bus control unit 100. As long as the processors 201 to 20n are operating normally, the processors 201 to 20n request the bus control unit 100 to start the bus at least once via the common bus 10 at least once within a predetermined period of time.
Transfers information to other processors. In this case, if any of the processors 201 to 20n is in an abnormal state, no bus activation request is issued from the processor in the abnormal state. Therefore, in the bus control unit 100, these processors 201 to
By monitoring the status of bus activation requests of 20n, it is possible to detect abnormal states of these processors.

FIG. 2 is a circuit diagram of the main parts of the bus control section according to the embodiment of the present invention. In FIG. 2, 1 is a startup request detection circuit that detects a bus startup request from each processor, and 2 is an expansion circuit that expands the number of the processor that has received a bus startup request detected by the startup request detection circuit 1 into correspondence with each processor. , 31-3n are counting circuits provided corresponding to each processor, 21-2n
are the output signal lines of the counting circuits 31 to 3n, 41 to 4n
is an AND gate circuit, 51 to 5n are inverters,
5 is a clock pulse generation circuit. Further, 10 is a common bus, and each processor is connected to this common bus 10. . If all processors are in a normal state, all the signals output to the counting output terminal OV of the counting circuit are at “0” level, and the output signal line 2
A "0" level signal is output to 1 to 2n.
Further, the logic of the signals output to the output terminals of the inverters 51-5n is inverted with respect to the signals on the output signal lines 21-2n, and becomes the "1" level, and the AND gate circuits 41-4n are opened. Therefore, the clock pulses output from the clock pulse generating circuit 5 at a predetermined period are outputted from the AND gate circuits 41 to 4.
The contents of the counter circuits 31-3n are updated each time the clock pulse is input. The signals output to the output terminals OV of the counting circuits 31 to 3n become "1" level when the number of clock pulse inputs exceeds a predetermined number, and the contents of the counting circuits 31 to 3n become this predetermined value. These counting circuits 31 to 3n before
There is a bus activation request from the processor corresponding to the processor, the activation request detection circuit 1 detects the bus activation request, and the counting circuit 2 outputs the count corresponding to the processor from which the bus activation request has been made among the counting circuits 31 to 3n. When a clear signal is input to the clear terminal CL of the circuit, the contents of this counting circuit are cleared, so
The signal output to the counting output terminal OV maintains the "0" level state. If a certain processor is in an abnormal state, a startup request to the common bus 10 will not be issued from that processor, so that the clear terminal CL of the counting circuit corresponding to the processor in the abnormal state among the counting circuits 31 to 3n is Since the clear signal is no longer input to the counter, more than a predetermined number of clock pulses are input to the counting circuit.
The signal output to the output terminal OV of the counting circuit changes from the "0" level to the "1" level, and a "1" level signal is output to the output signal line corresponding to that counting circuit among the output signal lines 21 to 2n. do. At the same time, due to the "1" level signal output to the output terminal OV, a "0" level signal is input to the input terminal of the AND gate circuit corresponding to the counting circuit among the AND gate circuits 41 to 4n, and the AND gate circuit is closed, the input of clock pulses to that counting circuit is stopped, and the output terminal of that counting circuit is closed.
The signal output to OV continues to be in the bell state of "1". Therefore, by monitoring the levels of the signals on the output signal lines 21-2n, it is possible to detect a processor in an abnormal state.

As explained above, the present invention facilitates monitoring of the status of each processor in a multiprocessor system in which a plurality of processors are interconnected via a common bus controlled by a bus controller, and This has the effect of making it possible to easily detect abnormal conditions.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a multiprocessor according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of the main part of a bus control section according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Start request detection circuit, 2...Development circuit, 5...Clock pulse generation circuit, 10...Common bus, 21-
2n...Output signal line, 31-3n...Counting circuit, 41
~4n...AND gate circuit, 51~5n...Inverter, 100...Bus control unit, 201~20n...Processor.

Claims (1)

[Claims] 1 In a processor monitoring system in which multiple processors are connected to a common bus with a bus control circuit and transmit and receive information between them, a processor is installed corresponding to each of the multiple processors and a clear signal is input and a clear signal is input within a predetermined time. The control circuit includes a time counting circuit that outputs a predetermined signal to the output terminal when the next clear signal is not input, and means for inputting the clear signal to the corresponding time counting circuit each time the processor activates the common bus. A method for monitoring a processor, characterized in that an abnormal state of the processor is detected by an output signal of a time counting circuit when the processor starts a common bus and does not start again within a predetermined time.