JPS6236307B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory, and more particularly to a memory circuit using an insulated gate transistor.

For convenience of explanation, we will discuss N-channel MOS static type memory below, but the same is essentially true for P-channel. in general
MOS memory is configured as shown in Figure 1. Signal lines word lines WL ₁ to WL _N related to X decoder 2, Y
The signal lines to the decoder and sense amplifier 4 are the digit lines _D1 to _Dn , and the output lines are the lead bus line BL.
It is called.

The connection with the conventional digit line lead bus line will be described with reference to FIG. In this circuit, the X decoder 2 first selects one word line, for example, word line _WL1 . Memory cells C ₁₁ and C ₁₂ connected to the selected word line WL ₁ start operating,
All digit lines D ₁ , ₁ , D ₂ , _{2 .} . . are directed to potentials corresponding to the contents of the memory cells. The sense amplifiers SA ₁ and SA ₂ are selectively operated by the Y decoder 4', and the memory cell at the intersection of the selected word line and the digit line is selected and becomes the memory cell to be read. However, the problem here is the influence of the unselected digit line on the read bus line RB. In the sense amplifiers SA ₁ and SA ₂ , the digit lines Di,
and read bus line RB, through weight capacitances C ₁ , C ₂ , C ₃ , C ₄ of the gates and drains (or leases) of the first transistors Q ₁ , Q ₂ , Q ₃ , Q ₄ inserted between Then, the signal on the digit line Di is transmitted to the read bus line RB, resulting in malfunction or speed delay.

An object of the present invention is to provide a memory circuit that is free from malfunctions and is capable of high-speed operation.

The memory circuit according to the present invention is characterized in that insulated gate FETs serving as a plurality of select gates provided between a plurality of digit line read bus lines are operated in an unsaturated region.

According to the present invention, in a memory circuit using MOS transistors, a sense amplifier is inserted between the digit line and the read bus line to transmit information on the digit line to the read bus line. , a transistor is inserted, the transistor connected to the selected digit line is turned ON, the transistor connected to the unselected digit line is turned OFF, and the change in the information on the unselected digit line becomes the sense of the unselected digit line. A memory circuit is obtained in which the data is not transmitted to the read bus line via the amplifier.

In addition, all the transistors mentioned above are kept in the ON state when the memory is not operating or not being read, and all the above transistors connected to the non-selected digit line are turned OFF when receiving the address decoder signal when the memory is operating or being read. The transistor connected to the digit line receives the address decoder signal and performs capacitive feedback to increase the degree of ON, thereby providing a memory circuit which is capable of increasing speed.

Next, a first embodiment of the present invention will be described with reference to FIG.

The description will be made assuming that the memory cell C is of a state type with a flip-flop configuration. Digit lines D, are connected to a pair of input and output points of memory C, and are inputted via transistors _Q4 and _Q5 , respectively, to a differential sense amplifier SA constituted by transistors _Q1 to _Q3 . Here, this is done by connecting to the gates of transistors Q ₁ and Q ₂ . The drains of transistors Q ₁ and Q ₂ are connected to read birth lines RB, respectively. The output of the Y decoder 4' is commonly supplied to the gates of the enable transistor Q ₃ and the transistors Q ₄ and Q ₅ of the sense amplifier. In such a configuration, transistors _Q4 and _Q5 are conductive only when digit line D is selected, and are non-conductive when not selected. This prevents the level of the unselected digit line from being transmitted to the read bus line RB via the sense amplifier. Note that the transistors Q ₄ and Q ₅ are rendered conductive when the memory is not read, that is, when the memory is reset, so that the flash discharge is performed uniformly.

Next, a second embodiment of the present invention will be described with reference to FIG.

In this embodiment, the output of the Y decoder 4' is supplied to the gates of the transistors _Q4 and _Q5 via the boost scrub circuit _B1 .
Therefore, since transistors _Q4 and _Q5 operate in a non-saturation region, the level of the digit line can be transmitted to the sense amplifier SA without causing any level loss. boost thrust circuit
_B1 includes an inverter N that receives input from the decoder output _Y1 , a capacitor _C1 whose one end is connected to _Y1 , and an inverter circuit including transistors _Q6 and _Q7 . When the memory is not read, the clock _φ1
The transistor Q ₆ is made conductive, and the node A is set at a potential such that the transistors Q ₄ and Q ₅ are almost made conductive. When reading the memory, transistor _Q6 is turned off, and the selected digit line is connected to Y decoder 4'.
Since the outputs Y ₁ and Y ₁ ' of the transistors go to high level, the potential of the node A further increases, and the conduction of the transistors Q ₄ and Q ₅ is increased.

In this embodiment, since the conductivity of transistors Q ₄ and Q ₅ is high, there is an advantage that the level of the digit line is completely transmitted to the sense amplifier SA.

The present invention, which has been described above with reference to embodiments, is not limited to the above-described embodiments, but can be similarly applied to cases where, for example, a dynamic type memory cell or a sense amplifier having a flip-flop configuration is used.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a conventional memory. Second
The figure is a circuit diagram showing a conventional MOS memory. FIGS. 3 and 4 are block diagrams showing embodiments of the present invention, respectively. 1...X address buffer, 2...X decoder, 3...Y address buffer, 4,4'...Y
Decoder, SA... sense amplifier.

Claims (1)

[Claims] 1. A transistor is inserted between the digit line and a sense amplifier inserted between the digit line and the read bus line to transmit information on the digit line to the read bus line, A memory circuit characterized in that the transistor connected to a digit line is made conductive, and the transistor connected to an unselected digit line is made non-conductive. 2 All of the above transistors are made conductive when the memory is not being read, and all of the above transistors connected to the unselected digit line upon receiving the address decoder signal are made non-conductive when the memory is read, and all of the above transistors connected to the selected digit line are made non-conductive. 2. The memory circuit according to claim 1, wherein a signal from an address decoder is supplied to the gate of said transistor through bootstrap means.