JPH0330237B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory, and more particularly to a memory circuit using an insulated gate transistor.

For convenience of explanation, we will discuss an N-channel MOS static type memory below, but the same is essentially true for a P-channel. in general
MOS memory is configured as shown in Figure 1. The signal line related to X decoder 2 is connected to the word line WL ₁ ~
The signal lines to WL _N , Y decoder and sense amplifier 4 are called digit lines D ₁ -D _n , and their output lines are called read bus lines BL.

A conventional connection between a digit line and a read bus line will be described with reference to FIG. In this circuit, first
Decoder 2 selects one word line, for example word line _WL1 . selected word line
Memory cells C ₁₁ and C ₁₂ connected to WL ₁ start operating, and all digit lines D ₁ , ₁ , D ₂ , ₂ . . .
to a potential corresponding to the contents of the memory cell.
Sense amplifiers SA ₁ and SA ₂ by Y decoder 4'
is selected, a pair of digit lines is selected, and the memory cell at the intersection of the word line and the digit line is selected and becomes the memory cell to be read.The problem here is that the unselected digit line This is the effect that the line has on the read bus line RB. Weight of the gate and drain (or lease) of the first transistors _{Q 1 ,} Q ₂ , Q ₃ , Q ₄ inserted between the digit lines D _i , _i and the read bus line RB in the sense amplifiers SA 1 , SA ₂ Capacity C ₁ , C ₂ ,
The signals on the digit lines D _i , _i are transmitted to the read bus line RB via C ₃ , C ₄ , resulting in malfunctions or speed delays.

An object of the present invention is to provide a memory circuit that is free from malfunctions and is capable of high-speed operation.

The memory circuit according to the present invention is characterized in that insulated gate FETs serving as a plurality of select gates provided between a plurality of digit lines and a read bus line are operated in an unsaturated region.

According to the present invention, in a memory circuit using MOS transistors, a transistor is inserted between the digit line and the read bus line in order to transmit information on the digit line to the read bus line, and connected to the selected digit line. The transistor connected to the unselected digit line is turned OFF, and the transistor connected to the selected digit line receives the address decoder signal and applies capacitive feedback to turn ON the transistor. It is characterized by increasing speed and increasing speed.

Next, a reference example of the present invention will be described with reference to FIG.

The description will be made assuming that the memory cell C is of a static type with a flip-flop configuration. Digit lines D, are connected to a pair of input and output points of memory C, respectively, and are inputted via transistors _Q4 and _Q5 to a differential sense amplifier SA constituted by transistors _Q1 to _Q3 . Here, this is done by connecting to the gates of transistors Q ₁ and Q ₂ . The drains of transistors Q ₁ and Q ₂ are connected to read bus lines RB and Q 2, respectively.
connected to. The output of the Y decoder 4' is commonly supplied to the gates of the enable transistor Q ₃ and the transistors Q ₄ and Q ₅ of the sense amplifier. In such a configuration, transistors _Q4 and _Q5 are conductive only when digit line D, is selected;
When not selected, it becomes non-conductive. This prevents the level of the unselected digit line from being transmitted to the read bus line BB via the sense amplifier. Note that the transistors Q ₄ and Q ₅ are rendered conductive when the memory is not read, that is, when the memory is reset, so that the precharging is performed uniformly.

Next, an embodiment of the present invention will be described with reference to FIG.

In this embodiment, the output of the Y decoder ₄ ' is supplied to the gates of the transistors Q4 and _Q5 via the bootstrap circuit _B1 .
Therefore, since transistors _Q4 and _Q5 operate in a non-saturation region, the level of the digit line can be transmitted to the sense amplifier SA without causing any level loss. bootstrap circuit
_B1 includes an inverter N that receives input from the decoder output _Y1 , a capacitor _C1 whose one end is connected to _Y1 , and an inverter circuit including transistors _Q6 and _Q7 . When the memory is not read, the clock _φ1
The transistor Q ₆ is made conductive, and the contact A is set at a potential such that the transistors Q ₄ and Q ₅ are almost made conductive. Turn off transistor _Q6 when reading memory
Then, the outputs Y ₁ and Y ₁ ' of the Y decoder 4' for the selected digit line go to high level, so the potential at node A further increases, and the transistors Q ₄ and Q ₅
Improves conductivity.

This embodiment has the advantage that the level of the digit line is completely transmitted to the sense amplifier SA because the conductivity of the transistors Q ₄ and Q ₅ is high.

Although the present invention has been described above with reference to embodiments, the present invention is not limited to the above-described embodiments, but can be similarly applied to cases where, for example, a dynamic type memory cell or a sense amplifier having a flip-flop configuration is used. .

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a conventional memory. Second
The figure is a circuit diagram showing a conventional MOS memory. FIG. 3 is a diagram showing a reference example of the present invention. FIG. 4 is a configuration diagram showing an embodiment of the present invention. 1...X address buffer, 2...X decoder, 3...Y address buffer, 4,4'...Y
Decoder, SA... sense amplifier.

Claims (1)

[Claims] 1. Insulated gate field effect transistors as a plurality of select gates provided between a plurality of digit lines and a read bus line, a decoder circuit for selecting the insulated gate field effect transistors, and a decoder circuit of the decoder circuit. means for boosting the output to a power supply potential or higher by a bootstrap means and supplying it to the gate of the insulated gate field effect transistor, so as to operate the selected insulated gate field effect transistor in a non-saturation region. A memory circuit characterized by: