JPS6236315B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a level shift circuit, particularly a level shift circuit suitable for an input bias circuit of a charge-coupled device that handles analog signals.

In order to obtain linearity between the input signal and the amount of injected charge (or output signal) in a charge-coupled device (hereinafter referred to as CCD), the input signal is superimposed on an appropriate DC bias voltage to increase the charge. It is necessary to lead to the input diffusion layer or input gate electrode of the injection part. Therefore, an input bias circuit has become an essential component in CCDs that handle analog signals.

Conventionally, capacitive coupling has been used exclusively as this input bias circuit. This changes the signal voltage to
The method was to connect the CCD to the input terminal (input diffusion layer or input gate electrode) through a capacitor, and to bias the input terminal through a resistor to a suitable operating point where linear operation could be achieved. Since this capacitive coupling has a cutoff frequency in the low range, it is necessary to use a large capacitor and high resistance to prevent deterioration of the low range characteristics. The capacitance value usually used is several μF to several tens of μF, and the resistance value is several KΩ to several hundred KΩ. As peripheral circuits become more integrated into ICs, such as on-chip clock drivers, input bias circuits naturally have compatibility with MOS-structured CCDs in terms of manufacturing processes, making it possible to integrate them on the same semiconductor substrate. are required. However, it is impossible to form such a large capacitance and high resistance as described above on a semiconductor substrate, and with conventional capacitive coupling, an input bias circuit cannot be provided on the same substrate as a CCD.

As a novel input bias circuit that improves the above-mentioned defects, the present applicant and the same applicant filed a patent application
In No. 116476, we proposed a level shift circuit and its driving method, an example of which is shown in Figure 1. That is,
In Figure 1, 3 is an operational amplifier, 1 and 2 are capacitors with capacitance values of C ₁ and C ₂ , respectively;
5 and 6 are switches, 7 is a signal source, and 8 is a constant voltage generating circuit. In the figure, for convenience of explanation, switches 4, 5, and 6 are shown as N-channel MOS transistors (hereinafter referred to as MOST) as specific examples.
Indicated by S ₁ , S ₂ , and S ₃ . These MOSTs are synchronous type switches that periodically repeat opening and closing (OFF to ON) by control pulse voltages applied to terminals 9 and 10. FIG. 2 is a timing diagram for explaining an example of a driving method of the level shift circuit shown in FIG. 1 and the operation thereof. In the same figure, 19 and 20 are the terminals and 10 of FIG.
indicates the control pulse voltage applied to, in this example
Since MOST is an N-channel type, the period when pulse voltages 9 and 10 are at the high level V _H is the period during which switches 4, 5, and 6 are closed, and the low level side V
The period when the signal becomes _L is the period during which switches 4, 5, and 6 are open. Therefore, the opening/closing state diagrams of the switches 4, 5, and 6 are as shown in 14, 15, and 16. However, in 14, 15, and 16, the solid line section corresponds to the switch close (ON) period, and the broken line section corresponds to the switch open (OFF) period.
In FIG. 2, 21 is the input signal voltage supplied from the signal source 7, 22 is the voltage between the terminals of the capacitor 1, that is, the voltage at the terminal 11, and 23 is the level shift circuit obtained at the output terminal 13 of the operational amplifier. is the output voltage of However, for the output voltage 23, periods corresponding to the rise time and settling time of the operational amplifier 3 are omitted for simplicity. This will be explained below using FIGS. 1 and 2. First, at time a in FIG. 2, the switch 5 is closed, so the terminal voltage 22 of the capacitor 1 is now:
It changes in the same way as the input signal voltage 21. Further, since the switch 4 is also closed, the operational amplifier 3 is connected as a unity feedback, and the output terminal 13 is set at the same potential as the non-inverting input terminal 18, that is, the voltage value V _A of the constant voltage generating circuit 8. At this time, capacitor 2 has no accumulated charge. At time b, when the stitch 5 is opened and the signal source 7 is disconnected, the terminal voltage 22 of the capacitor 1 is thereafter held at the input signal voltage Vs ₁ at this time b. At time b, switch 4 is also opened, but since there is still no accumulated charge in capacitor 2, the output voltage 23 at output terminal 13 is V _A
It remains as it is. Next, when the switch 6 closes at time c, the terminal 11 of the capacitor 1 is connected to the inverting input terminal 12 of the operational amplifier 3.
exhibits its characteristic large differential amplification effect, and the negative feedback loop via the capacitor 2 reduces the potential difference between the inverting input terminal 12 and the non-inverting input terminal 18 to almost zero. As a result, the terminal voltage 22 of the capacitor 1 becomes V _A , and the amount of charge C ₁ (Vs ₁ −V _A ) moves from the capacitor 1 to the capacitor 2. Considering that the total amount of charge remains unchanged before and after movement, assuming that the voltage value of the output terminal 13 at this time is Vo ₁ , C ₁ (Vs ₁ - V _A ) = C ₂ (V _A - Vo ₁ ). The relational expression is established, and the output voltage Vo ₁ becomes Vo ₁ =−(C ₁ /C ₂ )Vs ₁ +{1+(C ₁ /C ₂ )} _VA . At time d, switch 6 opens,
Since there is no change in the charges stored in capacitors 1 and 2, the values of terminal voltage 22 and output voltage 23 of capacitor 1 remain at V _A and Vo ₁ . The period from time a to e described above is one cycle of the operation of this circuit, and the same operation is repeated from e onwards, and the input signal voltage values Vs ₂ and Vs ₃ at each moment when the switch 5 is opened are
, output voltage values Vo ₂ and Vo ₃ are obtained sequentially. As explained above, in the level shift circuit shown in FIG. 1, the capacitor 1 is first charged by the signal source 7 by closing the switch 5, and then the sample value Vs of the input signal is changed to C ₁ ·Vs by opening the switch 5.
It is stored and held in the capacitor 1 as a charge. Next, switch 6 is closed, and using the high amplification and negative feedback effect of the operational amplifier to which DC voltage V _A is applied to non-inverting input terminal 18, capacitor 1 to C _{1 is}
By transferring the charge amount (Vs-V _A ) to the capacitor 2, a signal voltage - (C ₁ /C ₂ )Vs superimposed on the DC voltage {1+(C ₁ /C ₂ )}V _A is obtained. Note that each time the switch 4 is closed, the charge in the capacitor 2 is discharged and the output voltage becomes V _A. Therefore, the output voltage waveform 23 has a period of the level Vo indicated by 24 and a period of the level V _A indicated by 25. Repeat alternately. The capacitance values of capacitors 1 and 2 constituting the level shift circuit shown in Fig. 1 are:
The field-through effect of the control pulse voltages 19, 20 due to the gate capacitance of the MOST switches 4, 5, 6 may be so large that it can be ignored, and the value can be set to a sufficiently small value. Such a small-capacitance capacitor can be easily realized using MOS integrated circuit technology as an insulating film capacitor between a gate electrode and an inversion layer or between a two-layer electrode. Therefore, if a voltage divider (voltage dividing circuit) or the like configured by connecting load MOSTs in series is used as the constant voltage generating circuit 8, the level shift circuit shown in FIG.
It is easily integrated on the same substrate as the CCD using the same manufacturing process. Furthermore, according to the level shift circuit, the capacitance value C ₁ of capacitors 1 and 2
By selecting and _C2 , the input signal voltage Vs can also be amplified (attenuated).

However, in the configuration of the level shift circuit, once C ₁ /C ₂ is selected, the shift amount of the DC level is also uniquely determined, so the signal voltage superimposed on the optimal DC bias voltage V _B is applied to the CCD input terminal. In order to derive the voltage V A of the constant voltage generating circuit 8, it is necessary to limit the voltage V _A of the constant voltage generating circuit 8 to a specific value dependent on C ₁ /C ₂ . _{That is, V A is set to a specific value (V B / [ 1} + _{C 1} /C ₂ ]), which limits the degree of freedom in design. Also,
Due to the structure of the IC, it is desirable to reduce the constant voltage generation circuit, which requires constant current, as much as possible in terms of power consumption. However, in the conventional level shift circuit, the voltage value V _A of the constant voltage generation circuit 8
Since the voltage is limited, a specific constant voltage generation circuit is necessarily required, which is disadvantageous in terms of power consumption.

An object of the present invention is to solve the problems of the previously proposed level shift circuit, and to set the amount of shift of the DC level independently of the gain (loss) of the signal component and without using a specific constant voltage source. An object of the present invention is to provide an improved level shift circuit and a driving method thereof.

According to the present invention, an operational amplifier having a non-inverting input terminal connected to a first voltage, a first capacitor connected between an output terminal of the amplifier and an inverting input terminal, and a first capacitor connected in parallel with the capacitor. The first
a second and third capacitor having one end connected to the first voltage; a second switch provided between the second capacitor and the second voltage; a third switch provided between the capacitor and the third voltage;
There is also obtained a level shift circuit characterized in that it comprises fourth and fifth switches respectively provided between the third capacitor and the inverting side input terminal of the operational amplifier.

Furthermore, according to the present invention, in the level shift circuit, the opening/closing procedure of each of the switches is performed in a fourth manner.
The second switch is closed only when the fifth switch is open, and the third switch is closed only when the fifth switch is open. A level shift circuit characterized in that the fourth and fifth switches are selected to change from the open state to the closed state only when the switch is in the open state, and the opening/closing procedure is periodically repeated. A driving method is obtained.

The present invention will be explained below based on the drawings.

FIG. 3 is a block diagram showing one embodiment of a level shift circuit according to the present invention. In the figure, 30 is an operational amplifier, and 31, 32, and 33 are C _{31 and 33} , respectively.
Capacitors having capacitance values of C ₃₂ and C ₃₃ , 34,
35, 36, 37, and 38 are switches, and in this embodiment, a specific example is an N-channel type switch.
MOST switch is used. For convenience of the following explanation, it is assumed that the operational amplifier 30 performs differential direct current amplification centered on zero volts using power supply voltages that are symmetrical in positive and negative directions. In the circuit configuration shown in FIG. 3, an output terminal 40 of the operational amplifier 30 is led to an inverting input terminal 41 via a capacitor 31, forming a negative feedback loop. A switch 34 is provided in parallel with this negative feedback loop. On the other hand, the inverting side input terminal 41 is connected to a capacitor 3 whose one end is connected to a point with a voltage of zero volts via switches 37 and 38.
2 and 33, and terminals 42 and 43 are connected to switches 35 and 33.
6 respectively through signal source 45 and voltage source 46
It is tied to Further, the non-inverting side input terminal 39 of the operational amplifier 30 is connected to a point of zero volt voltage. In this embodiment, the switches 34, 35,
As an example of 36, 37, 38, N channel type
These MOST switches are periodically opened and closed (OFF-ON) by control pulse voltages (described later) applied to terminals 47 and 48.

FIG. 4 is for explaining an example of the driving method of the level shift circuit according to the present invention, and shows how the switches 34, 35, 3 in the embodiment shown in FIG.
FIG. 6 is a timing diagram showing the opening/closing procedures of Nos. 6, 37, and 38. In FIG. 4, 49 and 50 are control pulse voltages applied to the terminals 47 and 48 in FIG. shows. In this example, the switch is an N-channel type.
Since it is MOST, switches 34, 35, 36
is in a closed (ON) state during a period when the pulse voltage 49 is at a high level _VH , and is in an open (OFF) state during a period when the pulse voltage 49 is at a low level _VL . Similarly,
The switches 37 and 38 are closed (ON) during the period when the pulse voltage 50 is at the high level _VH ,
It is in an open (OFF) state during the period when the low level V _L is reached. That is, switches 34, 35, 36,
54, 55, 56, showing the open/closed state of 37, 38.
In 57 and 58, the solid line section represents the period when the switch is closed (ON), and the broken line section represents the period when the switch is open (OFF).

FIG. 5 is an explanatory diagram of the operation of this embodiment when the circuit shown in FIG. 3 is driven by the switch opening/closing procedure shown in FIG. 4. In the figure, 60 is the input signal voltage supplied from the signal source 45, 61 is the voltage of the voltage source 46, 62 is the voltage between the terminals of the capacitor 32, that is, the voltage of the terminal 42, and 63 is the voltage between the terminals of the capacitor 33, that is, the terminal 43 and 64 is the output voltage of this level shift circuit available at the output terminal 40 of the operational amplifier 30.

The operation of this embodiment will be explained using FIG. 3, FIG. 4, and FIG. 5. However, the times shown at the top of FIGS. 4 and 5 are indicated by the same reference numerals and represent the same times. First, at time _t0 in FIG. 4, switches 35 and 36 are closed, so that the voltage between the terminals of capacitor 32 moves with the input signal voltage 60 as shown at 62 in FIG. is charged to the voltage value V _BB of the voltage source 46 .
Also, since the switch 34 is closed, the operational amplifier 3
0 is a unity feedback connection, and the output terminal 40 and the inverting input terminal 41 are set at the same potential as the non-inverting input terminal 39, that is, 0 volts. At this time, there is naturally no accumulated charge in the capacitor 31. At time _t1 , switch 35 opens and signal source 45
When the voltage 60 is disconnected, the capacitor 32 receives a voltage C ₃₂ .proportional to the input signal voltage Vs ₁ at this time.
A stored charge of Vs ₁ remains, and thereafter the voltage 62 at terminal 42 is held at Vs ₁ . Similarly, switch 36
opens and the voltage source 46 is disconnected, the capacitor 33 has a voltage _VBB corresponding to the voltage value of the constant voltage source 46.
The amount of accumulated charge C ₃₃・V _BB remains, and from then on terminal 43
voltage 63 is held at V _BB . Furthermore, this time
At t ₁ , switch 34 also opens, but capacitor 3
The accumulated charge of 1 is still zero, and the output voltage 64 is 0.
It remains a bolt. Next, at time t ₂ , switch 37
and 38 close, capacitors 32 and 3
3 is connected to the inverting side input terminal 41 of the operational amplifier 30. At this time, the operational amplifier 30 amplifies the potential difference between the inverting side input terminal 41 and the non-inverting side input terminal 39 and feeds it back to the inverting side input terminal 41 via the capacitor 31. acts to bring the inverting side input terminal 41 to the same potential as the non-inverting side input terminal 39. Therefore, terminal 4
2 and 43 both become almost 0 volts, and C ₃₂・Vs ₁ and C ₃₃・ that had been accumulated in capacitors 32 and 33.
All of the charge amount V _BB is transferred to the capacitor 31 . Therefore, the operational amplifier output terminal 4 at this time
If the voltage value of 0 is Vo ₁ , then C ₃₂・Vs ₁ +C ₃₃・V _BB = −C ₃₁・Vo ₁ , and the output voltage value Vo ₁ is Vo ₁ = −(C ₃₂ /C ₃₁ )Vs ₁ −(C ₃₃ /C ₃₁ ) V _BB . At time _t3 , switches 37 and 3
8 is opened, but the accumulated charge in the capacitor 31 remains unchanged, so the value of the output voltage 64 remains Vo ₁ . The above is one cycle of operation in this embodiment. From then on, the same operation is repeated from t ₄ , and the input signal voltage values Vs ₂ and Vs ₃ at the moment when the switch 35 is opened, that is, at times t ₅ and t ₉ , etc. etc., the output voltage values Vo ₂ and Vo ₃ are obtained sequentially. Note that each time the switch 34 is closed, the accumulated charge in the capacitor 31 is discharged, and the output voltage 64 becomes 0 volts periodically. As explained above, in this embodiment, the sample value Vs of the input signal is accumulated and held in the capacitor 32 as a charge of C ₃₂ ·Vs by first closing and then opening the switch 35, and by closing and then opening the switch 36. A charge amount _C33 · _VBB proportional to the voltage value _VBB of the voltage source 46 is stored in another capacitor 33. Next, the switches 37 and 38 are closed, and the amount of charge accumulated in the capacitors 32 and 33 is integrated by the capacitor 31 forming the negative feedback loop of the operational amplifier 30, so that the output voltage [-(C ₃₂ /C ₃₁ ) Vs-(C ₃₃ /C ₃₁ )V _BB ], that is, the signal voltage [-(C ₃₂ /C ₃₁ )Vs] superimposed on the DC bias voltage [-(C ₃₃ /C ₃₁ )V _BB ] is obtained. There is.

In this embodiment, by appropriately selecting the capacitance value C ₃₂ of the capacitor 32 with respect to the capacitance value C ₃₁ of the capacitor 31, _a desired degree of amplification for the input signal voltage can be obtained. By appropriately selecting the capacitance value C33 of the capacitor ₃₃ with respect to the value _VBB , a desired DC level shift amount can be obtained. Therefore, the amount of DC level shift and signal gain can be determined independently. Also, depending on the capacitance value C ₃₃ , the DC level shift amount [-(C ₃₃ /
C ₃₁ )V _BB ], the voltage value V _BB of the voltage source 8 is not limited when obtaining a desired DC level shift amount. Therefore, there is no need for a specific constant voltage source, and for example, the power supply voltage of the operational amplifier 30 can be used as the voltage source 8. In addition, this example
When used as an input bias circuit for a CCD, the constant voltage source 8 may be a constant voltage generation circuit provided for driving the CCD, such as a voltage dividing circuit for generating a bias voltage for the CCD electrodes. It becomes possible.

Therefore, according to this embodiment, the amount of shift of the DC level and the signal gain are set independently, and a specific voltage source is not required for setting the amount of DC level shift. A level shift circuit that has a higher degree of freedom in design than a shift circuit and can reduce power consumption can be obtained.

As shown in FIGS. 4 and 5, one cycle of the operation of this embodiment is to close the switches 35 and 36, and use the signal source and constant voltage source to connect the capacitor 3.
and 33 charging period 71, and switch 35
and a period 72 in which the capacitors 32 and 33 accumulate an amount of charge proportional to the sample value of the signal voltage and the voltage value of the voltage source by opening and 36;
Switch 34 is opened and switches 37 and 38 are closed, and the amount of charge accumulated in capacitors 32 and 33 is transferred to capacitor 31 via operational amplifier 30.
A period 73 in which the desired DC level shift amount and amplification degree for the signal voltage component are obtained by shifting to
and a period 74 during which switches 37 and 38 are opened and capacitors 42 and 43 are isolated from operational amplifier 30 in preparation for the next cycle. Note that the accumulated charge in the capacitor 41 needs to be discharged every cycle, and in this embodiment, this is done using the period 71.

However, the driving pulse voltages 49 and 50 and the corresponding opening/closing states of each switch in the above embodiment shown in FIG. 4 are merely examples, and the present invention is not limited to these. In the above embodiment, switches 35 and 36 are closed only when switches 37 and 38 are open.

Switches 37 and 38 change from the open state to the closed state only when switch 34 is in the open state.

As long as the above two conditions are satisfied, other time relationships may be selected in any manner. For example, period 74
is not necessarily necessary, and even if the closed state of the switches 37 and 38 is extended until the time when the switch 34 is in the closed state, the operation can still be achieved. Note that the remaining three periods 71, 72, and 73 are necessary, but the proportion of these periods in one cycle is free. In the above embodiment, the gates of the MOST switches 34, 35, and 36 are connected to the terminal 47.
Connect the gates of MOST switches 37 and 38 to terminal 48.
are commonly connected to the two-phase drive pulse voltage 4.
9 and 50, a driving method is adopted in which the open/close states of five switches are controlled, but it is clear from the specification that this is just an example, and that many variations are possible. It is.

As is clear from the above description, the feature of the level shift circuit according to the present invention is that the shift amount of the DC level and the degree of amplification for the signal voltage can be set independently, and the degree of freedom in design is greater than that of conventional level shift circuits. It is at an increased point. That is, in the conventional configuration shown in FIG. 1, when the amplification degree C ₁ /C ₂ for the signal voltage component is specified, the shift amount of the DC level is also limited to (1+C ₁ /C ₂ )V _A. In the present invention, as described in the above embodiment, by selecting C ₃₂ and C ₃₃ , the amplification degree for the signal voltage component can be adjusted.
C ₃₂ /C ₃₁ and DC level shift amount - (C ₃₃ /C ₃₁ )V _B
The circuit configuration and driving method have been modified so that _B can be selected independently. As a result, since the amount of DC level shift can be adjusted using C ₃₃ , there is no need for a specific constant voltage source to obtain the desired amount of DC level shift, and compared to conventional level shift circuits,
Reduces power consumption.

As described above, the present invention is effective in increasing the degree of freedom in the design of level shift circuits and reducing power consumption.
Furthermore, since it is suitable for integration, its effect is remarkable when used as an input bias circuit for a CCD.

[Brief explanation of the drawing]

Figure 1 is a diagram showing a configuration example of a level shift circuit conventionally considered as an input bias circuit for a CCD. 1 and 2 are capacitors, 3 is an operational amplifier, 4, 5, and 6 are MOST switches, and 7 is a The signal source 8 is a constant voltage generating circuit, and 9 and 10 are terminals for applying control pulse voltages to the switches 4, 5, and 6. 2 is a timing diagram for explaining an example of the operation of the level shift circuit shown in FIG. 1, 19 and 20 are examples of control pulse voltages applied to terminals 9 and 10 in FIG.
5 and 16 are the open/close states of switches 4, 5, and 6 at this time, 21 is the input signal voltage, and 22 is the capacitor 1.
and 23 indicate the output voltage appearing at the output terminal of the operational amplifier 3, respectively. FIG. 3 is a diagram showing the configuration of a level shift circuit in an embodiment of the present invention, in which 30 is an operational amplifier, 31,
32, 33 are capacitors, 34, 35, 36, 3
7, 38 are MOST switches, 45 is a signal source, 4
6 is a voltage source, 47 is a switch 34, 35, 36
A terminal 48 is a terminal for applying a control pulse voltage to the switches 37 and 38. FIG. 4 is a timing diagram showing a method of driving the level shift circuit in an embodiment of the present invention, 49 and 50 are control pulse voltages applied to the terminals 47 and 48 in FIG. 3, and 54, 55,
Reference numerals 56, 57, and 58 indicate the open and closed states of the switches 34, 35, 36, 37, and 38, respectively, at this time. FIG. 5 is an explanatory diagram of the operation of the embodiment shown in FIGS. 3 and 4, where 60 is the input signal voltage, 61 is the voltage of the voltage source 46, 62 is the voltage between the terminals of the capacitor 32, and 63 is the capacitor. Voltage between terminals of 33, 6
4 is the output voltage obtained at the output terminal of the operational amplifier 30.

Claims (1)

[Claims] 1. An operational amplifier whose non-inverting input terminal is connected to a first voltage, a first capacitor connected between the output terminal of the amplifier and the inverting input terminal, and a first capacitor connected to the capacitor. a first switch provided in parallel;
second and third capacitors, one end of which is connected to the first voltage;
a second switch provided between the third capacitor and the third voltage, a third switch provided between the third capacitor and the third voltage, the second and third capacitors, and the operational amplifier. A level shift circuit comprising a fourth switch and a fifth switch respectively provided between the inverting side input terminal of the switch and the inverting side input terminal of the switch. 2 an operational amplifier whose non-inverting input terminal is connected to a first voltage; a first capacitor connected between the output terminal of the amplifier and the inverting input terminal; and a first capacitor connected in parallel to the capacitor. 1 switch and
second and third capacitors, one end of which is connected to the first voltage;
a second switch provided between the third capacitor and the third voltage, a third switch provided between the third capacitor and the third voltage, the second and third capacitors, and the operational amplifier. In a level shift circuit comprising fourth and fifth switches respectively provided between the inverting side input terminal of The third switch is selected to be closed only when the second switch is closed and the fifth switch is open, and the third switch is selected to be closed only when the first switch is open. A method for driving a level shift circuit, characterized in that the fourth and fifth switches are selected to change from an open state to a closed state, and the opening/closing procedure is periodically repeated.