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JPS6236391B2 - - Google Patents
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JPS6236391B2 - - Google Patents

Info

Publication number
JPS6236391B2
JPS6236391B2 JP57076941A JP7694182A JPS6236391B2 JP S6236391 B2 JPS6236391 B2 JP S6236391B2 JP 57076941 A JP57076941 A JP 57076941A JP 7694182 A JP7694182 A JP 7694182A JP S6236391 B2 JPS6236391 B2 JP S6236391B2
Authority
JP
Japan
Prior art keywords
brazing
metal
brazing material
semiconductor element
brazed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57076941A
Other languages
Japanese (ja)
Other versions
JPS5890748A (en
Inventor
Shinzo Anazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP57076941A priority Critical patent/JPS5890748A/en
Publication of JPS5890748A publication Critical patent/JPS5890748A/en
Publication of JPS6236391B2 publication Critical patent/JPS6236391B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00Packaging processes not covered by the other groups of this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07551Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/547Dispositions of multiple bond wires

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置とくにろう付部を有する半
導体装置に係るものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device having a brazed portion.

小型電子回路装置、特に混成集積回路或いは高
周波用半導体装置の発展に伴い種々の絶縁材料が
使用される様になつた。周知の如く最近電子回路
の小型化の強調と電気的特性面からの要求から、
使用される材料並びに物理的な構造に大きな制約
がかかり、要求される特性の全てを満足せしめる
為にはかなり困難な問題が存する。その内の重要
な問題はろう付である。電子回路用基板又は容器
等の限られた面積に金属リード等をろう付する
際、所定のろう付強度を確保する為にはその構成
材料の特質、メタライズ技術、ろう付技術の調和
がとれていないといけないが、一方高周波特性等
の電気的な面から単なるろう付技術の面から考慮
した解決を適用出来ないことが多い。例えば第1
図に示す如く絶縁基板1の表面にメタライズ層2
を施し、該層2に平型のリード3をろう付する場
合に、要求されるろう付強度を得る為にはメタラ
イズ層の幅、リードの幅、ろう材4の量を適宜に
選択しなければならない。例えば絶縁基板1とし
て、誘電率が低く且つ熱放散のよいベリリアセラ
ミツクを採用し、所望の特性インピーダンスを保
有せしめる電子回路基板を製作する場合には、電
気的特性を優先せしめる必要からメタライズ層の
幅、リードの幅に制限をうけ、所定のメタライズ
強度、ろう付強度を得る事が困難な事が多い。特
に高周波領域に使用する電子回路に於いてその影
響は顕著である。この解決の為に今迄種々提案さ
れている方法として、第2図に示す如く絶縁基板
1の上に設けられたメタライズ層2に外部引出リ
ード3をろう材4でろう付する際に出来るだけろ
う付部にろう材4が溜まる様にして歪の緩和を計
るとか、或いは第3図に示す如く絶縁基板1の側
面の一部にメタライズ層2″を設けてろう付の際
のろう溜を生じせしめてろう付強度を増加せしめ
る方法がある。その他外部引出リード3のろう付
部分に孔を設けたり又は第4図に示す如き形状に
してろう材4が溜り易くしたりする方法も提案さ
れている。しかしながら第2図の場合は実質的に
ろう材4が外部引出リード3の他の部分に流れて
しまうのでろう溜を歩留よくつくる事は困難であ
り、又第3図の如き構成の場合には絶縁基板1の
側面メタライズ層2″と裏面メタライズ2′の間の
実質的静電容量を増加せしめて電気的特性を損わ
しめる欠点がある。又外部引出リードの形状に工
夫をこらしても多少ろう溜歩留がよくなるだけで
本質的な解決は得られない。
With the development of small electronic circuit devices, especially hybrid integrated circuits and high frequency semiconductor devices, various insulating materials have come to be used. As is well known, due to the recent emphasis on miniaturization of electronic circuits and demands from the electrical characteristics aspect,
There are significant restrictions on the materials used and the physical structure, and there are considerable difficulties in satisfying all of the required properties. An important issue among these is brazing. When brazing metal leads, etc. to a limited area such as an electronic circuit board or container, in order to ensure the specified brazing strength, the characteristics of the constituent materials, metallization technology, and brazing technology must be balanced. However, due to electrical aspects such as high frequency characteristics, it is often impossible to apply solutions that are considered simply from the perspective of brazing technology. For example, the first
As shown in the figure, a metallized layer 2 is formed on the surface of an insulating substrate 1.
When brazing a flat lead 3 to the layer 2, the width of the metallized layer, the width of the lead, and the amount of brazing material 4 must be selected appropriately in order to obtain the required brazing strength. Must be. For example, when manufacturing an electronic circuit board that uses beryllia ceramic, which has a low dielectric constant and good heat dissipation, as the insulating substrate 1 and has a desired characteristic impedance, it is necessary to give priority to electrical characteristics, so the metallized layer is It is often difficult to obtain the specified metallization strength and brazing strength due to limitations on width and lead width. The effect is particularly noticeable in electronic circuits used in high frequency ranges. To solve this problem, various methods have been proposed up to now, as shown in FIG. The strain can be alleviated by allowing the brazing material 4 to accumulate in the brazing part, or by providing a metallized layer 2'' on a part of the side surface of the insulating substrate 1 as shown in FIG. There is a method of increasing the brazing strength by increasing the brazing strength.Other methods have also been proposed, such as providing a hole in the brazing part of the external lead 3 or creating a shape as shown in FIG. 4 to make it easier for the brazing material 4 to accumulate. However, in the case of FIG. 2, the brazing material 4 substantially flows to other parts of the external lead 3, making it difficult to create a wax reservoir with a good yield. In this case, there is a drawback that the substantial capacitance between the side metallized layer 2'' and the back metallized layer 2' of the insulating substrate 1 increases, thereby impairing the electrical characteristics. Furthermore, even if the shape of the external lead is modified, the wax yield will only improve to some extent, but no essential solution will be obtained.

一方電子回路の組立面から考えた場合に、ろう
材が流出して電子回路素子をマウントする所又は
金属細線等でボンデイングする所に種々のトラブ
ル例えばマウント又はボンデイングが不可能であ
るとか或いはマウントが出来ても熱抵抗を増大せ
しめるとか、接続浮遊容量を増すとか又はボンデ
イングが出来てもボンデイング強度が弱いとか、
長期の寿命試験でボンデイング強度が落ちてくる
等の欠点がある。
On the other hand, when considering the assembly of electronic circuits, brazing filler metal may leak out and cause various problems at the locations where electronic circuit elements are mounted or where bonding is performed with thin metal wires, etc. For example, mounting or bonding may not be possible, or mounting may not be possible. Even if bonding is possible, it increases the thermal resistance, increases the stray capacitance of the connection, or even if bonding is possible, the bonding strength is weak.
There are drawbacks such as the bonding strength decreasing during long-term life tests.

本発明は従来の上記諸欠点を除去する為になさ
れたものであり、従つて本発明の目的は、金属体
上に半導体素子をろう付した半導体装置におい
て、電気的、機械的特性を劣化させることなく、
所定のろう付強度を容易に確保することができる
新規な半導体装置を提供することにある。
The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional technology, and therefore, an object of the present invention is to solve the problem of deteriorating the electrical and mechanical characteristics of a semiconductor device in which a semiconductor element is brazed onto a metal body. without any
An object of the present invention is to provide a novel semiconductor device that can easily ensure a predetermined brazing strength.

本発明によれば、金属体上に半導体素子とこれ
を封入する壁部材とをろう付した半導体装置にお
いて、壁部材および半導体素子をろう付する部分
の金属体表面にはろう材にぬれやすい金属部材が
設けられ、半導体素子と壁部材との間にはろう材
にぬれにくい金属を介在せしめた半導体装置を得
る。
According to the present invention, in a semiconductor device in which a semiconductor element and a wall member enclosing the semiconductor element are brazed onto a metal body, the surface of the metal body in the portion where the wall member and the semiconductor element are brazed is made of a metal that is easily wetted by the brazing material. A semiconductor device is obtained in which a member is provided and a metal that is difficult to wet with a brazing material is interposed between a semiconductor element and a wall member.

本発明のろう付技術はこの様にろう付部にはろ
う材が濡れ易い(なじみ易い)金属層を設け、ろ
う材の流出してはならない部分に対しては少くと
もろう材と近接する部分にろう材が濡れにくい
(なじみ難い)金属とする技術である。即ちろう
付部にろう材が濡れ易い金属層と濡れにくい金属
とを連続して配置する事により、ろう溜が容易に
出来ると同時に、従来の技術に於いて生ずるろう
材の流出に基づく前記の如き種々の障害を防止す
るものである。
In this way, the brazing technology of the present invention provides the brazing part with a metal layer that is easily wettable (easily compatible) with the brazing material, and at least the portions that are close to the brazing material are provided in areas where the brazing material should not flow out. This is a technique that makes the brazing material a metal that is difficult to wet (hard to get acquainted with). That is, by consecutively arranging a metal layer that is easily wetted by the brazing material and a metal that is difficult to wet the brazing material in the brazing part, a brazing pool can be easily formed, and at the same time, the above-mentioned problem caused by the outflow of the brazing material that occurs in the conventional technology can be avoided. This prevents various troubles such as:

金属体として、ろう材が濡れにくい金属を用い
ると、ろう付すべき部分にろう材が濡れ易い金属
を被着し、ろう材が濡れにくい金属の金属体の素
面を露出してろう材の流出に対する塞き止め部と
して作用せしめることができる。
If a metal that is difficult to wet with the brazing material is used as the metal body, the part to be brazed will be coated with a metal that is easy to get wet with the brazing material, exposing the bare surface of the metal body that is difficult to get wet with the brazing material, and preventing the soldering material from flowing out. It can act as a blocking part.

次に本発明を更に具体的に明白にする為に実施
例に基き第5図および第6図を参照しながら説明
する。
Next, in order to clarify the present invention more specifically, an explanation will be given based on an embodiment with reference to FIGS. 5 and 6.

第5図は本発明に係る一実施例を説明する為の
図であり、スタツド(放熱体)16(例えば銅)
に通常の積層セラミツク技術に基いた絶縁壁部材
17(例えばアルミナ)(該絶縁部材17には容
器の電極となるべきメタライズ層18及び前記ス
タツド16にろう付する為のメタライズ層18′
が設けられている)を及び外部引出リード13を
ろう付して容器を形成し、該容器の内部に半導体
素子19(例えばトランジスタ)をマウントし金
属細線(例えば金線)20,20′によつて前記
半導体素子19の電極と該半導体容器とを電気的
に接続してなる半導体装置例えばFETに於い
て、スタツド16と絶縁壁部材17とをろう材1
4(例えば銀銅共晶ろう)でろう付の際に、スタ
ツド16のろう付部分のみにろう材14が濡れ易
い金属層15(例えばNi)をメツキ等で施した
後に、該金属層15の一部を除去してろう材の濡
れにくい金属層を露出せしめ、即ち例えば切削等
により溝21を設けたり、或いは第6図に示す如
くスタツド16に突出部22を設け該突出部22
を何らかの方法で遮閉してろう材14が濡れ易い
金属層15を被覆する、即ちろう材が濡れにくい
金属層としてもよい。これらの溝21又は突出部
22を形成すれば、半導体素子のマウント部及び
金属細線のボンデイング部はろう付部分からかな
り距離が長くなるので、該マウント部及びボンデ
イング部に対する信頼度は更に一段と増大する。
尚ろう材の流れ防止の為にろう流れ防止剤の塗布
とか、或いは硝子とか酸化層を部分的に設ける等
の方法も考えられるが、ろう流れ防止剤の塗布、
除去に高度の技術が要求されるし、又硝子とか酸
化層の設置は酸化雰囲気還元雰囲気のサイクルに
よる材質劣化を惹起し、且つ該層の設置、除去等
に高度の技術が要求される事及び両技術共に著し
い工数がかかる等の理由により望ましい方法とは
言えない。
FIG. 5 is a diagram for explaining one embodiment of the present invention, in which a stud (heat sink) 16 (for example, copper) is used.
An insulating wall member 17 (for example, alumina) based on the usual laminated ceramic technology (the insulating member 17 includes a metallized layer 18 to become an electrode of the container and a metallized layer 18' to be brazed to the stud 16).
A container is formed by brazing the external drawer lead 13 and a semiconductor element 19 (for example, a transistor) is mounted inside the container, and is connected by thin metal wires (for example, gold wire) 20, 20'. In a semiconductor device, for example, an FET, in which the electrodes of the semiconductor element 19 and the semiconductor container are electrically connected, the studs 16 and the insulating wall member 17 are connected with the brazing material 1.
4 (for example, silver-copper eutectic solder), a metal layer 15 (for example, Ni) that easily wets the brazing material 14 is applied only to the brazed portion of the stud 16 by plating, etc., and then the metal layer 15 is A part of the stud 16 is removed to expose the metal layer that is difficult to wet with the brazing material, that is, a groove 21 is provided by cutting or the like, or a protrusion 22 is provided on the stud 16 as shown in FIG.
The metal layer 15 which is easily wetted by the brazing material 14 may be covered by shielding and closing it in some way, that is, the metal layer 15 which is easily wetted by the brazing material 14 may be formed as a metal layer which is difficult to get wetted by the brazing material 14. If these grooves 21 or protrusions 22 are formed, the distance between the mounting part of the semiconductor element and the bonding part of the thin metal wire will be considerably longer from the brazing part, so the reliability of the mounting part and the bonding part will further increase. .
In order to prevent the wax from flowing, methods such as applying a wax flow preventive agent or partially providing a glass or oxidized layer may be considered; however, applying a wax flow preventive agent,
Removal requires advanced technology, and installation of glass or oxide layers causes material deterioration due to cycles of oxidizing and reducing atmospheres, and installation and removal of such layers requires advanced technology. Both techniques cannot be said to be desirable methods because they require a significant amount of man-hours.

しかして、本発明によれば、被ろう付体及びそ
の近接する部材の機械的、電気的諸特性を劣化せ
しめることなく、所定のろう付強度を極めて容易
に確保することができるろう付方法が与えられ、
前記した従来の諸欠点がことごとく解消される。
According to the present invention, there is provided a brazing method that can extremely easily ensure a predetermined brazing strength without deteriorating the mechanical and electrical properties of the object to be brazed and its adjacent members. given,
All of the conventional drawbacks mentioned above are completely eliminated.

以上本発明はその良好な実施例について説明さ
れたが、それは単なる例示的なものであつて制限
的意味を有するものでないことは勿論である。従
つて本発明の精神及び範囲から逸脱することなし
に本発明は種々の変更を加えて実施し得るが、そ
れらはすべて前記した本願特許請求の範囲内に包
含されるものである。
Although the present invention has been described above with respect to its preferred embodiments, it goes without saying that these are merely illustrative and do not have a limiting meaning. Accordingly, the present invention may be practiced with various modifications without departing from the spirit and scope of the invention, but all such modifications are included within the scope of the claims of the present invention.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はろう付技術に於ける基本図、第2〜第
4図は従来のろう付技術を説明する為の図、第5
図および第6図は本発明にかかる各実施例を説明
する為の断面図である。 1……絶縁基板、2,12……メタライズ層、
3,13……外部引出リード、4,14……ろう
材、5,15……ろう材が濡れ易い金属層、16
……スタツド、17……絶縁壁部材、18……メ
タライズ層、19……半導体素子、20……金属
細線、21……溝、22……突出部。
Figure 1 is a basic diagram of brazing technology, Figures 2 to 4 are diagrams for explaining conventional brazing technology, and Figure 5 is a basic diagram of brazing technology.
The figures and FIG. 6 are cross-sectional views for explaining each embodiment according to the present invention. 1... Insulating substrate, 2, 12... Metallized layer,
3, 13... External drawer lead, 4, 14... Brazing metal, 5, 15... Metal layer to which the brazing metal is easily wetted, 16
... Stud, 17 ... Insulating wall member, 18 ... Metallized layer, 19 ... Semiconductor element, 20 ... Fine metal wire, 21 ... Groove, 22 ... Projection.

Claims (1)

【特許請求の範囲】[Claims] 1 金属体上に半導体素子とこれを封入する壁部
材とをろう付した半導体装置において、前記壁部
材および半導体素子をろう付する部分の前記金属
体表面にはろう材にぬれやすい金属部材が設けら
れ、前記半導体素子と壁部材との間には前記ろう
材にぬれにくい金属を介在せしめたことを特徴と
する半導体装置。
1. In a semiconductor device in which a semiconductor element and a wall member enclosing the semiconductor element are brazed onto a metal body, a metal member that is easily wetted by a brazing material is provided on the surface of the metal body in a portion where the wall member and the semiconductor element are brazed. A semiconductor device characterized in that a metal that is difficult to wet with the brazing material is interposed between the semiconductor element and the wall member.
JP57076941A 1982-05-07 1982-05-07 Semiconductor device Granted JPS5890748A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57076941A JPS5890748A (en) 1982-05-07 1982-05-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57076941A JPS5890748A (en) 1982-05-07 1982-05-07 Semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP49100939A Division JPS5819385B2 (en) 1974-09-04 1974-09-04 Rouzukehouhou

Publications (2)

Publication Number Publication Date
JPS5890748A JPS5890748A (en) 1983-05-30
JPS6236391B2 true JPS6236391B2 (en) 1987-08-06

Family

ID=13619764

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57076941A Granted JPS5890748A (en) 1982-05-07 1982-05-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5890748A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59195856A (en) * 1983-04-20 1984-11-07 Fujitsu Ltd Semiconductor device and manufacture thereof
JPS61107751A (en) * 1984-10-30 1986-05-26 Nec Kansai Ltd Resin mold type semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5819385B2 (en) * 1974-09-04 1983-04-18 日本電気株式会社 Rouzukehouhou

Also Published As

Publication number Publication date
JPS5890748A (en) 1983-05-30

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