JPS6236392B2 - - Google Patents
Info
- Publication number
- JPS6236392B2 JPS6236392B2 JP57076942A JP7694282A JPS6236392B2 JP S6236392 B2 JPS6236392 B2 JP S6236392B2 JP 57076942 A JP57076942 A JP 57076942A JP 7694282 A JP7694282 A JP 7694282A JP S6236392 B2 JPS6236392 B2 JP S6236392B2
- Authority
- JP
- Japan
- Prior art keywords
- brazing
- metal
- wall member
- brazing material
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W95/00—Packaging processes not covered by the other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
- H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置に関し、とくにろう付技術
を必要とする半導体装置に係るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device that requires brazing technology.
小型電子回路装置、特に混成集積回路或いは高
周波用半導体装置の発展に伴い種々の絶縁材料が
使用される様になつた。周知の如く最近半導体装
置の小型化の強調と電気的特性面からの要求から
使用される材料並びに物理的な構造に大きな制約
がかかり、要求される特性の全てを満足せしめる
為にはかなり困難な問題が存する。その内の重要
な問題はろう付である。半導体素子搭載用基板又
は容器等の限られた面積に装置構成体をろう付す
る際、所定のろう付強度を確保する為にはその構
成材料の性質、メタライズ技術、ろう付技術の調
和がとれていないといけないが、高周波特性等の
電気的な面や単なるろう付技術の面からだけでは
この調和をとることはできないことが多い。例え
ば第1図に示す如く絶縁基板1の表面にメタライ
ズ層2を施し、該層2に平型のリード3をろう付
する場合に、要求されるろう付強度を得る為には
メタライズ層の幅、リードの幅、ろう材4の量を
適宜に選択しなければならない。例えば絶縁基板
1として、誘電率が低く且つ熱放散のよいベリリ
アセラミツクを採用し、所望の特性インピーダン
スを保有せしめる電子回路基板を製作する場合に
は、電気的特性を優先せしめる必要からメタライ
ズ層の幅、リードの幅に制限をうけ、所定のメタ
ライズ強度、ろう付強度を得る事が困難な事が多
い。特に高周波領域に使用する電子回路に於いて
その影響は顕著である。この解決の為に今迄種々
提案されている方法として、第2図に示す如く絶
縁基板1の上に設けられたメタライズ層2に外部
引出リード3をろう材4でろう付する際に出来る
だけろう付部にろう材4が溜まる様にして歪の緩
和を計るとか、或いは第3図に示す如く絶縁基板
1の側面の一部にメタライズ層2″を設けてろう
付の際のろう溜を生じせしめてろう付強度を増加
せしめる方法がある。その他外部引出リード3の
ろう付部分に孔を設けたり又は第4図に示す如き
形状にしてろう材4が溜り易くしたりする方法も
提案されている。 With the development of small electronic circuit devices, especially hybrid integrated circuits and high frequency semiconductor devices, various insulating materials have come to be used. As is well known, the recent emphasis on miniaturization of semiconductor devices and the demands for electrical characteristics have placed significant restrictions on the materials and physical structures used, making it extremely difficult to satisfy all of the required characteristics. There is a problem. An important issue among these is brazing. When brazing device components onto a limited area such as a substrate or container for mounting semiconductor elements, it is necessary to balance the properties of the constituent materials, metallization technology, and brazing technology in order to ensure the desired brazing strength. However, it is often not possible to achieve this harmony only from the electrical aspects such as high frequency characteristics or simply from the aspect of brazing technology. For example, when a metallized layer 2 is applied to the surface of an insulating substrate 1 as shown in FIG. 1, and a flat lead 3 is brazed to the layer 2, the width of the metallized layer must be , the width of the leads, and the amount of brazing filler metal 4 must be selected appropriately. For example, when manufacturing an electronic circuit board that uses beryllia ceramic, which has a low dielectric constant and good heat dissipation, as the insulating substrate 1 and has a desired characteristic impedance, it is necessary to give priority to electrical characteristics, so the metallized layer is It is often difficult to obtain the specified metallization strength and brazing strength due to limitations on width and lead width. The effect is particularly noticeable in electronic circuits used in high frequency ranges. To solve this problem, various methods have been proposed up to now, as shown in FIG. The strain can be alleviated by allowing the brazing material 4 to accumulate in the brazing part, or by providing a metallized layer 2'' on a part of the side surface of the insulating substrate 1 as shown in FIG. There is a method of increasing the brazing strength by increasing the brazing strength.Other methods have also been proposed, such as providing a hole in the brazing part of the external lead 3 or creating a shape as shown in FIG. 4 to make it easier for the brazing material 4 to accumulate. ing.
しかしながら第2図の場合は実質的にろう材4
が外部引出リード3の他の部分に流れてしまうの
でろう溜を歩留よくつくる事は困難であり、接続
強度も弱い。又第3図の如き構成の場合には絶縁
基板1の側面メタライズ層2″と裏面メタライズ
2′の間の実質的静電容量を増加せしめ電気的特
性を損わしめる欠点がある。又外部引出リードす
なわちろう付体の形状に工夫をこらしても多少ろ
う溜歩留がよくなるだけで本質的な解決は得られ
ない。 However, in the case of Fig. 2, the brazing material 4
Since the wax flows to other parts of the external lead 3, it is difficult to form a wax reservoir with a good yield, and the connection strength is also weak. Further, in the case of the structure as shown in FIG. 3, there is a drawback that the substantial capacitance between the side metallized layer 2'' and the back metallized layer 2' of the insulating substrate 1 increases, impairing the electrical characteristics. Even if the shape of the lead, that is, the brazing body is modified, the solder retention rate will only improve somewhat, but no essential solution will be obtained.
一方電子回路の組立面から考えた場合に、ろう
材が流出して電子回路素子をマウントする所又は
金属細線等でボンデイングする所に種々のトラブ
ル例えばろう材拡散によりマウント又はボンデイ
ングが不可能になるとか或いはマウントが出来て
も熱抵抗を増大せしめるとか、接続浮遊容量を増
すとか又はボンデイングが出来てもボンデイング
強度が弱いとか、長期の寿命試験でボンデイング
強度が落ちてくる等の欠点がある。中でも半導体
素子を封入する容器構造において、封入用壁部材
のろう付は極めて欠点が多く困難であつた。 On the other hand, when considering the assembly of electronic circuits, various problems may occur at the locations where electronic circuit elements are mounted or bonded with fine metal wires due to the leakage of the brazing material, for example, the diffusion of the brazing material makes mounting or bonding impossible. Alternatively, even if mounting is possible, there are disadvantages such as increasing thermal resistance, increasing connection stray capacitance, or even if bonding is possible, bonding strength is weak, and bonding strength decreases in long-term life tests. In particular, in a container structure for enclosing a semiconductor element, brazing the enclosing wall member has many drawbacks and is difficult.
本発明の目的は、被ろう付体、その他の電気
的、機械的特性を劣化させることなく、壁部材の
ろう付強度を容易に確保することができる構造の
半導体装置を提供することにある。 An object of the present invention is to provide a semiconductor device having a structure in which the brazing strength of a wall member can be easily ensured without deteriorating the electrical and mechanical properties of the object to be brazed and other electrical and mechanical properties.
本発明は上記目的は、壁部材が接続される金属
板の表面において前記壁部材が当接される部分に
ろう材にぬれやすい金属部材を選択的に設け、こ
の金属部材と前記壁部材とをろう付したことを特
徴とする半導体装置によつて達成される。 The above object of the present invention is to selectively provide a metal member that is easily wetted by a brazing material on the surface of a metal plate to which a wall member is connected, at a portion where the wall member abuts, and to connect this metal member and the wall member. This is achieved by a semiconductor device characterized by being soldered.
本発明の半導体装置はこの様にろう材が濡れ易
い(なじみ易い)金属部材によつてろう付部を限
定し、その部分にのみろう材がたまるようにし、
かつ前記金属層の周辺がろう材流出をせき止める
境界として作用するようにして、この金属層と近
接する金属板上へろう材が拡散しないように工夫
されている。 In this way, in the semiconductor device of the present invention, the brazing part is limited by the metal member to which the brazing material easily wets (fits easily), so that the brazing material accumulates only in that part,
Furthermore, the periphery of the metal layer acts as a boundary to stop the outflow of the brazing material, so that the brazing material does not spread onto the metal plate adjacent to the metal layer.
即ち単に金属板にろう付するのではなく、その
ろう付すべき部分以外にろう材が流れないように
ろう材に濡れ易い金属層を設け、金属板の方へろ
う材が拡散しないようにして従来の技術に於いて
生ずるろう材の流出に基づく前記の如き種々の障
害を防止するものである。 In other words, instead of simply brazing to a metal plate, a metal layer that is easily wetted by the brazing material is provided to prevent the brazing material from flowing to areas other than those to be brazed, and to prevent the brazing material from spreading toward the metal plate. This is to prevent the various troubles mentioned above due to the leakage of the brazing filler metal that occurs in this technique.
また換言すれば、本発明は、金属板としてろう
材が濡れにくい金属体を用い、ろう材すべき部分
をろう材が濡れ易い金属部材で被着することによ
り前記金属体の表面とくにろう材がぬれやすい金
属部材との境界部でろう材が金属部材側に収縮す
るようにしてろう材の流出に対する塞き止め部と
して作用せしめることを特徴とする壁部材の取り
付け構造である。 In other words, the present invention uses a metal body to which the brazing material does not easily wet as the metal plate, and by covering the portion where the brazing material is to be coated with a metal member to which the brazing material easily wets, the surface of the metal body, especially the brazing material, is This wall member mounting structure is characterized in that the brazing filler metal contracts toward the metal member at the boundary with the easily wetted metal member, thereby acting as a blocking portion against outflow of the brazing filler metal.
次に本発明の主旨を更に具体的に明白にする為
に実施例に基き図面を参照しながら説明する。 Next, in order to clarify the gist of the present invention more specifically, an explanation will be given based on embodiments with reference to the drawings.
第5図は本発明に係る半導体装置の一実施例を
説明する為の断面図である。 FIG. 5 is a sectional view for explaining one embodiment of the semiconductor device according to the present invention.
第5図に示す如く、スタツド(放熱体)16
(例えば放熱性のよい銅)に通常の積層セラミツ
ク技術に基いた絶縁壁部材17(例えばアルミ
ナ)(該絶縁部材17には容器の電極となるべき
メタライズ層18及び前記スタツド16にろう付
する為のメタライズ層18′が設けられている)
をろう付し、この壁部材の上側に外部引出リード
13をろう付して容器を形成し、該容器の内部に
半導体素子19(例えばトランジスタ)をマウン
トし金属細線(例えば金線)20,20′によつ
て前記半導体素子19の電極と該半導体容器とを
電気的に接続してなる半導体装置例えばFETに
於いて、スタツド16と絶縁壁部材17とをろう
材14(例えば銀銅共晶ろう)でろう付の際に、
スタツド16のろう付部分のみに選択的にろう材
14が濡れ易い金属層15(例えばNi)をクラ
ツドしておくとろう材14が容器の内部に流れこ
まないので、半導体素子19のマウント部および
金属細線20′のボンデイング部に対して著しく
信頼度が増す。 As shown in FIG. 5, a stud (heat sink) 16
(for example, copper with good heat dissipation) and an insulating wall member 17 (for example, alumina) based on ordinary laminated ceramic technology (the insulating member 17 includes a metallized layer 18 that will become the electrode of the container and a layer for brazing to the stud 16). metallized layer 18' is provided)
A container is formed by brazing the external lead 13 on the upper side of this wall member, and a semiconductor element 19 (for example, a transistor) is mounted inside the container, and thin metal wires (for example, gold wire) 20, 20 are mounted. In a semiconductor device, such as an FET, in which the electrode of the semiconductor element 19 and the semiconductor container are electrically connected through ) when brazing,
If only the brazed portion of the stud 16 is selectively covered with a metal layer 15 (for example, Ni) that is easily wetted by the brazing filler metal 14, the brazing filler metal 14 will not flow into the container, and the mounting portion of the semiconductor element 19 and The reliability of the bonding portion of the thin metal wire 20' is significantly increased.
本実施例に於いては部分的にとくに壁部材底面
が当接される場所に選択的にろう材14が濡れ易
い金属層15をスタツド16上にあえて設けてい
るが、これは金属層15のみに集中してろう材が
もり上がるようにして壁部材17との接続強度を
向上させることにある。尚ろう材の流れ防止の為
にろう流れ防止剤の塗布とか、或いは硝子とか酸
化層を部分的に設ける等の方法も考えられるが、
ろう流れ防止剤の塗布、除去に高度の技術が要求
されるし、又硝子とか酸化層の設置は酸化雰囲気
還元雰囲気のサイクルによる材質劣化を誘起し、
且つ該層の設置、除去等に高度の技術が要求され
る事、及び両技術共に著しい工数がかかる等の理
由により望ましい方法とは言えない。 In this embodiment, a metal layer 15 to which the brazing filler metal 14 easily wets is selectively provided on the stud 16 at a location where the bottom surface of the wall member comes into contact, but this is only the metal layer 15. The purpose is to improve the connection strength with the wall member 17 by making the brazing filler metal rise up in a concentrated manner. In order to prevent the flow of the solder metal, methods such as applying a solder flow prevention agent or partially providing a glass or oxidized layer may also be considered.
Highly sophisticated techniques are required to apply and remove the wax flow preventive agent, and the installation of glass or oxide layers induces material deterioration due to the cycle of oxidizing and reducing atmospheres.
Furthermore, this method cannot be said to be a desirable method because a high level of skill is required to install and remove the layer, and both techniques require a significant number of man-hours.
しかし、本発明によれば、被ろう付体及びその
近接する部材の機械的、電気的諸特性を劣化せし
めることなく、所定のろう付強度を極めて容易に
確保することができるろう付方法が与えられ、前
記した従来の諸欠点がことごとく解消される。 However, according to the present invention, a brazing method is provided that can extremely easily ensure a predetermined brazing strength without deteriorating the mechanical and electrical properties of the object to be brazed and its adjacent members. This eliminates all of the conventional drawbacks mentioned above.
以上本発明はその良好な実施例について説明さ
れたが、それは単なる例示的なものであつて制限
的意味を有するものではないことは勿論である。
従つて本発明の精神及び範囲から逸脱することな
しに本発明は種々の変更を加えて実施し得るが、
それらはすべて前記した本願特許請求の範囲内に
包含されるものである。 Although the present invention has been described above with respect to its preferred embodiments, it goes without saying that these are merely illustrative and do not have a limiting meaning.
Accordingly, the present invention may be practiced with various modifications without departing from the spirit and scope of the invention,
All of these are intended to be included within the scope of the claims set forth above.
第1図はろう付技術に於ける基本図、第2〜第
4図は従来のろう付技術を説明する為の図、第5
図は本発明に係るろう付構造を用いた半導体装置
の一実施例の断面図である。
1……絶縁基板、2,12……メタライズ層、
3,13……外部引出リード、4,14……ろう
材、5,15……ろう材が濡れ易い金属層、16
……スタツド、17……絶縁壁部材、18……メ
タライズ層、19……半導体素子、20……金属
細線。
Figure 1 is a basic diagram of brazing technology, Figures 2 to 4 are diagrams for explaining conventional brazing technology, and Figure 5 is a basic diagram of brazing technology.
The figure is a sectional view of an embodiment of a semiconductor device using a brazing structure according to the present invention. 1... Insulating substrate, 2, 12... Metallized layer,
3, 13... External drawer lead, 4, 14... Brazing metal, 5, 15... Metal layer to which the brazing metal is easily wetted, 16
... Stud, 17 ... Insulating wall member, 18 ... Metallized layer, 19 ... Semiconductor element, 20 ... Metal thin wire.
Claims (1)
し壁部材を有する半導体装置において、前記壁部
材の底面と対向する前記金属体表面に選択的にろ
う材が濡れ易い金属部材を設けて、その部分で壁
部材をろう付したことを特徴とする半導体装置。1. In a semiconductor device that encapsulates a semiconductor element mounted on a metal body and has a wall member, a metal member that is easily wetted by a brazing material is selectively provided on the surface of the metal body opposite to the bottom surface of the wall member, and that part A semiconductor device characterized in that a wall member is brazed with.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57076942A JPS5890749A (en) | 1982-05-07 | 1982-05-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57076942A JPS5890749A (en) | 1982-05-07 | 1982-05-07 | Semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP49100939A Division JPS5819385B2 (en) | 1974-09-04 | 1974-09-04 | Rouzukehouhou |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5890749A JPS5890749A (en) | 1983-05-30 |
| JPS6236392B2 true JPS6236392B2 (en) | 1987-08-06 |
Family
ID=13619792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57076942A Granted JPS5890749A (en) | 1982-05-07 | 1982-05-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5890749A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4734747B2 (en) * | 2001-04-06 | 2011-07-27 | ミツミ電機株式会社 | Current limiting circuit and power supply circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5819385B2 (en) * | 1974-09-04 | 1983-04-18 | 日本電気株式会社 | Rouzukehouhou |
-
1982
- 1982-05-07 JP JP57076942A patent/JPS5890749A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5890749A (en) | 1983-05-30 |
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