JPS6237426B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention determines the priority order of control order processing when controlling a peripheral processing unit rather than a central processing unit, so that control with higher urgency can be performed first. The present invention relates to an inter-device control system.

(b) Prior art and problems Figures 1 and 2 are diagrams showing a conventional example, in which 1 is a central processing unit, 2 is a receiving circuit, and 3 is a first
In-first-out buffer circuit, 4
1 is a buffer control circuit, 5 is a processing circuit, 9 is a peripheral processing device, and 10 is a control bus.

Conventional inter-device control systems include a system in which control orders are processed immediately after they are received, as shown in Figure 1, and a system in which control orders are stored in a buffer memory once and then processed in the order in which they arrive, as shown in Figure 2. However, in the former case, the control order must be processed immediately after receiving it, and the processing results must be reported to the central control unit, i.e., an answer must be given to the central control unit, and the peripheral processing unit side must prioritize the processing of the control order. There is a disadvantage that it must be done. Furthermore, the latter has the disadvantage that even highly urgent control orders have to wait in the buffer memory until their turn arrives, resulting in a delay in processing.

(c) Object of the Invention The object of the present invention is to provide a device that eliminates the above-mentioned drawbacks, reduces the burden of control order processing on peripheral processing devices, and can process control orders with high priority faster than other control orders. The purpose of the present invention is to provide a method for controlling the time.

(d) Structure of the Invention According to the present invention, the above objects are as follows: 1. A central processing unit and a plurality of peripheral processing units are connected by a control bus, and the central processing unit sends control orders to the control bus, and the peripheral processing units In a data processing system that controls a processing device, each peripheral processing device includes a receiving circuit that receives the control order from the control bus, a determination circuit that determines the processing priority of the control order, and a first In first, out buffer circuit,
Based on the output of the determination circuit, if the priority is low, the control order is stored in the first-in-first-out buffer circuit in the order of arrival; if the priority is high, it is stored in the first-in-first-out buffer circuit. A control bus interface circuit and a processing circuit are provided, each of which includes a buffer control circuit for storage at the head position on the output side, and the processing circuit is configured to store the first-in, first-out buffer of the control bus interface circuit. An inter-device control method characterized by sequentially reading and executing the contents of a circuit at regular intervals.

2. In a data processing system in which a central processing unit and a plurality of peripheral processing units are connected via a control bus, and the central processing unit sends control orders to the control bus to control the peripheral processing units, the peripheral processing units a receiving circuit that receives the control order from the control bus, a first-in-first-out buffer circuit, and a buffer control that stores the control order in the first-in-first-out buffer circuit in the order of arrival. A control bus interface circuit and a processing circuit, each comprising a circuit and an interrupt circuit that determines the processing priority of the control order output from the receiving circuit and generates an interrupt signal if the priority is high. If there is no interrupt signal from the control bus interface circuit, the processing circuit reads the first-in, first-out buffer circuit sequentially at regular intervals, executes the read control order, and receives an interrupt signal. If there is an interrupt signal, the process is interrupted when an interrupt signal is generated, and the first-in-first-out buffer circuit is read until the control order with a high priority is detected, and the control order with a high priority is given priority over other control orders. This is achieved by providing an inter-device control method that is characterized in that it is executed.

(e) Embodiments of the invention The present invention determines the priority of control order processing;
Control orders with low priority are sequentially stored in the buffer memory, and peripheral processing units continue to process them at regular intervals, reducing the burden of processing control orders, and control orders with high priority are processed more quickly than other control orders. It is also designed so that it can be processed with priority.

FIG. 3 is a diagram showing an embodiment of the present invention, in which 1 is a central control unit, 2 is a receiving circuit, and 3 is a first
In-first-out buffer circuit (FI/FO buffer circuit), 4 is a buffer control circuit, 5 is a processing circuit, 6 is a control order priority judgment circuit, 8 is a control bus interface circuit, 9
1 is a peripheral processing device, and 10 is a control bus.

Below, FIG. 3 will be explained in detail. Central control unit 1 sends control orders to control bus 10 . The peripheral processing device receives the control order in the reception circuit 2, and if it determines that the received control order is addressed to itself, it sends a write signal to the buffer control circuit 4 and also sends a write signal to the FI/FO buffer circuit 3 and the control order. The control order is sent to the priority determination circuit 6. The control order priority determination circuit 6 notifies the buffer control circuit 4 of the determination result. The buffer control circuit 4 outputs a shift signal to the FI/FO buffer circuit 3 to store this control order if it is a low level control order based on the write signal from the reception circuit 2 and the output of the control order priority determination circuit 6. , if it is a high level control order
Sends a reset signal to FI/FO buffer circuit 3
After emptying the FI/FO buffer circuit 3, a shift-in signal is issued to store this high-priority control order at the head of the FI/FO buffer circuit 3. The processing circuit 5 issues a read signal to the buffer control circuit 4 at regular intervals, and the buffer control circuit 4 issues a shift out signal to the FI/FO buffer circuit 3 to send a control order to the processing circuit 5. In this way, priority processing is performed.

FIG. 4 is a diagram showing another embodiment of the present invention, in which reference numeral 7 denotes a control order priority determination and interrupt circuit, and other numbers and symbols are the same as in FIG. 3.

The embodiment shown in FIG. 4 differs from the embodiment shown in FIG. 3 in that as a result of priority determination of control orders, if the order is a high-level control order, an interrupt signal is sent to the processing circuit 5. In Fig. 3, the FI/FO buffer circuit 3 is reset when it is determined that the level is high, so the data stored up to that point will be discarded, but in the embodiment shown in Fig. 4, the FI/FO buffer circuit 3 is reset.
Since the FI/FO buffer circuit 3 is not reset, there is an advantage that data loss can be prevented.

(f) Effects of the Invention As described in detail above, according to the present invention, by storing control orders in the FI/FO buffer circuit, the burden of processing control orders on peripheral processing devices can be reduced, and the burden of processing orders with high urgency can be reduced. Control orders can be processed with priority, so in case of an emergency, for example, troubleshooting or restarting the system can be carried out quickly, so it is possible to improve the processing capacity of peripheral processing equipment and restart the system quickly. There are great effects that can be achieved.

[Brief explanation of the drawing]

1 and 2 are diagrams showing conventional examples, in which 1 is a central processing unit, 2 is a receiving circuit, and 3 is a first
In-first-out buffer circuit, 4
1 is a buffer control circuit, 5 is a processing circuit, 9 is a peripheral processing device, and 10 is a control bus. FIG. 3 is a diagram showing an embodiment of the present invention, in which 1 is a central control unit, 2 is a receiving circuit, and 3 is a first
In-first-out buffer circuit, 4
5 is a buffer control circuit, 5 is a processing circuit, 6 is a control order priority determination circuit, 8 is a control bus interface circuit, 9 is a peripheral processing device, and 10 is a control bus. FIG. 4 is a diagram showing another embodiment of the present invention, in which reference numeral 7 denotes a control order priority determination and interrupt circuit, and other numbers and symbols are the same as in FIG. 3.

Claims (1)

[Claims] 1. A data processing system in which a central processing unit and a plurality of peripheral processing units are connected via a control bus, and the central processing unit sends control orders to the control bus to control the peripheral processing units. a receiving circuit that receives the control order from the control bus, a determination circuit that determines the processing priority of the control order, and a first-in-first-out buffer circuit for each peripheral processing device; Based on the output of the determination circuit, if the priority is low, the control order is stored in the first-in-first-out buffer circuit in the order of arrival; if the priority is high, it is stored in the first-in-first-out buffer circuit. A control bus interface circuit and a processing circuit are provided, each of which includes a buffer control circuit for storage at the head position on the output side, and the processing circuit is configured to store the first-in, first-out buffer of the control bus interface circuit. An inter-device control method characterized by sequentially reading and executing the contents of a circuit at regular intervals. 2. In a data processing system in which a central processing unit and a plurality of peripheral processing units are connected via a control bus, and the central processing unit sends control orders to the control bus to control the peripheral processing units, the peripheral processing units a receiving circuit that receives the control order from the control bus, a first-in-first-out buffer circuit, and a buffer control that stores the control order in the first-in-first-out buffer circuit in the order of arrival. A control bus interface circuit and a processing circuit, each comprising a circuit, an interrupt circuit that determines the processing priority of the control order output from the receiving circuit, and generates an interrupt signal if the priority is high. If there is no interrupt signal from the control bus interface circuit, the processing circuit reads the first-in, first-out buffer circuit sequentially at a fixed period and executes the read control order, and when there is no interrupt signal, If there is an interrupt signal, the process is interrupted when an interrupt signal is generated, and the first-in-first-out buffer circuit is read until the control order with a high priority is detected, and the control order with a high priority is given priority over other control orders. An inter-device control method characterized by: