JPS6237476B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a redundant/normal bit switching circuit.

Recently, the capacity of semiconductor devices has been rapidly increasing at a pace of approximately doubling every two years. However, as capacity increases, the pattern becomes finer and the chip area increases, resulting in problems such as dust scratches, dimensional variations, and diffusion variations that occur during the manufacturing process.
The probability that IC chips will contain defects has increased, thereby reducing yield.

When we examine the details of defects in defective chips, we find that in memory devices, only a certain number of bits are often defective.This means that if redundancy can be provided to memory bits, IC chips that are currently defective can be eliminated. Many of these bits can be saved and yields can be significantly improved, but this requires a switching circuit that avoids defective bits.

Conventional ultraviolet erasable semiconductor devices with redundant bits use polycrystalline silicon fuses in their switching circuits (Nikkei Electronics).
1980.7.21 P.189-201) It is common to select redundant bits or regular bits depending on whether or not they will melt due to the Joule heat generated by applying large current and high voltage to them. It was hot.

FIG. 1 is a circuit diagram of an example of a conventional redundant/regular bit switching circuit.

This example is an N-channel stacked gate type.
This is an example of a switching circuit for a memory device using an MIS transistor (hereinafter referred to as SGMISFET). In FIG. 1, Vcc is a power supply voltage, and Vpp is a write voltage, to which normally 5V and 20 to 25V are applied, respectively. As long as no defective bit is detected, node _N11 is kept at a high level by the pull-up resistor of transistor _Q11 , transistor _Q14 is off, and transistors _Q16 , _Q15 are configured by polycrystalline silicon fuse 1. Node N ₁₄ due to resistance division of the current path
It is designed to produce low levels. This turns off transistor _Q19 and turns on transistor _Q1A . That is, the regular bits are selected and the redundant bits are not selected.

Next, when a defective bit is detected, a low level signal is applied to the terminal from the outside, turning on the transistor _Q14 . As a result, a current is supplied from the Vpp terminal to the polycrystalline silicon fuse 1 through the transistor _Q14 , and the polycrystalline silicon fuse 1 is blown out by Joule heat generated at this time. Here, the transistor _Q15 is a transistor that prevents the current supplied from the Vpp terminal from flowing into the node _N14 . Next, when the signal is removed, transistor Q ₁₄ is turned off, and the current path of previously formed transistors Q ₁₆ , Q ₁₅ and the polycrystalline silicon fuse is broken, so that node N ₁₄ is always high and node N ₁₅ is always low. level and transistor Q ₁₉
is turned on, transistor _Q1A is turned off, and the regular matrix is switched to the redundant matrix.

However, in switching circuits using such polycrystalline silicon fuses, it is necessary to apply large currents and high voltages in order to blow the fuses, and in order to withstand these, the junction breakdown voltage and the generation transistor in the field region must be increased. threshold,
Design consideration must be given to the current capacity of the wiring, etc. Further, a certain distance is required so that the transistors and polycrystalline silicon interconnection layers disposed in the periphery are not affected by the Joule heat generated at the time of fusing. It is also necessary to consider the possibility that silicon scattered by heat may affect other elements, and to keep other elements sufficiently away from the fuse. Furthermore, sufficient wiring current capacity is required to supply the polycrystalline silicon fuse with the current necessary for blowing. For example, if 1W is required to blow a polycrystalline silicon fuse, if Vpp = 25V, a current of 40mA will flow, and if the wiring layer is made of Al and has a thickness of 1.0μm, then
A width of 40 μm is required, resulting in a huge Al wiring pattern. Furthermore, the thermal stress generated when the fuse blows damages the passivation film above the fuse, contaminating the chip and causing serious reliability problems.

In this way, in switching circuits using conventional polycrystalline silicon fuses, the Al wiring becomes huge, which takes up the area for forming the elements, reducing the integration density. There were serious drawbacks, such as the element integration density being further reduced due to the separation of the elements, and the reliability of the element being reduced due to contamination of the silicon layer scattered during fusing.

The present invention eliminates the above drawbacks and provides a semiconductor device including a redundant/regular bit switching circuit that improves integration density and reliability by using stacked gate MIS transistors instead of polycrystalline silicon fuses. It is something to do.

The semiconductor device of the present invention is connected in series between a write power supply terminal and a ground terminal. An MIS transistor having an enhancement type transistor, a depletion type transistor, and a charge trapping layer, and a gate of the MIS transistor having the charge trapping layer is connected to a source/drain connection point of the enhancement type transistor and the depletion type transistor. a first node, an MIS diode connected between the first node and a power supply terminal, and an inverter whose output is connected to the gate of the enhancement transistor;
A pull-up resistor connected to a connection line between the repair terminal and the input terminal of the inverter, and a level connected to a second node formed by the connection between the depletion type transistor and the MIS transistor having the charge trapping layer. The redundant/regular bit switching circuit includes a shaping circuit and a transfer gate connected to the shaping circuit and controlled by a signal output to the second node.

Next, embodiments of the present invention will be described using the drawings.

FIG. 2 is a circuit diagram of one embodiment of the present invention.

The redundant/regular bit switching circuit of this embodiment includes an enhancement type transistor _Q24 connected in series between the write power supply terminal Vpp terminal and the ground terminal.
The gate of the MIS transistor Q ₂₆ having a charge trapping layer is connected to the source/drain connection point of the depletion type transistor Q ₂₅ and the MIS transistor Q ₂₆ having a charge trapping layer _, and the enhancement type transistor Q 24 and the depletion type transistor Q ₂₅ . a first node N ₂₃ formed by
an inverter consisting of an MIS diode Q ₂₇ connected between node N ₂₃ and the power supply terminal (Vcc terminal), and transistors Q ₂₂ and Q ₂₃ , the output of which is connected to the gate of an enhancement transistor Q ₂₄ ; Pull-up resistor connected to the connection line between the repair terminal and the input terminal of the inverter
Q ₁ and a second node N ₂₄ formed by connecting a depletion type transistor Q ₂₅ and a MIS transistor Q ₂₆ having a charge trapping layer, and consisting of transistors Q ₂₈ and Q ₂₉ , or a transistor Q _2A. and a level shaping circuit consisting of _Q2B ,
A transfer gate Q connected to this shaping circuit and controlled by a signal output to the second node _N24
It is constructed by including a redundant/regular bit switching circuit including _2D or _Q2C , and this switching circuit is incorporated into a semiconductor device.

Next, the operation of this embodiment will be explained.

Vcc is used with a power supply voltage of 5V, and the same voltage is applied during both writing and reading. Vpp is a write power supply voltage, and normally 20V to 25V is applied during writing, and 5V during reading. The node _N21 of the terminal is set to a high level by the pull-up transistor _Q21 . During a non-defective product check, this state is maintained and transistor _Q24 is turned off unless a defect is found in a regular bit. As a result, transistors Q ₂₅ and Q ₂₆ are connected from the Vcc terminal.
Voltage is supplied through Q ₂₇ . transistor
Q ₂₆ is a memory transistor, which is turned on when a voltage is applied to the control gate when no writing is being performed, and N ₂₄ is at a low level.
Therefore, node _N25 becomes high level and node _N26 becomes low level, transfer gate _Q2C is turned on and transfer gate _Q2D is turned off, and the normal bit is selected. Next, when a defective bit is found among the regular bits during a non-defective item check, a signal for forcibly lowering the level to a low level is input to the terminal from the outside. Transistor Q ₂₂ ,
This signal is inverted by the inverter formed by Q ₂₃ , turning on transistor Q ₂₄ and applying the write voltage Vpp to the write transistor load of transistor Q ₂₅ , which
The memory cell _Q26 is programmed by channel injection, the threshold voltage increases from 1.0V to around 20V, and transistor _Q26 is completely turned off. Thereafter, when the signal is removed, the transistor _Q24 is turned off again, and the power supply voltage Vcc is applied to the transistor _Q25 via the MIS type diode _Q27 . Transistor Q ₂₆ is turned off due to the threshold value of 2.0V due to the above operation, the second node N ₂₄ is at a high level, the node N ₂₅ is at a low level, and the node N ₂₆ is at a high level. As a result, transfer gate Q
_2C is turned off and transfer gate _Q2D is turned on, meaning that the regular bit is switched to the redundant bit.

As explained in detail above, according to the present invention,
This is highly effective because it provides a semiconductor device including a redundant/normal bit switching circuit that can perform redundant/normal bit switching without requiring large currents and thus improves integration density and reliability.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an example of a conventional redundant/regular bit switching circuit, and FIG. 2 is a circuit diagram of an embodiment of the present invention. 1...Polycrystalline silicon fuse, _Q2C , _Q2D ...
...transfer gate, Q ₂₁ ... pull-up resistor, Q ₂₄ ... enhancement type transistor,
Q ₂₅ ... depletion type transistor, Q ₂₆ ...
...MIS transistor with charge trapping layer, Q ₂₇ ...
...MIS type diode, Vcc...power supply voltage, Vpp...
...Write voltage, _N23 ...First node, _N24 ...Second node.

Claims (1)

[Claims] 1 An enhancement type transistor, a depletion type transistor, and a charge trapping layer are connected in series between a write power supply terminal and a ground terminal.
an MIS transistor; a first node formed by connecting the gate of the MIS transistor having the charge trapping layer to a source/drain connection point of the enhancement type transistor and the depletion type transistor; and a power source connected to the first node; an inverter whose output is connected to the gate of the enhancement transistor; a pull-up resistor connected to a connection line between the repair terminal and the input terminal of the inverter; a level shaping circuit connected to a second node formed by connecting the depletion type transistor and the MIS transistor having the charge trapping layer;
1. A semiconductor device comprising a redundant/regular bit switching circuit including a transfer gate controlled by a signal output to a node.